| /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */ |
| |
| module grid_clb(SC_IN_TOP, SC_OUT_BOT, SC_OUT_TOP, Test_en_E_in, Test_en_E_out, Test_en_W_in, Test_en_W_out, bottom_width_0_height_0__pin_50_, bottom_width_0_height_0__pin_51_, ccff_head, ccff_tail, clk_0_N_in, clk_0_S_in, prog_clk_0_E_out, prog_clk_0_N_in, prog_clk_0_N_out, prog_clk_0_S_in, prog_clk_0_S_out, prog_clk_0_W_out, right_width_0_height_0__pin_16_, right_width_0_height_0__pin_17_, right_width_0_height_0__pin_18_, right_width_0_height_0__pin_19_, right_width_0_height_0__pin_20_, right_width_0_height_0__pin_21_, right_width_0_height_0__pin_22_, right_width_0_height_0__pin_23_, right_width_0_height_0__pin_24_, right_width_0_height_0__pin_25_, right_width_0_height_0__pin_26_, right_width_0_height_0__pin_27_, right_width_0_height_0__pin_28_, right_width_0_height_0__pin_29_, right_width_0_height_0__pin_30_, right_width_0_height_0__pin_31_, right_width_0_height_0__pin_42_lower, right_width_0_height_0__pin_42_upper, right_width_0_height_0__pin_43_lower, right_width_0_height_0__pin_43_upper, right_width_0_height_0__pin_44_lower, right_width_0_height_0__pin_44_upper, right_width_0_height_0__pin_45_lower, right_width_0_height_0__pin_45_upper, right_width_0_height_0__pin_46_lower, right_width_0_height_0__pin_46_upper, right_width_0_height_0__pin_47_lower, right_width_0_height_0__pin_47_upper, right_width_0_height_0__pin_48_lower, right_width_0_height_0__pin_48_upper, right_width_0_height_0__pin_49_lower, right_width_0_height_0__pin_49_upper, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_11_, top_width_0_height_0__pin_12_, top_width_0_height_0__pin_13_, top_width_0_height_0__pin_14_, top_width_0_height_0__pin_15_, top_width_0_height_0__pin_1_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_32_, top_width_0_height_0__pin_33_, top_width_0_height_0__pin_34_lower, top_width_0_height_0__pin_34_upper, top_width_0_height_0__pin_35_lower, top_width_0_height_0__pin_35_upper, top_width_0_height_0__pin_36_lower, top_width_0_height_0__pin_36_upper, top_width_0_height_0__pin_37_lower, top_width_0_height_0__pin_37_upper, top_width_0_height_0__pin_38_lower, top_width_0_height_0__pin_38_upper, top_width_0_height_0__pin_39_lower, top_width_0_height_0__pin_39_upper, top_width_0_height_0__pin_3_, top_width_0_height_0__pin_40_lower, top_width_0_height_0__pin_40_upper, top_width_0_height_0__pin_41_lower, top_width_0_height_0__pin_41_upper, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_5_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_7_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_9_, VPWR, VGND); |
| input SC_IN_TOP; |
| output SC_OUT_BOT; |
| output SC_OUT_TOP; |
| input Test_en_E_in; |
| output Test_en_E_out; |
| input Test_en_W_in; |
| output Test_en_W_out; |
| input VGND; |
| input VPWR; |
| wire _00_; |
| wire _01_; |
| wire _02_; |
| wire _03_; |
| wire _04_; |
| wire _05_; |
| wire _06_; |
| wire _07_; |
| wire _08_; |
| wire _09_; |
| wire _10_; |
| wire _11_; |
| wire _12_; |
| wire _13_; |
| wire _14_; |
| wire _15_; |
| wire _16_; |
| wire _17_; |
| wire _18_; |
| wire _19_; |
| wire _20_; |
| wire _21_; |
| wire _22_; |
| wire _23_; |
| wire _24_; |
| wire _25_; |
| wire _26_; |
| wire _27_; |
| wire _28_; |
| wire _29_; |
| wire _30_; |
| wire _31_; |
| output bottom_width_0_height_0__pin_50_; |
| output bottom_width_0_height_0__pin_51_; |
| input ccff_head; |
| output ccff_tail; |
| input clk_0_N_in; |
| input clk_0_S_in; |
| wire \clknet_0_ltile_clb_mode__0.clb_clk ; |
| wire \clknet_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_1_0_0_ltile_clb_mode__0.clb_clk ; |
| wire \clknet_1_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_1_1_0_ltile_clb_mode__0.clb_clk ; |
| wire \clknet_1_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_2_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_2_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_2_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_2_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_3_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_3_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_3_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_3_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_3_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_3_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_3_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_3_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_12_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_8_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \ltile_clb_mode__0.Test_en ; |
| wire \ltile_clb_mode__0.clb_clk ; |
| wire \ltile_clb_mode__0.direct_interc_29_.in ; |
| wire \ltile_clb_mode__0.direct_interc_36_.in ; |
| wire \ltile_clb_mode__0.direct_interc_43_.in ; |
| wire \ltile_clb_mode__0.direct_interc_50_.in ; |
| wire \ltile_clb_mode__0.direct_interc_57_.in ; |
| wire \ltile_clb_mode__0.direct_interc_64_.in ; |
| wire \ltile_clb_mode__0.direct_interc_71_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.direct_interc_8_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.direct_interc_9_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.direct_interc_8_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.direct_interc_9_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.direct_interc_8_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.direct_interc_9_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.direct_interc_8_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.direct_interc_9_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.direct_interc_8_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.direct_interc_9_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.direct_interc_8_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.direct_interc_9_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.direct_interc_8_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.direct_interc_9_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.direct_interc_8_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.direct_interc_9_.in ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ; |
| wire \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ; |
| output prog_clk_0_E_out; |
| input prog_clk_0_N_in; |
| output prog_clk_0_N_out; |
| input prog_clk_0_S_in; |
| output prog_clk_0_S_out; |
| output prog_clk_0_W_out; |
| input right_width_0_height_0__pin_16_; |
| input right_width_0_height_0__pin_17_; |
| input right_width_0_height_0__pin_18_; |
| input right_width_0_height_0__pin_19_; |
| input right_width_0_height_0__pin_20_; |
| input right_width_0_height_0__pin_21_; |
| input right_width_0_height_0__pin_22_; |
| input right_width_0_height_0__pin_23_; |
| input right_width_0_height_0__pin_24_; |
| input right_width_0_height_0__pin_25_; |
| input right_width_0_height_0__pin_26_; |
| input right_width_0_height_0__pin_27_; |
| input right_width_0_height_0__pin_28_; |
| input right_width_0_height_0__pin_29_; |
| input right_width_0_height_0__pin_30_; |
| input right_width_0_height_0__pin_31_; |
| output right_width_0_height_0__pin_42_lower; |
| output right_width_0_height_0__pin_42_upper; |
| output right_width_0_height_0__pin_43_lower; |
| output right_width_0_height_0__pin_43_upper; |
| output right_width_0_height_0__pin_44_lower; |
| output right_width_0_height_0__pin_44_upper; |
| output right_width_0_height_0__pin_45_lower; |
| output right_width_0_height_0__pin_45_upper; |
| output right_width_0_height_0__pin_46_lower; |
| output right_width_0_height_0__pin_46_upper; |
| output right_width_0_height_0__pin_47_lower; |
| output right_width_0_height_0__pin_47_upper; |
| output right_width_0_height_0__pin_48_lower; |
| output right_width_0_height_0__pin_48_upper; |
| output right_width_0_height_0__pin_49_lower; |
| output right_width_0_height_0__pin_49_upper; |
| input top_width_0_height_0__pin_0_; |
| input top_width_0_height_0__pin_10_; |
| input top_width_0_height_0__pin_11_; |
| input top_width_0_height_0__pin_12_; |
| input top_width_0_height_0__pin_13_; |
| input top_width_0_height_0__pin_14_; |
| input top_width_0_height_0__pin_15_; |
| input top_width_0_height_0__pin_1_; |
| input top_width_0_height_0__pin_2_; |
| input top_width_0_height_0__pin_32_; |
| input top_width_0_height_0__pin_33_; |
| output top_width_0_height_0__pin_34_lower; |
| output top_width_0_height_0__pin_34_upper; |
| output top_width_0_height_0__pin_35_lower; |
| output top_width_0_height_0__pin_35_upper; |
| output top_width_0_height_0__pin_36_lower; |
| output top_width_0_height_0__pin_36_upper; |
| output top_width_0_height_0__pin_37_lower; |
| output top_width_0_height_0__pin_37_upper; |
| output top_width_0_height_0__pin_38_lower; |
| output top_width_0_height_0__pin_38_upper; |
| output top_width_0_height_0__pin_39_lower; |
| output top_width_0_height_0__pin_39_upper; |
| input top_width_0_height_0__pin_3_; |
| output top_width_0_height_0__pin_40_lower; |
| output top_width_0_height_0__pin_40_upper; |
| output top_width_0_height_0__pin_41_lower; |
| output top_width_0_height_0__pin_41_upper; |
| input top_width_0_height_0__pin_4_; |
| input top_width_0_height_0__pin_5_; |
| input top_width_0_height_0__pin_6_; |
| input top_width_0_height_0__pin_7_; |
| input top_width_0_height_0__pin_8_; |
| input top_width_0_height_0__pin_9_; |
| sky130_fd_sc_hd__diode_2 ANTENNA_Test_en_E_FTB01_A ( |
| .DIODE(Test_en_E_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA_Test_en_FTB00_A ( |
| .DIODE(Test_en_E_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA_Test_en_W_FTB01_A ( |
| .DIODE(Test_en_E_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__65__A ( |
| .DIODE(SC_OUT_BOT), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__66__A ( |
| .DIODE(SC_OUT_BOT), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__67__A ( |
| .DIODE(right_width_0_height_0__pin_42_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__68__A ( |
| .DIODE(right_width_0_height_0__pin_43_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__69__A ( |
| .DIODE(right_width_0_height_0__pin_44_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__70__A ( |
| .DIODE(right_width_0_height_0__pin_45_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__71__A ( |
| .DIODE(right_width_0_height_0__pin_46_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__72__A ( |
| .DIODE(right_width_0_height_0__pin_47_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__73__A ( |
| .DIODE(right_width_0_height_0__pin_48_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__74__A ( |
| .DIODE(right_width_0_height_0__pin_49_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__75__A ( |
| .DIODE(top_width_0_height_0__pin_34_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__76__A ( |
| .DIODE(top_width_0_height_0__pin_35_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__77__A ( |
| .DIODE(top_width_0_height_0__pin_36_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__78__A ( |
| .DIODE(top_width_0_height_0__pin_37_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__79__A ( |
| .DIODE(top_width_0_height_0__pin_38_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__80__A ( |
| .DIODE(top_width_0_height_0__pin_39_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__81__A ( |
| .DIODE(top_width_0_height_0__pin_40_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA__82__A ( |
| .DIODE(top_width_0_height_0__pin_41_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA_clk_0_FTB00_A ( |
| .DIODE(clk_0_N_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0__SCD ( |
| .DIODE(SC_IN_TOP), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0__A ( |
| .DIODE(top_width_0_height_0__pin_0_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1__A ( |
| .DIODE(top_width_0_height_0__pin_1_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2__A ( |
| .DIODE(top_width_0_height_0__pin_2_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0__B ( |
| .DIODE(top_width_0_height_0__pin_3_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0__D ( |
| .DIODE(ccff_head), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l1_in_0__A0 ( |
| .DIODE(top_width_0_height_0__pin_32_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0__A ( |
| .DIODE(top_width_0_height_0__pin_4_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1__A ( |
| .DIODE(top_width_0_height_0__pin_5_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2__A ( |
| .DIODE(top_width_0_height_0__pin_6_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0__B ( |
| .DIODE(top_width_0_height_0__pin_7_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0__A ( |
| .DIODE(top_width_0_height_0__pin_8_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1__A ( |
| .DIODE(top_width_0_height_0__pin_9_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2__A ( |
| .DIODE(top_width_0_height_0__pin_10_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0__B ( |
| .DIODE(top_width_0_height_0__pin_11_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0__A ( |
| .DIODE(top_width_0_height_0__pin_12_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1__A ( |
| .DIODE(top_width_0_height_0__pin_13_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2__A ( |
| .DIODE(top_width_0_height_0__pin_14_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0__B ( |
| .DIODE(top_width_0_height_0__pin_15_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0__A ( |
| .DIODE(right_width_0_height_0__pin_16_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1__A ( |
| .DIODE(right_width_0_height_0__pin_17_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2__A ( |
| .DIODE(right_width_0_height_0__pin_18_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0__B ( |
| .DIODE(right_width_0_height_0__pin_19_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0__A ( |
| .DIODE(right_width_0_height_0__pin_20_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1__A ( |
| .DIODE(right_width_0_height_0__pin_21_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2__A ( |
| .DIODE(right_width_0_height_0__pin_22_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0__B ( |
| .DIODE(right_width_0_height_0__pin_23_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0__A ( |
| .DIODE(right_width_0_height_0__pin_24_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1__A ( |
| .DIODE(right_width_0_height_0__pin_25_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2__A ( |
| .DIODE(right_width_0_height_0__pin_26_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0__B ( |
| .DIODE(right_width_0_height_0__pin_27_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0__SCE ( |
| .DIODE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0__A ( |
| .DIODE(right_width_0_height_0__pin_28_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1__A ( |
| .DIODE(right_width_0_height_0__pin_29_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2__A ( |
| .DIODE(right_width_0_height_0__pin_30_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0__B ( |
| .DIODE(right_width_0_height_0__pin_31_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 \ANTENNA_ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_fabric_out_1.mux_l1_in_0__A1 ( |
| .DIODE(SC_OUT_BOT), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA_prog_clk_0_E_FTB01_A ( |
| .DIODE(prog_clk_0_N_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA_prog_clk_0_FTB00_A ( |
| .DIODE(prog_clk_0_N_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA_prog_clk_0_N_FTB01_A ( |
| .DIODE(prog_clk_0_N_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA_prog_clk_0_S_FTB01_A ( |
| .DIODE(prog_clk_0_N_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__diode_2 ANTENNA_prog_clk_0_W_FTB01_A ( |
| .DIODE(prog_clk_0_N_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_0_106 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_0_118 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_0_125 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_0_137 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_0_149 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_0_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_0_156 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_0_168 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_0_180 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_0_203 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_0_207 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_0_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_0_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_0_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_0_44 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_0_56 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_0_63 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_0_75 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_0_87 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_0_94 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_10_118 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_10_139 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_10_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_10_161 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_10_213 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_10_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_10_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_10_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_10_44 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_10_56 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_10_68 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_10_86 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_11_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_11_239 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_11_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_11_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_11_39 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_11_51 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_11_59 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_11_62 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_11_74 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_11_86 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_12_109 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_12_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_12_217 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_12_239 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_12_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_12_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_12_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_12_44 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_12_56 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_12_68 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_12_80 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_13_108 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_13_112 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_13_139 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_13_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_13_161 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_13_228 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_13_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_13_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_13_39 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_13_51 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_13_59 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_13_62 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_13_74 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_13_86 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_13_92 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_13_96 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_14_111 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_14_119 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_14_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_14_170 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_14_199 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_14_209 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_14_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_14_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_14_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_14_44 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_14_56 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_14_68 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_14_90 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_15_121 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_15_123 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_15_17 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_15_188 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_15_198 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_15_239 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_15_29 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_15_41 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_15_5 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_15_53 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_15_62 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_15_66 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_15_83 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_16_120 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_16_124 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_16_154 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_16_171 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_16_19 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_16_211 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_16_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_16_44 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_16_56 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_16_90 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_16_93 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_17_117 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_17_121 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_17_123 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_17_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_17_153 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_17_176 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_17_204 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_17_21 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_17_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_17_38 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_17_50 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_17_58 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_17_62 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_17_80 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_18_184 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_18_204 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_18_215 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_18_234 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_18_26 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_18_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_18_30 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_18_9 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_18_96 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_19_102 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_19_127 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_19_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_19_200 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_19_239 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_19_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_19_35 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_19_55 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_19_62 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_19_92 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_1_110 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_1_123 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_1_135 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_1_147 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_1_159 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_1_193 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_1_197 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_1_21 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_1_239 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_1_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_1_33 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_1_45 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_1_51 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_1_55 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_1_62 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_1_74 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_1_86 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_1_98 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_20_147 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_20_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_20_202 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_20_28 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_20_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_20_41 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_20_67 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_21_120 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_21_136 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_21_182 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_21_238 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_21_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_21_42 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_21_66 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_22_163 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_22_211 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_22_219 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_22_23 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_22_239 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_22_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_22_30 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_22_59 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_22_83 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_23_121 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_23_130 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_23_156 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_23_182 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_23_190 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_23_216 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_23_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_23_9 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_24_151 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_24_192 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_24_215 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_24_219 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_24_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_24_30 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_24_64 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_25_121 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_25_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_25_9 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_26_110 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_26_125 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_26_133 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_26_151 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_26_157 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_26_174 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_26_215 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_26_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_26_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_26_36 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_26_62 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_26_93 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_27_120 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_27_139 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_27_156 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_27_168 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_27_180 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_27_209 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_27_220 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_27_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_27_7 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_28_111 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_28_115 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_28_170 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_28_212 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_28_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_28_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_28_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_28_56 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_29_117 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_29_121 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_29_148 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_29_182 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_29_184 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_29_219 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_29_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_29_39 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_29_60 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_2_105 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_2_11 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_2_117 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_2_129 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_2_141 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_2_154 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_2_166 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_2_212 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_2_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_2_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_2_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_2_44 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_2_56 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_2_68 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_2_80 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_2_93 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_30_150 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_30_167 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_30_192 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_30_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_30_58 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_30_91 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_31_113 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_31_116 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_31_139 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_31_184 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_31_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_31_34 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_31_59 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_31_7 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_32_113 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_32_121 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_32_195 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_32_206 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_32_215 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_32_225 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_32_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_32_30 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_33_114 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_33_143 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_33_182 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_33_209 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_33_221 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_33_227 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_33_238 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_33_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_33_43 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_33_60 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_33_87 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_34_147 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_34_202 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_34_215 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_34_227 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_34_87 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_35_168 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_35_182 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_35_201 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_35_213 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_35_225 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_35_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_35_36 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_35_7 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_35_82 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_36_106 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_36_11 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_36_118 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_36_125 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_36_137 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_36_14 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_36_166 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_36_174 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_36_18 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_36_189 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_36_201 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_36_213 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_36_218 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_36_230 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_36_238 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_36_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_36_30 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_36_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_36_38 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_36_43 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_36_61 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_36_65 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_36_78 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_36_90 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_3_110 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_3_123 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_3_135 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_3_147 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_3_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_3_159 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_3_181 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_3_184 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_3_218 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_3_237 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_3_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_3_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_3_39 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_3_51 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_3_59 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_3_62 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_3_74 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_3_86 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_3_98 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_4_114 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_4_126 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_4_138 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_4_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_4_150 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_4_154 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_4_213 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_4_219 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_4_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_4_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_4_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_4_44 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_4_56 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_4_68 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_4_80 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_4_93 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_5_106 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_6 FILLER_5_116 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_5_139 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_5_145 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_5_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_5_157 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_5_177 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_5_211 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_5_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_5_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_5_39 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_5_51 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_5_59 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_5_62 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_5_74 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_5_86 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_5_98 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_6_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_6_163 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_6_191 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_6_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_6_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_6_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_6_44 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_6_56 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_6_68 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_6_80 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_6_93 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_7_117 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_7_121 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_7_123 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_7_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_7_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_7_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_7_39 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_7_51 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_7_59 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_7_62 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_7_74 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_7_82 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_8_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_8_191 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_8_239 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_4 FILLER_8_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_8_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_8_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_8_44 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_8_56 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_8_68 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_8_80 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_9_118 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_9_136 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_9_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_9_200 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_1 FILLER_9_239 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_9_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_9_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_9_39 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_8 FILLER_9_51 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__fill_2 FILLER_9_59 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_9_62 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_12 FILLER_9_74 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 FILLER_9_86 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_0 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_1 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_10 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_100 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_101 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_102 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_103 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_104 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_105 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_106 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_107 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_108 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_109 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_11 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_110 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_111 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_112 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_113 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_114 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_115 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_116 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_117 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_118 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_119 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_12 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_120 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_121 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_122 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_123 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_124 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_125 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_126 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_127 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_128 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_129 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_13 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_130 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_131 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_132 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_133 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_134 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_135 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_136 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_137 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_138 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_139 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_14 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_140 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_141 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_142 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_143 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_144 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_145 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_146 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_147 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_148 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_149 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_15 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_150 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_151 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_152 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_153 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_154 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_155 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_156 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_157 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_158 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_159 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_16 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_160 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_161 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_162 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_163 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_164 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_165 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_166 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_167 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_168 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_169 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_17 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_170 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_171 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_172 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_173 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_174 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_175 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_176 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_177 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_178 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_179 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_18 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_180 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_181 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_182 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_183 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_184 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_185 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_186 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_187 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_188 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_189 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_19 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_190 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_191 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_192 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_193 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_194 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_195 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_196 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_197 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_198 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_199 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_2 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_20 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_200 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_201 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_202 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_203 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_204 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_205 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_206 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_207 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_208 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_209 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_21 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_22 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_23 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_24 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_25 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_26 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_27 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_28 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_29 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_3 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_30 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_31 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_32 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_33 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_34 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_35 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_36 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_37 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_38 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_39 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_4 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_40 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_41 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_42 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_43 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_44 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_45 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_46 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_47 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_48 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_49 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_5 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_50 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_51 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_52 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_53 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_54 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_55 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_56 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_57 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_58 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_59 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_6 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_60 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_61 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_62 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_63 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_64 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_65 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_66 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_67 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_68 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_69 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_7 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_70 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_71 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_72 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_73 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_74 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_75 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_76 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_77 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_78 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_79 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_8 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_80 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_81 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_82 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_83 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_84 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_85 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_86 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_87 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_88 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_89 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__decap_3 PHY_9 ( |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_90 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_91 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_92 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_93 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_94 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_95 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_96 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_97 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_98 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_99 ( |
| .VGND(VGND), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__buf_4 Test_en_E_FTB01 ( |
| .A(Test_en_E_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(Test_en_E_out) |
| ); |
| sky130_fd_sc_hd__buf_8 Test_en_FTB00 ( |
| .A(Test_en_E_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.Test_en ) |
| ); |
| sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( |
| .A(Test_en_E_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(Test_en_W_out) |
| ); |
| sky130_fd_sc_hd__conb_1 _32_ ( |
| .HI(_31_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _33_ ( |
| .HI(_00_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _34_ ( |
| .HI(_01_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _35_ ( |
| .HI(_02_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _36_ ( |
| .HI(_03_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _37_ ( |
| .HI(_04_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _38_ ( |
| .HI(_05_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _39_ ( |
| .HI(_06_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _40_ ( |
| .HI(_07_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _41_ ( |
| .HI(_08_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _42_ ( |
| .HI(_09_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _43_ ( |
| .HI(_10_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _44_ ( |
| .HI(_11_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _45_ ( |
| .HI(_12_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _46_ ( |
| .HI(_13_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _47_ ( |
| .HI(_14_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _48_ ( |
| .HI(_15_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _49_ ( |
| .HI(_16_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _50_ ( |
| .HI(_17_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _51_ ( |
| .HI(_18_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _52_ ( |
| .HI(_19_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _53_ ( |
| .HI(_20_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _54_ ( |
| .HI(_21_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _55_ ( |
| .HI(_22_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _56_ ( |
| .HI(_23_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _57_ ( |
| .HI(_24_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _58_ ( |
| .HI(_25_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _59_ ( |
| .HI(_26_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _60_ ( |
| .HI(_27_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _61_ ( |
| .HI(_28_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _62_ ( |
| .HI(_29_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _63_ ( |
| .HI(_30_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__conb_1 _64_ ( |
| .LO(bottom_width_0_height_0__pin_51_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__buf_2 _65_ ( |
| .A(SC_OUT_BOT), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(SC_OUT_TOP) |
| ); |
| sky130_fd_sc_hd__buf_2 _66_ ( |
| .A(SC_OUT_BOT), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(bottom_width_0_height_0__pin_50_) |
| ); |
| sky130_fd_sc_hd__buf_2 _67_ ( |
| .A(right_width_0_height_0__pin_42_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_42_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _68_ ( |
| .A(right_width_0_height_0__pin_43_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_43_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _69_ ( |
| .A(right_width_0_height_0__pin_44_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_44_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _70_ ( |
| .A(right_width_0_height_0__pin_45_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_45_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _71_ ( |
| .A(right_width_0_height_0__pin_46_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_46_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _72_ ( |
| .A(right_width_0_height_0__pin_47_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_47_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _73_ ( |
| .A(right_width_0_height_0__pin_48_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_48_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _74_ ( |
| .A(right_width_0_height_0__pin_49_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_49_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _75_ ( |
| .A(top_width_0_height_0__pin_34_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_34_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _76_ ( |
| .A(top_width_0_height_0__pin_35_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_35_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _77_ ( |
| .A(top_width_0_height_0__pin_36_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_36_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _78_ ( |
| .A(top_width_0_height_0__pin_37_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_37_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _79_ ( |
| .A(top_width_0_height_0__pin_38_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_38_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _80_ ( |
| .A(top_width_0_height_0__pin_39_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_39_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _81_ ( |
| .A(top_width_0_height_0__pin_40_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_40_upper) |
| ); |
| sky130_fd_sc_hd__buf_2 _82_ ( |
| .A(top_width_0_height_0__pin_41_lower), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_41_upper) |
| ); |
| sky130_fd_sc_hd__buf_8 clk_0_FTB00 ( |
| .A(clk_0_N_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.clb_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_16 \clkbuf_0_ltile_clb_mode__0.clb_clk ( |
| .A(\ltile_clb_mode__0.clb_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_0_ltile_clb_mode__0.clb_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_16 \clkbuf_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_1_0_0_ltile_clb_mode__0.clb_clk ( |
| .A(\clknet_0_ltile_clb_mode__0.clb_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_1_0_0_ltile_clb_mode__0.clb_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_1_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_1_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_1_1_0_ltile_clb_mode__0.clb_clk ( |
| .A(\clknet_0_ltile_clb_mode__0.clb_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_1_1_0_ltile_clb_mode__0.clb_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_1_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_1_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_2_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_1_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_2_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_2_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_1_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_2_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_2_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_1_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_2_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_2_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_1_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_2_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_3_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_2_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_3_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_3_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_2_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_3_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_3_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_2_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_3_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_3_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_2_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_3_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_3_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_2_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_3_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_3_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_2_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_3_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_3_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_2_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_3_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_3_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_2_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_3_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_12_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_12_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_8_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_8_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__clkbuf_1 \clkbuf_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ( |
| .A(\clknet_3_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_0_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCD(SC_IN_TOP), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_0_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .Q(\ltile_clb_mode__0.direct_interc_29_.in ), |
| .SCD(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.direct_interc_8_.in ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(top_width_0_height_0__pin_0_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(top_width_0_height_0__pin_1_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(top_width_0_height_0__pin_2_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__or2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .B(top_width_0_height_0__pin_3_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(ccff_head), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_10_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_11_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_12_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_13_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_14_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_15_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_16_ ( |
| .CLK(\clknet_4_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_2_ ( |
| .CLK(\clknet_4_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_3_ ( |
| .CLK(\clknet_4_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_4_ ( |
| .CLK(\clknet_4_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_5_ ( |
| .CLK(\clknet_4_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_6_ ( |
| .CLK(\clknet_4_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_7_ ( |
| .CLK(\clknet_4_0_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_8_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_9_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_ ( |
| .A0(_19_), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_fabric_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_fabric_out_0.mux_l2_in_0_ ( |
| .A0(_20_), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_35_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_fabric_out_1.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .A1(\ltile_clb_mode__0.direct_interc_29_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_fabric_out_1.mux_l2_in_0_ ( |
| .A0(_21_), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_34_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l1_in_0_ ( |
| .A0(top_width_0_height_0__pin_32_), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l2_in_0_ ( |
| .A0(_22_), |
| .A1(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_0_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCD(\ltile_clb_mode__0.direct_interc_29_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_0_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .Q(\ltile_clb_mode__0.direct_interc_36_.in ), |
| .SCD(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.direct_interc_8_.in ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(top_width_0_height_0__pin_4_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(top_width_0_height_0__pin_5_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(top_width_0_height_0__pin_6_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__or2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .B(top_width_0_height_0__pin_7_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_10_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_11_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_12_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_13_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_14_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_15_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_16_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_2_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_3_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_4_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_5_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_6_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_7_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_8_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_9_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_4_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_ ( |
| .A0(_23_), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_5_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_fabric_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_fabric_out_0.mux_l2_in_0_ ( |
| .A0(_24_), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_37_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_fabric_out_1.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .A1(\ltile_clb_mode__0.direct_interc_36_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_fabric_out_1.mux_l2_in_0_ ( |
| .A0(_25_), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_36_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.direct_interc_29_.in ), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l2_in_0_ ( |
| .A0(_26_), |
| .A1(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_1.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_0_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCD(\ltile_clb_mode__0.direct_interc_36_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_0_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .Q(\ltile_clb_mode__0.direct_interc_43_.in ), |
| .SCD(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.direct_interc_8_.in ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(top_width_0_height_0__pin_8_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(top_width_0_height_0__pin_9_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(top_width_0_height_0__pin_10_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__or2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .B(top_width_0_height_0__pin_11_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_1.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_10_ ( |
| .CLK(\clknet_4_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_11_ ( |
| .CLK(\clknet_4_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_12_ ( |
| .CLK(\clknet_4_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_13_ ( |
| .CLK(\clknet_4_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_14_ ( |
| .CLK(\clknet_4_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_15_ ( |
| .CLK(\clknet_4_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_16_ ( |
| .CLK(\clknet_4_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_2_ ( |
| .CLK(\clknet_4_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_3_ ( |
| .CLK(\clknet_4_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_4_ ( |
| .CLK(\clknet_4_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_5_ ( |
| .CLK(\clknet_4_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_6_ ( |
| .CLK(\clknet_4_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_7_ ( |
| .CLK(\clknet_4_1_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_8_ ( |
| .CLK(\clknet_4_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_9_ ( |
| .CLK(\clknet_4_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_ ( |
| .A0(_27_), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_3_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_12_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_6_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_2.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_fabric_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_fabric_out_0.mux_l2_in_0_ ( |
| .A0(_28_), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_39_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_fabric_out_1.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .A1(\ltile_clb_mode__0.direct_interc_43_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_fabric_out_1.mux_l2_in_0_ ( |
| .A0(_29_), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_38_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.direct_interc_36_.in ), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l2_in_0_ ( |
| .A0(_30_), |
| .A1(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_2.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_2.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_0_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCD(\ltile_clb_mode__0.direct_interc_43_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_1_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .Q(\ltile_clb_mode__0.direct_interc_50_.in ), |
| .SCD(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.direct_interc_8_.in ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(top_width_0_height_0__pin_12_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(top_width_0_height_0__pin_13_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(top_width_0_height_0__pin_14_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__or2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .B(top_width_0_height_0__pin_15_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_2.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_10_ ( |
| .CLK(\clknet_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_11_ ( |
| .CLK(\clknet_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_12_ ( |
| .CLK(\clknet_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_13_ ( |
| .CLK(\clknet_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_14_ ( |
| .CLK(\clknet_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_15_ ( |
| .CLK(\clknet_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_16_ ( |
| .CLK(\clknet_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_2_ ( |
| .CLK(\clknet_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_3_ ( |
| .CLK(\clknet_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_4_ ( |
| .CLK(\clknet_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_5_ ( |
| .CLK(\clknet_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_6_ ( |
| .CLK(\clknet_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_7_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_8_ ( |
| .CLK(\clknet_4_7_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_9_ ( |
| .CLK(\clknet_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_ ( |
| .A0(_31_), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_13_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_12_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_3.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_fabric_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_fabric_out_0.mux_l2_in_0_ ( |
| .A0(_00_), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_41_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_fabric_out_1.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .A1(\ltile_clb_mode__0.direct_interc_50_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_fabric_out_1.mux_l2_in_0_ ( |
| .A0(_01_), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(top_width_0_height_0__pin_40_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.direct_interc_43_.in ), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l2_in_0_ ( |
| .A0(_02_), |
| .A1(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_3.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_3.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_1_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCD(\ltile_clb_mode__0.direct_interc_50_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_1_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .Q(\ltile_clb_mode__0.direct_interc_57_.in ), |
| .SCD(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.direct_interc_8_.in ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(right_width_0_height_0__pin_16_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(right_width_0_height_0__pin_17_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(right_width_0_height_0__pin_18_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__or2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .B(right_width_0_height_0__pin_19_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_3.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_10_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_11_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_12_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_13_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_14_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_15_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_16_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_2_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_3_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_4_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_5_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_6_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_7_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_8_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_9_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_ ( |
| .A0(_03_), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_4.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_fabric_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_fabric_out_0.mux_l2_in_0_ ( |
| .A0(_04_), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_43_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_fabric_out_1.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .A1(\ltile_clb_mode__0.direct_interc_57_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_fabric_out_1.mux_l2_in_0_ ( |
| .A0(_05_), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_42_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.direct_interc_50_.in ), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l2_in_0_ ( |
| .A0(_06_), |
| .A1(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_4.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_4.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_1_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCD(\ltile_clb_mode__0.direct_interc_57_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_1_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .Q(\ltile_clb_mode__0.direct_interc_64_.in ), |
| .SCD(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.direct_interc_8_.in ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(right_width_0_height_0__pin_20_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(right_width_0_height_0__pin_21_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(right_width_0_height_0__pin_22_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__or2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .B(right_width_0_height_0__pin_23_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_8_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_4.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_10_ ( |
| .CLK(\clknet_4_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_11_ ( |
| .CLK(\clknet_4_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_12_ ( |
| .CLK(\clknet_4_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_13_ ( |
| .CLK(\clknet_4_8_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_14_ ( |
| .CLK(\clknet_4_8_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_15_ ( |
| .CLK(\clknet_4_8_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_16_ ( |
| .CLK(\clknet_4_8_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_2_ ( |
| .CLK(\clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_3_ ( |
| .CLK(\clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_4_ ( |
| .CLK(\clknet_4_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_5_ ( |
| .CLK(\clknet_4_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_6_ ( |
| .CLK(\clknet_4_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_7_ ( |
| .CLK(\clknet_4_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_8_ ( |
| .CLK(\clknet_4_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_9_ ( |
| .CLK(\clknet_4_2_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_8_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_8_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_ ( |
| .A0(_07_), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_8_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_8_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_10_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_8_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_5.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_fabric_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_fabric_out_0.mux_l2_in_0_ ( |
| .A0(_08_), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_45_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_fabric_out_1.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .A1(\ltile_clb_mode__0.direct_interc_64_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_fabric_out_1.mux_l2_in_0_ ( |
| .A0(_09_), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_44_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.direct_interc_57_.in ), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l2_in_0_ ( |
| .A0(_10_), |
| .A1(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_5.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_5.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_1_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCD(\ltile_clb_mode__0.direct_interc_64_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_1_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .Q(\ltile_clb_mode__0.direct_interc_71_.in ), |
| .SCD(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.direct_interc_8_.in ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(right_width_0_height_0__pin_24_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(right_width_0_height_0__pin_25_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(right_width_0_height_0__pin_26_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__or2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .B(right_width_0_height_0__pin_27_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_5.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_10_ ( |
| .CLK(\clknet_4_12_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_11_ ( |
| .CLK(\clknet_4_12_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_12_ ( |
| .CLK(\clknet_4_12_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_13_ ( |
| .CLK(\clknet_4_12_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_14_ ( |
| .CLK(\clknet_4_12_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_15_ ( |
| .CLK(\clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_16_ ( |
| .CLK(\clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_2_ ( |
| .CLK(\clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_3_ ( |
| .CLK(\clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_4_ ( |
| .CLK(\clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_5_ ( |
| .CLK(\clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_6_ ( |
| .CLK(\clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_7_ ( |
| .CLK(\clknet_4_9_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_8_ ( |
| .CLK(\clknet_4_12_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_9_ ( |
| .CLK(\clknet_4_12_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_ ( |
| .A0(_11_), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_6.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_fabric_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_fabric_out_0.mux_l2_in_0_ ( |
| .A0(_12_), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_47_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_fabric_out_1.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .A1(\ltile_clb_mode__0.direct_interc_71_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_fabric_out_1.mux_l2_in_0_ ( |
| .A0(_13_), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_46_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.direct_interc_64_.in ), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l2_in_0_ ( |
| .A0(_14_), |
| .A1(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_6.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_6.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_clb_fle_ff_0.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_1_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCD(\ltile_clb_mode__0.direct_interc_71_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__sdfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_clb_fle_ff_1.sky130_fd_sc_hd__sdfxtp_1_0_ ( |
| .CLK(\clknet_1_1_0_ltile_clb_mode__0.clb_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .Q(SC_OUT_BOT), |
| .SCD(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .SCE(\ltile_clb_mode__0.Test_en ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_4_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_5_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_6_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l1_in_7_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_1_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_3_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_2_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_2_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_5_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_4_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l2_in_3_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_7_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_6_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l3_in_1_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.mux_l4_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_12_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_13_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.direct_interc_8_.in ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_14_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_8_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_9_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_4_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_10_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_5_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__mux2_1_11_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.sky130_fd_sc_hd__buf_2_6_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_ ( |
| .A(right_width_0_height_0__pin_28_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_0_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_ ( |
| .A(right_width_0_height_0__pin_29_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_1_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_ ( |
| .A(right_width_0_height_0__pin_30_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_2_X ) |
| ); |
| sky130_fd_sc_hd__buf_2 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__buf_2_3_X ) |
| ); |
| sky130_fd_sc_hd__or2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_ ( |
| .A(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .B(right_width_0_height_0__pin_31_), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.sky130_fd_sc_hd__or2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_6.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_10_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_11_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[10] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_12_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[11] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_13_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[12] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_14_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[13] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_15_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[14] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_16_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[15] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_2_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[1] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_3_ ( |
| .CLK(\clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[2] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_4_ ( |
| .CLK(\clknet_4_12_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[3] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_5_ ( |
| .CLK(\clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[4] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_6_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[5] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_7_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[6] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_8_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[7] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_9_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[8] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.in[9] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_15_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut3_out[0] ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_0_.frac_lut4_mux_0_.lut4_out ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mem_frac_logic_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.mux_l2_in_0_ ( |
| .A0(_15_), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_1.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_0_ ( |
| .CLK(\clknet_4_14_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .Q(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__dfxtp_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_ff_0_D_0.sky130_fd_sc_hd__dfxtp_1_1_ ( |
| .CLK(\clknet_4_11_0_ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ), |
| .D(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .Q(ccff_tail), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_fabric_out_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.direct_interc_9_.in ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_fabric_out_0.mux_l2_in_0_ ( |
| .A0(_16_), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_fabric_out_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_0.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_49_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_fabric_out_1.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.direct_interc_8_.in ), |
| .A1(SC_OUT_BOT), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_1.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_fabric_out_1.mux_l2_in_0_ ( |
| .A0(_17_), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_fabric_out_1.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_fabric_out_1.ccff_tail ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(right_width_0_height_0__pin_48_lower) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l1_in_0_ ( |
| .A0(\ltile_clb_mode__0.direct_interc_71_.in ), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_frac_logic_0.mux_frac_logic_out_0.out ), |
| .S(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mem_ff_0_D_0.mem_out[0] ), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ) |
| ); |
| sky130_fd_sc_hd__mux2_1 \ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_ff_0_D_0.mux_l2_in_0_ ( |
| .A0(_18_), |
| .A1(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.mux_ff_0_D_0.sky130_fd_sc_hd__mux2_1_0_X ), |
| .S(ccff_tail), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_7.ltile_phy_fabric_0.ltile_clb_fle_ff_0.ff_D ) |
| ); |
| sky130_fd_sc_hd__buf_4 prog_clk_0_E_FTB01 ( |
| .A(prog_clk_0_N_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(prog_clk_0_E_out) |
| ); |
| sky130_fd_sc_hd__buf_8 prog_clk_0_FTB00 ( |
| .A(prog_clk_0_N_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(\ltile_clb_mode__0.ltile_fle_0.ltile_phy_fabric_0.ltile_frac_logic_0.ltile_frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ) |
| ); |
| sky130_fd_sc_hd__buf_4 prog_clk_0_N_FTB01 ( |
| .A(prog_clk_0_N_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(prog_clk_0_N_out) |
| ); |
| sky130_fd_sc_hd__buf_4 prog_clk_0_S_FTB01 ( |
| .A(prog_clk_0_N_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(prog_clk_0_S_out) |
| ); |
| sky130_fd_sc_hd__buf_4 prog_clk_0_W_FTB01 ( |
| .A(prog_clk_0_N_in), |
| .VGND(VGND), |
| .VNB(VGND), |
| .VPB(VPWR), |
| .VPWR(VPWR), |
| .X(prog_clk_0_W_out) |
| ); |
| endmodule |
