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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-030 / 53ba2391592bc54fdee71e7e20d624213756d176 / . / verilog / gl / user_project / gl / cbx_1__0_.v
blob: b0caa4a9761e1619bc0bb6bab98b5e38cfe01c6c [file] [log] [blame]
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
module cbx_1__0_(IO_ISOL_N, SC_IN_BOT, SC_IN_TOP, SC_OUT_BOT, SC_OUT_TOP, bottom_grid_pin_0_, bottom_grid_pin_10_, bottom_grid_pin_12_, bottom_grid_pin_14_, bottom_grid_pin_16_, bottom_grid_pin_2_, bottom_grid_pin_4_, bottom_grid_pin_6_, bottom_grid_pin_8_, ccff_head, ccff_tail, prog_clk_0_N_in, prog_clk_0_W_out, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_11_lower, top_width_0_height_0__pin_11_upper, top_width_0_height_0__pin_12_, top_width_0_height_0__pin_13_lower, top_width_0_height_0__pin_13_upper, top_width_0_height_0__pin_14_, top_width_0_height_0__pin_15_lower, top_width_0_height_0__pin_15_upper, top_width_0_height_0__pin_16_, top_width_0_height_0__pin_17_lower, top_width_0_height_0__pin_17_upper, top_width_0_height_0__pin_1_lower, top_width_0_height_0__pin_1_upper, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_3_lower, top_width_0_height_0__pin_3_upper, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_5_lower, top_width_0_height_0__pin_5_upper, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_7_lower, top_width_0_height_0__pin_7_upper, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_9_lower, top_width_0_height_0__pin_9_upper, VPWR, VGND, chanx_left_in, chanx_left_out, chanx_right_in, chanx_right_out, gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, gfpga_pad_EMBEDDED_IO_HD_SOC_IN, gfpga_pad_EMBEDDED_IO_HD_SOC_OUT);
input IO_ISOL_N;
input SC_IN_BOT;
input SC_IN_TOP;
output SC_OUT_BOT;
output SC_OUT_TOP;
input VGND;
input VPWR;
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
output bottom_grid_pin_0_;
output bottom_grid_pin_10_;
output bottom_grid_pin_12_;
output bottom_grid_pin_14_;
output bottom_grid_pin_16_;
output bottom_grid_pin_2_;
output bottom_grid_pin_4_;
output bottom_grid_pin_6_;
output bottom_grid_pin_8_;
input ccff_head;
output ccff_tail;
input [19:0] chanx_left_in;
output [19:0] chanx_left_out;
input [19:0] chanx_right_in;
output [19:0] chanx_right_out;
wire \clknet_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ;
wire \clknet_1_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ;
wire \clknet_1_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ;
wire \clknet_2_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ;
wire \clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ;
wire \clknet_2_2_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ;
wire \clknet_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ;
output [8:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
input [8:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
output [8:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire \logical_tile_io_mode_io__0.ccff_head ;
wire \logical_tile_io_mode_io__0.ccff_tail ;
wire \logical_tile_io_mode_io__0.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
wire \logical_tile_io_mode_io__0.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
wire \logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ;
wire \logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ;
wire \logical_tile_io_mode_io__1.ccff_tail ;
wire \logical_tile_io_mode_io__1.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
wire \logical_tile_io_mode_io__1.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
wire \logical_tile_io_mode_io__1.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ;
wire \logical_tile_io_mode_io__2.ccff_tail ;
wire \logical_tile_io_mode_io__2.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
wire \logical_tile_io_mode_io__2.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
wire \logical_tile_io_mode_io__2.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ;
wire \logical_tile_io_mode_io__3.ccff_tail ;
wire \logical_tile_io_mode_io__3.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
wire \logical_tile_io_mode_io__3.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
wire \logical_tile_io_mode_io__3.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ;
wire \logical_tile_io_mode_io__4.ccff_tail ;
wire \logical_tile_io_mode_io__4.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
wire \logical_tile_io_mode_io__4.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
wire \logical_tile_io_mode_io__4.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ;
wire \logical_tile_io_mode_io__5.ccff_tail ;
wire \logical_tile_io_mode_io__5.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
wire \logical_tile_io_mode_io__5.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
wire \logical_tile_io_mode_io__5.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ;
wire \logical_tile_io_mode_io__6.ccff_tail ;
wire \logical_tile_io_mode_io__6.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
wire \logical_tile_io_mode_io__6.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
wire \logical_tile_io_mode_io__6.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ;
wire \logical_tile_io_mode_io__7.ccff_tail ;
wire \logical_tile_io_mode_io__7.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
wire \logical_tile_io_mode_io__7.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
wire \logical_tile_io_mode_io__7.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ;
wire \logical_tile_io_mode_io__8.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
wire \logical_tile_io_mode_io__8.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
wire \logical_tile_io_mode_io__8.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ;
wire \mem_top_ipin_0.ccff_tail ;
wire \mem_top_ipin_0.mem_out[0] ;
wire \mem_top_ipin_0.mem_out[1] ;
wire \mem_top_ipin_0.mem_out[2] ;
wire \mem_top_ipin_1.ccff_tail ;
wire \mem_top_ipin_1.mem_out[0] ;
wire \mem_top_ipin_1.mem_out[1] ;
wire \mem_top_ipin_1.mem_out[2] ;
wire \mem_top_ipin_2.ccff_tail ;
wire \mem_top_ipin_2.mem_out[0] ;
wire \mem_top_ipin_2.mem_out[1] ;
wire \mem_top_ipin_2.mem_out[2] ;
wire \mem_top_ipin_3.ccff_tail ;
wire \mem_top_ipin_3.mem_out[0] ;
wire \mem_top_ipin_3.mem_out[1] ;
wire \mem_top_ipin_3.mem_out[2] ;
wire \mem_top_ipin_4.ccff_tail ;
wire \mem_top_ipin_4.mem_out[0] ;
wire \mem_top_ipin_4.mem_out[1] ;
wire \mem_top_ipin_4.mem_out[2] ;
wire \mem_top_ipin_5.ccff_tail ;
wire \mem_top_ipin_5.mem_out[0] ;
wire \mem_top_ipin_5.mem_out[1] ;
wire \mem_top_ipin_5.mem_out[2] ;
wire \mem_top_ipin_6.ccff_tail ;
wire \mem_top_ipin_6.mem_out[0] ;
wire \mem_top_ipin_6.mem_out[1] ;
wire \mem_top_ipin_6.mem_out[2] ;
wire \mem_top_ipin_7.ccff_tail ;
wire \mem_top_ipin_7.mem_out[0] ;
wire \mem_top_ipin_7.mem_out[1] ;
wire \mem_top_ipin_7.mem_out[2] ;
wire \mem_top_ipin_8.mem_out[0] ;
wire \mem_top_ipin_8.mem_out[1] ;
wire \mem_top_ipin_8.mem_out[2] ;
wire \mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_0_X ;
wire \mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_1_X ;
wire \mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_2_X ;
wire \mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_3_X ;
wire \mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_4_X ;
wire \mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_5_X ;
wire \mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_6_X ;
wire \mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_7_X ;
wire \mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_8_X ;
wire \mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_9_X ;
wire \mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_0_X ;
wire \mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_1_X ;
wire \mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_2_X ;
wire \mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_3_X ;
wire \mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_4_X ;
wire \mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_5_X ;
wire \mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_6_X ;
wire \mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_7_X ;
wire \mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_8_X ;
wire \mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_9_X ;
wire \mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_0_X ;
wire \mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_1_X ;
wire \mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_2_X ;
wire \mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_3_X ;
wire \mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_4_X ;
wire \mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_5_X ;
wire \mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_6_X ;
wire \mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_7_X ;
wire \mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_8_X ;
wire \mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_9_X ;
wire \mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_0_X ;
wire \mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_1_X ;
wire \mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_2_X ;
wire \mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_3_X ;
wire \mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_4_X ;
wire \mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_5_X ;
wire \mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_6_X ;
wire \mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_7_X ;
wire \mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_8_X ;
wire \mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_9_X ;
wire \mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_0_X ;
wire \mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_1_X ;
wire \mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_2_X ;
wire \mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_3_X ;
wire \mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_4_X ;
wire \mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_5_X ;
wire \mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_6_X ;
wire \mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_7_X ;
wire \mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_8_X ;
wire \mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_9_X ;
wire \mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_0_X ;
wire \mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_1_X ;
wire \mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_2_X ;
wire \mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_3_X ;
wire \mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_4_X ;
wire \mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_5_X ;
wire \mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_6_X ;
wire \mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_7_X ;
wire \mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_8_X ;
wire \mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_9_X ;
wire \mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_0_X ;
wire \mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_1_X ;
wire \mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_2_X ;
wire \mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_3_X ;
wire \mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_4_X ;
wire \mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_5_X ;
wire \mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_6_X ;
wire \mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_7_X ;
wire \mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_8_X ;
wire \mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_9_X ;
wire \mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_0_X ;
wire \mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_1_X ;
wire \mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_2_X ;
wire \mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_3_X ;
wire \mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_4_X ;
wire \mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_5_X ;
wire \mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_6_X ;
wire \mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_7_X ;
wire \mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_8_X ;
wire \mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_9_X ;
wire \mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_0_X ;
wire \mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_1_X ;
wire \mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_2_X ;
wire \mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_3_X ;
wire \mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_4_X ;
wire \mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_5_X ;
wire \mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_6_X ;
wire \mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_7_X ;
wire \mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_8_X ;
wire \mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_9_X ;
input prog_clk_0_N_in;
output prog_clk_0_W_out;
input top_width_0_height_0__pin_0_;
input top_width_0_height_0__pin_10_;
output top_width_0_height_0__pin_11_lower;
output top_width_0_height_0__pin_11_upper;
input top_width_0_height_0__pin_12_;
output top_width_0_height_0__pin_13_lower;
output top_width_0_height_0__pin_13_upper;
input top_width_0_height_0__pin_14_;
output top_width_0_height_0__pin_15_lower;
output top_width_0_height_0__pin_15_upper;
input top_width_0_height_0__pin_16_;
output top_width_0_height_0__pin_17_lower;
output top_width_0_height_0__pin_17_upper;
output top_width_0_height_0__pin_1_lower;
output top_width_0_height_0__pin_1_upper;
input top_width_0_height_0__pin_2_;
output top_width_0_height_0__pin_3_lower;
output top_width_0_height_0__pin_3_upper;
input top_width_0_height_0__pin_4_;
output top_width_0_height_0__pin_5_lower;
output top_width_0_height_0__pin_5_upper;
input top_width_0_height_0__pin_6_;
output top_width_0_height_0__pin_7_lower;
output top_width_0_height_0__pin_7_upper;
input top_width_0_height_0__pin_8_;
output top_width_0_height_0__pin_9_lower;
output top_width_0_height_0__pin_9_upper;
sky130_fd_sc_hd__diode_2 ANTENNA__18__A (
.DIODE(chanx_right_in[5]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__19__A (
.DIODE(chanx_right_in[6]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__20__A (
.DIODE(chanx_right_in[7]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__21__A (
.DIODE(chanx_right_in[8]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__22__A (
.DIODE(chanx_right_in[9]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__23__A (
.DIODE(chanx_right_in[10]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__24__A (
.DIODE(chanx_right_in[11]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__25__A (
.DIODE(chanx_right_in[12]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__26__A (
.DIODE(chanx_right_in[13]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__27__A (
.DIODE(chanx_right_in[14]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__28__A (
.DIODE(chanx_right_in[15]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__29__A (
.DIODE(chanx_right_in[16]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__30__A (
.DIODE(chanx_right_in[17]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__31__A (
.DIODE(chanx_right_in[18]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__32__A (
.DIODE(chanx_right_in[19]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__33__A (
.DIODE(chanx_left_in[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__34__A (
.DIODE(chanx_left_in[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__35__A (
.DIODE(chanx_left_in[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__36__A (
.DIODE(chanx_left_in[3]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__37__A (
.DIODE(chanx_left_in[4]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__38__A (
.DIODE(chanx_left_in[5]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__39__A (
.DIODE(chanx_left_in[6]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__40__A (
.DIODE(chanx_left_in[7]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__41__A (
.DIODE(chanx_left_in[8]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__42__A (
.DIODE(chanx_left_in[9]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__43__A (
.DIODE(chanx_left_in[10]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__44__A (
.DIODE(chanx_left_in[11]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__45__A (
.DIODE(chanx_left_in[12]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__46__A (
.DIODE(chanx_left_in[13]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__47__A (
.DIODE(chanx_left_in[14]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__48__A (
.DIODE(chanx_left_in[15]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__49__A (
.DIODE(chanx_left_in[16]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__50__A (
.DIODE(chanx_left_in[17]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__51__A (
.DIODE(chanx_left_in[18]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__52__A (
.DIODE(chanx_left_in[19]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__75__A (
.DIODE(top_width_0_height_0__pin_1_lower),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__76__A (
.DIODE(top_width_0_height_0__pin_3_lower),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__77__A (
.DIODE(top_width_0_height_0__pin_5_lower),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__78__A (
.DIODE(top_width_0_height_0__pin_7_lower),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__79__A (
.DIODE(top_width_0_height_0__pin_9_lower),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__80__A (
.DIODE(SC_IN_TOP),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__81__A (
.DIODE(SC_IN_BOT),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__82__A (
.DIODE(chanx_right_in[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__83__A (
.DIODE(chanx_right_in[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__84__A (
.DIODE(chanx_right_in[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__85__A (
.DIODE(chanx_right_in[3]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA__86__A (
.DIODE(chanx_right_in[4]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE_A (
.DIODE(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE_B_N (
.DIODE(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE_A (
.DIODE(top_width_0_height_0__pin_0_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__1.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE_A (
.DIODE(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__1.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE_B_N (
.DIODE(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__1.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE_A (
.DIODE(top_width_0_height_0__pin_2_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__2.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE_A (
.DIODE(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__2.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE_B_N (
.DIODE(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__2.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE_A (
.DIODE(top_width_0_height_0__pin_4_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__3.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE_A (
.DIODE(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__3.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE_B_N (
.DIODE(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__3.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE_A (
.DIODE(top_width_0_height_0__pin_6_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__4.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE_A (
.DIODE(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__4.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE_B_N (
.DIODE(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__4.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE_A (
.DIODE(top_width_0_height_0__pin_8_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__5.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE_A (
.DIODE(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__5.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE_B_N (
.DIODE(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__5.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE_A (
.DIODE(top_width_0_height_0__pin_10_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__6.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE_A (
.DIODE(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__6.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE_B_N (
.DIODE(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__6.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE_A (
.DIODE(top_width_0_height_0__pin_12_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__7.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE_A (
.DIODE(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__7.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE_B_N (
.DIODE(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__7.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE_A (
.DIODE(top_width_0_height_0__pin_14_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__8.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE_A (
.DIODE(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__8.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE_B_N (
.DIODE(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_logical_tile_io_mode_io__8.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE_A (
.DIODE(top_width_0_height_0__pin_16_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mem_top_ipin_0.sky130_fd_sc_hd__dfxtp_1_0__D (
.DIODE(ccff_head),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_0.mux_l1_in_0__A0 (
.DIODE(chanx_right_in[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_0.mux_l1_in_0__A1 (
.DIODE(chanx_left_in[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_0.mux_l1_in_1__A0 (
.DIODE(chanx_right_in[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_0.mux_l1_in_1__A1 (
.DIODE(chanx_left_in[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_0.mux_l1_in_2__A0 (
.DIODE(chanx_right_in[4]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_0.mux_l1_in_2__A1 (
.DIODE(chanx_left_in[4]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_0.mux_l2_in_1__A0 (
.DIODE(chanx_left_in[10]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_0.mux_l2_in_2__A0 (
.DIODE(chanx_left_in[16]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_0.mux_l2_in_2__A1 (
.DIODE(chanx_right_in[10]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_0.mux_l2_in_3__A1 (
.DIODE(chanx_right_in[16]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_1.mux_l1_in_0__A0 (
.DIODE(chanx_right_in[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_1.mux_l1_in_0__A1 (
.DIODE(chanx_left_in[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_1.mux_l1_in_1__A0 (
.DIODE(chanx_right_in[3]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_1.mux_l1_in_1__A1 (
.DIODE(chanx_left_in[3]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_1.mux_l1_in_2__A0 (
.DIODE(chanx_right_in[5]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_1.mux_l1_in_2__A1 (
.DIODE(chanx_left_in[5]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_1.mux_l2_in_1__A0 (
.DIODE(chanx_left_in[11]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_1.mux_l2_in_2__A0 (
.DIODE(chanx_left_in[17]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_1.mux_l2_in_2__A1 (
.DIODE(chanx_right_in[11]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_1.mux_l2_in_3__A1 (
.DIODE(chanx_right_in[17]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_2.mux_l1_in_0__A0 (
.DIODE(chanx_right_in[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_2.mux_l1_in_0__A1 (
.DIODE(chanx_left_in[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_2.mux_l1_in_1__A0 (
.DIODE(chanx_right_in[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_2.mux_l1_in_1__A1 (
.DIODE(chanx_left_in[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_2.mux_l1_in_2__A0 (
.DIODE(chanx_right_in[6]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_2.mux_l1_in_2__A1 (
.DIODE(chanx_left_in[6]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_2.mux_l2_in_1__A0 (
.DIODE(chanx_left_in[12]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_2.mux_l2_in_2__A0 (
.DIODE(chanx_left_in[18]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_2.mux_l2_in_2__A1 (
.DIODE(chanx_right_in[12]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_2.mux_l2_in_3__A1 (
.DIODE(chanx_right_in[18]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_3.mux_l1_in_0__A0 (
.DIODE(chanx_right_in[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_3.mux_l1_in_0__A1 (
.DIODE(chanx_left_in[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_3.mux_l1_in_1__A0 (
.DIODE(chanx_right_in[3]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_3.mux_l1_in_1__A1 (
.DIODE(chanx_left_in[3]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_3.mux_l1_in_2__A0 (
.DIODE(chanx_right_in[7]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_3.mux_l1_in_2__A1 (
.DIODE(chanx_left_in[7]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_3.mux_l2_in_1__A0 (
.DIODE(chanx_left_in[13]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_3.mux_l2_in_2__A0 (
.DIODE(chanx_left_in[19]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_3.mux_l2_in_2__A1 (
.DIODE(chanx_right_in[13]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_3.mux_l2_in_3__A1 (
.DIODE(chanx_right_in[19]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_4.mux_l1_in_0__A0 (
.DIODE(chanx_right_in[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_4.mux_l1_in_0__A1 (
.DIODE(chanx_left_in[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_4.mux_l1_in_1__A0 (
.DIODE(chanx_right_in[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_4.mux_l1_in_1__A1 (
.DIODE(chanx_left_in[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_4.mux_l1_in_2__A0 (
.DIODE(chanx_right_in[4]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_4.mux_l1_in_2__A1 (
.DIODE(chanx_left_in[4]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_4.mux_l2_in_1__A0 (
.DIODE(chanx_left_in[8]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_4.mux_l2_in_2__A0 (
.DIODE(chanx_left_in[14]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_4.mux_l2_in_2__A1 (
.DIODE(chanx_right_in[8]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_4.mux_l2_in_3__A1 (
.DIODE(chanx_right_in[14]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_5.mux_l1_in_0__A0 (
.DIODE(chanx_right_in[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_5.mux_l1_in_0__A1 (
.DIODE(chanx_left_in[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_5.mux_l1_in_1__A0 (
.DIODE(chanx_right_in[3]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_5.mux_l1_in_1__A1 (
.DIODE(chanx_left_in[3]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_5.mux_l1_in_2__A0 (
.DIODE(chanx_right_in[5]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_5.mux_l1_in_2__A1 (
.DIODE(chanx_left_in[5]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_5.mux_l2_in_1__A0 (
.DIODE(chanx_left_in[9]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_5.mux_l2_in_2__A0 (
.DIODE(chanx_left_in[15]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_5.mux_l2_in_2__A1 (
.DIODE(chanx_right_in[9]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_5.mux_l2_in_3__A1 (
.DIODE(chanx_right_in[15]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_6.mux_l1_in_0__A0 (
.DIODE(chanx_right_in[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_6.mux_l1_in_0__A1 (
.DIODE(chanx_left_in[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_6.mux_l1_in_1__A0 (
.DIODE(chanx_right_in[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_6.mux_l1_in_1__A1 (
.DIODE(chanx_left_in[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_6.mux_l1_in_2__A0 (
.DIODE(chanx_right_in[6]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_6.mux_l1_in_2__A1 (
.DIODE(chanx_left_in[6]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_6.mux_l2_in_1__A0 (
.DIODE(chanx_left_in[10]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_6.mux_l2_in_2__A0 (
.DIODE(chanx_left_in[16]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_6.mux_l2_in_2__A1 (
.DIODE(chanx_right_in[10]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_6.mux_l2_in_3__A1 (
.DIODE(chanx_right_in[16]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_7.mux_l1_in_0__A0 (
.DIODE(chanx_right_in[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_7.mux_l1_in_0__A1 (
.DIODE(chanx_left_in[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_7.mux_l1_in_1__A0 (
.DIODE(chanx_right_in[3]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_7.mux_l1_in_1__A1 (
.DIODE(chanx_left_in[3]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_7.mux_l1_in_2__A0 (
.DIODE(chanx_right_in[7]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_7.mux_l1_in_2__A1 (
.DIODE(chanx_left_in[7]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_7.mux_l2_in_1__A0 (
.DIODE(chanx_left_in[11]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_7.mux_l2_in_2__A0 (
.DIODE(chanx_left_in[17]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_7.mux_l2_in_2__A1 (
.DIODE(chanx_right_in[11]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_7.mux_l2_in_3__A1 (
.DIODE(chanx_right_in[17]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_8.mux_l1_in_0__A0 (
.DIODE(chanx_right_in[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_8.mux_l1_in_0__A1 (
.DIODE(chanx_left_in[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_8.mux_l1_in_1__A0 (
.DIODE(chanx_right_in[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_8.mux_l1_in_1__A1 (
.DIODE(chanx_left_in[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_8.mux_l1_in_2__A0 (
.DIODE(chanx_right_in[8]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_8.mux_l1_in_2__A1 (
.DIODE(chanx_left_in[8]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_8.mux_l2_in_1__A0 (
.DIODE(chanx_left_in[12]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_8.mux_l2_in_2__A0 (
.DIODE(chanx_left_in[18]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_8.mux_l2_in_2__A1 (
.DIODE(chanx_right_in[12]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 \ANTENNA_mux_top_ipin_8.mux_l2_in_3__A1 (
.DIODE(chanx_right_in[18]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA_prog_clk_0_FTB00_A (
.DIODE(prog_clk_0_N_in),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__diode_2 ANTENNA_prog_clk_0_W_FTB01_A (
.DIODE(prog_clk_0_N_in),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_0_154 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_0_17 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_0_185 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_0_189 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_0_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_0_30 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_0_38 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_0_52 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_0_87 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_0_92 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_10_140 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_10_152 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_10_181 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_10_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_10_30 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_10_66 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_10_87 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_10_91 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_10_93 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_11_110 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_11_123 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_11_140 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_11_162 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_11_22 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_11_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_11_42 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_11_60 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_11_64 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_12_106 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_12_123 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_12_140 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_12_152 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_12_154 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_12_160 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_12_167 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_12_24 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_12_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_12_30 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_12_32 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_12_43 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_12_64 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_12_7 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_12_82 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_13_102 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_13_106 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_13_110 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_13_120 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_13_123 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_13_148 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_13_16 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_13_176 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_13_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_13_60 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_13_73 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_13_83 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_14_118 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_14_129 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_14_13 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_14_135 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_14_23 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_14_32 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_14_5 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_14_86 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_14_93 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_15_100 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_15_112 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_15_136 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_15_153 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_15_174 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_15_29 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_15_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_15_37 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_15_58 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_15_62 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_16_116 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_16_140 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_16_152 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_16_154 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_16_166 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_16_178 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_16_28 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_16_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_16_32 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_16_44 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_16_47 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_16_61 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_16_78 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_16_90 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_16_93 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_16_99 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_17_110 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_17_123 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_17_135 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_17_147 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_17_159 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_17_171 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_17_184 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_17_24 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_17_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_17_58 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_17_62 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_17_70 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_17_86 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_17_98 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_18_105 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_18_117 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_18_129 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_18_141 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_18_154 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_18_166 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_18_178 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_18_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_18_32 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_18_44 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_18_50 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_18_67 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_18_79 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_18_91 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_18_93 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_19_110 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_19_123 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_19_135 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_19_147 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_19_159 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_19_171 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_19_184 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_19_27 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_19_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_19_39 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_19_51 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_19_59 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_19_62 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_19_74 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_19_86 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_19_98 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_1_121 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_1_138 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_1_156 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_1_174 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_1_22 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_1_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_1_34 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_1_46 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_1_58 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_1_62 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_1_78 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_1_81 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_20_105 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_20_117 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_20_12 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_20_129 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_20_141 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_20_154 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_20_16 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_20_166 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_20_178 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_20_28 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_20_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_20_32 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_20_44 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_20_56 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_20_68 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_20_80 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_20_9 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_20_93 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_21_102 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_21_114 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_21_123 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_21_135 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_21_140 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_21_144 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_21_149 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_21_161 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_21_173 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_21_181 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_21_184 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_21_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_21_32 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_21_44 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_21_52 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_21_66 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_21_78 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_21_90 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_22_106 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_22_118 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_22_125 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_22_137 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_22_149 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_22_15 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_22_156 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_22_168 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_22_180 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_22_187 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_22_27 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_22_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_22_32 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_22_44 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_22_56 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_22_63 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_22_75 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_22_87 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_22_94 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_2_129 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_2_135 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_2_14 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_2_142 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_2_148 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_2_164 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_2_167 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_2_26 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_2_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_2_30 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_2_32 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_2_91 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_3_123 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_3_140 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_3_182 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_3_23 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_3_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_3_60 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_3_64 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_3_99 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_4_115 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_4_136 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_4_14 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_4_145 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_4_167 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_4_181 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_4_26 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_4_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_4_30 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_4_32 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_4_61 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_4_73 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_4_91 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_4_95 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_5_104 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_5_108 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_5_125 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_5_146 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_5_158 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_5_162 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_5_178 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_5_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_5_41 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_5_78 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_5_86 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_6_109 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_6_120 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_6_126 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_6_143 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_6_151 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_6_154 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_6_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_6_32 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_6_54 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_6_62 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_12 FILLER_6_75 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_6_87 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_6_91 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_7_10 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_7_101 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_7_105 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_7_134 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_7_138 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_7_155 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_7_159 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_7_182 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_7_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_7_43 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_7_47 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_7_65 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 FILLER_7_73 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_7_87 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_7_97 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_8_101 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_4 FILLER_8_140 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_8_27 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_8_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_8_30 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_8_65 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_8_73 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_2 FILLER_8_90 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_8 FILLER_8_93 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_9_112 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_9_137 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_6 FILLER_9_154 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_9_160 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__fill_1 FILLER_9_29 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_0 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_1 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_10 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_100 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_101 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_102 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_103 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_104 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_105 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_106 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_107 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_108 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_109 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_11 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_110 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_111 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_112 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_113 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_114 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_115 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_116 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_117 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_118 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_119 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_12 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_120 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_13 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_14 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_15 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_16 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_17 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_18 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_19 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_2 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_20 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_21 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_22 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_23 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_24 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_25 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_26 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_27 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_28 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_29 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_3 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_30 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_31 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_32 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_33 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_34 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_35 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_36 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_37 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_38 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_39 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_4 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_40 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_41 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_42 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_43 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_44 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_45 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_46 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_47 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_48 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_49 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_5 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_50 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_51 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_52 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_53 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_54 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_55 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_56 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_57 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_58 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_59 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_6 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_60 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_61 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_62 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_63 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_64 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_65 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_66 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_67 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_68 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_69 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_7 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_70 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_71 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_72 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_73 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_74 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_75 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_76 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_77 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_78 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_79 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_8 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_80 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_81 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_82 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_83 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_84 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_85 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_86 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_87 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_88 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_89 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__decap_3 PHY_9 (
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_90 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_91 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_92 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_93 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_94 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_95 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_96 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_97 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_98 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_99 (
.VGND(VGND),
.VPWR(VPWR)
);
sky130_fd_sc_hd__conb_1 _09_ (
.HI(_00_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__conb_1 _10_ (
.HI(_01_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__conb_1 _11_ (
.HI(_02_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__conb_1 _12_ (
.HI(_03_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__conb_1 _13_ (
.HI(_04_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__conb_1 _14_ (
.HI(_05_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__conb_1 _15_ (
.HI(_06_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__conb_1 _16_ (
.HI(_07_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__conb_1 _17_ (
.HI(_08_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__buf_2 _18_ (
.A(chanx_right_in[5]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[5])
);
sky130_fd_sc_hd__buf_2 _19_ (
.A(chanx_right_in[6]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[6])
);
sky130_fd_sc_hd__buf_2 _20_ (
.A(chanx_right_in[7]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[7])
);
sky130_fd_sc_hd__buf_2 _21_ (
.A(chanx_right_in[8]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[8])
);
sky130_fd_sc_hd__buf_2 _22_ (
.A(chanx_right_in[9]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[9])
);
sky130_fd_sc_hd__buf_2 _23_ (
.A(chanx_right_in[10]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[10])
);
sky130_fd_sc_hd__buf_2 _24_ (
.A(chanx_right_in[11]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[11])
);
sky130_fd_sc_hd__buf_2 _25_ (
.A(chanx_right_in[12]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[12])
);
sky130_fd_sc_hd__buf_2 _26_ (
.A(chanx_right_in[13]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[13])
);
sky130_fd_sc_hd__buf_2 _27_ (
.A(chanx_right_in[14]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[14])
);
sky130_fd_sc_hd__buf_2 _28_ (
.A(chanx_right_in[15]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[15])
);
sky130_fd_sc_hd__buf_2 _29_ (
.A(chanx_right_in[16]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[16])
);
sky130_fd_sc_hd__buf_2 _30_ (
.A(chanx_right_in[17]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[17])
);
sky130_fd_sc_hd__buf_2 _31_ (
.A(chanx_right_in[18]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[18])
);
sky130_fd_sc_hd__buf_2 _32_ (
.A(chanx_right_in[19]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[19])
);
sky130_fd_sc_hd__buf_2 _33_ (
.A(chanx_left_in[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[0])
);
sky130_fd_sc_hd__buf_2 _34_ (
.A(chanx_left_in[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[1])
);
sky130_fd_sc_hd__buf_2 _35_ (
.A(chanx_left_in[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[2])
);
sky130_fd_sc_hd__buf_2 _36_ (
.A(chanx_left_in[3]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[3])
);
sky130_fd_sc_hd__buf_2 _37_ (
.A(chanx_left_in[4]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[4])
);
sky130_fd_sc_hd__buf_2 _38_ (
.A(chanx_left_in[5]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[5])
);
sky130_fd_sc_hd__buf_2 _39_ (
.A(chanx_left_in[6]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[6])
);
sky130_fd_sc_hd__buf_2 _40_ (
.A(chanx_left_in[7]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[7])
);
sky130_fd_sc_hd__buf_2 _41_ (
.A(chanx_left_in[8]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[8])
);
sky130_fd_sc_hd__buf_2 _42_ (
.A(chanx_left_in[9]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[9])
);
sky130_fd_sc_hd__buf_2 _43_ (
.A(chanx_left_in[10]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[10])
);
sky130_fd_sc_hd__buf_2 _44_ (
.A(chanx_left_in[11]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[11])
);
sky130_fd_sc_hd__buf_2 _45_ (
.A(chanx_left_in[12]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[12])
);
sky130_fd_sc_hd__buf_2 _46_ (
.A(chanx_left_in[13]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[13])
);
sky130_fd_sc_hd__buf_2 _47_ (
.A(chanx_left_in[14]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[14])
);
sky130_fd_sc_hd__buf_2 _48_ (
.A(chanx_left_in[15]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[15])
);
sky130_fd_sc_hd__buf_2 _49_ (
.A(chanx_left_in[16]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[16])
);
sky130_fd_sc_hd__buf_2 _50_ (
.A(chanx_left_in[17]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[17])
);
sky130_fd_sc_hd__buf_2 _51_ (
.A(chanx_left_in[18]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[18])
);
sky130_fd_sc_hd__buf_2 _52_ (
.A(chanx_left_in[19]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_right_out[19])
);
sky130_fd_sc_hd__buf_2 _53_ (
.A(\logical_tile_io_mode_io__0.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0])
);
sky130_fd_sc_hd__buf_2 _54_ (
.A(\logical_tile_io_mode_io__1.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1])
);
sky130_fd_sc_hd__buf_2 _55_ (
.A(\logical_tile_io_mode_io__2.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2])
);
sky130_fd_sc_hd__buf_2 _56_ (
.A(\logical_tile_io_mode_io__3.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3])
);
sky130_fd_sc_hd__buf_2 _57_ (
.A(\logical_tile_io_mode_io__4.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4])
);
sky130_fd_sc_hd__buf_2 _58_ (
.A(\logical_tile_io_mode_io__5.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5])
);
sky130_fd_sc_hd__buf_2 _59_ (
.A(\logical_tile_io_mode_io__6.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6])
);
sky130_fd_sc_hd__buf_2 _60_ (
.A(\logical_tile_io_mode_io__7.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7])
);
sky130_fd_sc_hd__buf_2 _61_ (
.A(\logical_tile_io_mode_io__8.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8])
);
sky130_fd_sc_hd__buf_2 _62_ (
.A(\logical_tile_io_mode_io__0.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0])
);
sky130_fd_sc_hd__buf_2 _63_ (
.A(\logical_tile_io_mode_io__1.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1])
);
sky130_fd_sc_hd__buf_2 _64_ (
.A(\logical_tile_io_mode_io__2.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2])
);
sky130_fd_sc_hd__buf_2 _65_ (
.A(\logical_tile_io_mode_io__3.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3])
);
sky130_fd_sc_hd__buf_2 _66_ (
.A(\logical_tile_io_mode_io__4.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4])
);
sky130_fd_sc_hd__buf_2 _67_ (
.A(\logical_tile_io_mode_io__5.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5])
);
sky130_fd_sc_hd__buf_2 _68_ (
.A(\logical_tile_io_mode_io__6.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6])
);
sky130_fd_sc_hd__buf_2 _69_ (
.A(\logical_tile_io_mode_io__7.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7])
);
sky130_fd_sc_hd__buf_2 _70_ (
.A(\logical_tile_io_mode_io__8.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8])
);
sky130_fd_sc_hd__buf_2 _71_ (
.A(top_width_0_height_0__pin_11_lower),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(top_width_0_height_0__pin_11_upper)
);
sky130_fd_sc_hd__buf_2 _72_ (
.A(top_width_0_height_0__pin_13_lower),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(top_width_0_height_0__pin_13_upper)
);
sky130_fd_sc_hd__buf_2 _73_ (
.A(top_width_0_height_0__pin_15_lower),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(top_width_0_height_0__pin_15_upper)
);
sky130_fd_sc_hd__buf_2 _74_ (
.A(top_width_0_height_0__pin_17_lower),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(top_width_0_height_0__pin_17_upper)
);
sky130_fd_sc_hd__buf_2 _75_ (
.A(top_width_0_height_0__pin_1_lower),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(top_width_0_height_0__pin_1_upper)
);
sky130_fd_sc_hd__buf_2 _76_ (
.A(top_width_0_height_0__pin_3_lower),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(top_width_0_height_0__pin_3_upper)
);
sky130_fd_sc_hd__buf_2 _77_ (
.A(top_width_0_height_0__pin_5_lower),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(top_width_0_height_0__pin_5_upper)
);
sky130_fd_sc_hd__buf_2 _78_ (
.A(top_width_0_height_0__pin_7_lower),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(top_width_0_height_0__pin_7_upper)
);
sky130_fd_sc_hd__buf_2 _79_ (
.A(top_width_0_height_0__pin_9_lower),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(top_width_0_height_0__pin_9_upper)
);
sky130_fd_sc_hd__buf_2 _80_ (
.A(SC_IN_TOP),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(SC_OUT_BOT)
);
sky130_fd_sc_hd__buf_2 _81_ (
.A(SC_IN_BOT),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(SC_OUT_TOP)
);
sky130_fd_sc_hd__buf_2 _82_ (
.A(chanx_right_in[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[0])
);
sky130_fd_sc_hd__buf_2 _83_ (
.A(chanx_right_in[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[1])
);
sky130_fd_sc_hd__buf_2 _84_ (
.A(chanx_right_in[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[2])
);
sky130_fd_sc_hd__buf_2 _85_ (
.A(chanx_right_in[3]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[3])
);
sky130_fd_sc_hd__buf_2 _86_ (
.A(chanx_right_in[4]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(chanx_left_out[4])
);
sky130_fd_sc_hd__clkbuf_16 \clkbuf_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk (
.A(\logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\clknet_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk )
);
sky130_fd_sc_hd__clkbuf_1 \clkbuf_1_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk (
.A(\clknet_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\clknet_1_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk )
);
sky130_fd_sc_hd__clkbuf_1 \clkbuf_1_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk (
.A(\clknet_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\clknet_1_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk )
);
sky130_fd_sc_hd__clkbuf_1 \clkbuf_2_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk (
.A(\clknet_1_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\clknet_2_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk )
);
sky130_fd_sc_hd__clkbuf_1 \clkbuf_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk (
.A(\clknet_1_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk )
);
sky130_fd_sc_hd__clkbuf_1 \clkbuf_2_2_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk (
.A(\clknet_1_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\clknet_2_2_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk )
);
sky130_fd_sc_hd__clkbuf_1 \clkbuf_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk (
.A(\clknet_1_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\clknet_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk )
);
sky130_fd_sc_hd__inv_1 \logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.INV_SOC_DIR (
.A(\logical_tile_io_mode_io__0.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Y(\logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE (
.A(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.TE_B(\logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(top_width_0_height_0__pin_1_lower)
);
sky130_fd_sc_hd__or2b_4 \logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE (
.A(\logical_tile_io_mode_io__0.ccff_tail ),
.B_N(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\logical_tile_io_mode_io__0.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE (
.A(top_width_0_height_0__pin_0_),
.TE_B(\logical_tile_io_mode_io__0.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(\logical_tile_io_mode_io__0.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT )
);
sky130_fd_sc_hd__dfxtp_1 \logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_2_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\logical_tile_io_mode_io__0.ccff_head ),
.Q(\logical_tile_io_mode_io__0.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__inv_1 \logical_tile_io_mode_io__1.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.INV_SOC_DIR (
.A(\logical_tile_io_mode_io__1.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Y(\logical_tile_io_mode_io__1.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__1.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE (
.A(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.TE_B(\logical_tile_io_mode_io__1.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(top_width_0_height_0__pin_3_lower)
);
sky130_fd_sc_hd__or2b_4 \logical_tile_io_mode_io__1.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE (
.A(\logical_tile_io_mode_io__1.ccff_tail ),
.B_N(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\logical_tile_io_mode_io__1.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__1.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE (
.A(top_width_0_height_0__pin_2_),
.TE_B(\logical_tile_io_mode_io__1.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(\logical_tile_io_mode_io__1.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT )
);
sky130_fd_sc_hd__dfxtp_1 \logical_tile_io_mode_io__1.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\logical_tile_io_mode_io__0.ccff_tail ),
.Q(\logical_tile_io_mode_io__1.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__inv_1 \logical_tile_io_mode_io__2.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.INV_SOC_DIR (
.A(\logical_tile_io_mode_io__2.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Y(\logical_tile_io_mode_io__2.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__2.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE (
.A(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.TE_B(\logical_tile_io_mode_io__2.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(top_width_0_height_0__pin_5_lower)
);
sky130_fd_sc_hd__or2b_4 \logical_tile_io_mode_io__2.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE (
.A(\logical_tile_io_mode_io__2.ccff_tail ),
.B_N(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\logical_tile_io_mode_io__2.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__2.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE (
.A(top_width_0_height_0__pin_4_),
.TE_B(\logical_tile_io_mode_io__2.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(\logical_tile_io_mode_io__2.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT )
);
sky130_fd_sc_hd__dfxtp_1 \logical_tile_io_mode_io__2.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\logical_tile_io_mode_io__1.ccff_tail ),
.Q(\logical_tile_io_mode_io__2.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__inv_1 \logical_tile_io_mode_io__3.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.INV_SOC_DIR (
.A(\logical_tile_io_mode_io__3.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Y(\logical_tile_io_mode_io__3.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__3.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE (
.A(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.TE_B(\logical_tile_io_mode_io__3.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(top_width_0_height_0__pin_7_lower)
);
sky130_fd_sc_hd__or2b_4 \logical_tile_io_mode_io__3.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE (
.A(\logical_tile_io_mode_io__3.ccff_tail ),
.B_N(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\logical_tile_io_mode_io__3.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__3.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE (
.A(top_width_0_height_0__pin_6_),
.TE_B(\logical_tile_io_mode_io__3.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(\logical_tile_io_mode_io__3.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT )
);
sky130_fd_sc_hd__dfxtp_1 \logical_tile_io_mode_io__3.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\logical_tile_io_mode_io__2.ccff_tail ),
.Q(\logical_tile_io_mode_io__3.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__inv_1 \logical_tile_io_mode_io__4.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.INV_SOC_DIR (
.A(\logical_tile_io_mode_io__4.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Y(\logical_tile_io_mode_io__4.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__4.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE (
.A(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4]),
.TE_B(\logical_tile_io_mode_io__4.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(top_width_0_height_0__pin_9_lower)
);
sky130_fd_sc_hd__or2b_4 \logical_tile_io_mode_io__4.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE (
.A(\logical_tile_io_mode_io__4.ccff_tail ),
.B_N(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\logical_tile_io_mode_io__4.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__4.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE (
.A(top_width_0_height_0__pin_8_),
.TE_B(\logical_tile_io_mode_io__4.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(\logical_tile_io_mode_io__4.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT )
);
sky130_fd_sc_hd__dfxtp_1 \logical_tile_io_mode_io__4.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\logical_tile_io_mode_io__3.ccff_tail ),
.Q(\logical_tile_io_mode_io__4.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__inv_1 \logical_tile_io_mode_io__5.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.INV_SOC_DIR (
.A(\logical_tile_io_mode_io__5.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Y(\logical_tile_io_mode_io__5.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__5.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE (
.A(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5]),
.TE_B(\logical_tile_io_mode_io__5.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(top_width_0_height_0__pin_11_lower)
);
sky130_fd_sc_hd__or2b_4 \logical_tile_io_mode_io__5.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE (
.A(\logical_tile_io_mode_io__5.ccff_tail ),
.B_N(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\logical_tile_io_mode_io__5.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__5.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE (
.A(top_width_0_height_0__pin_10_),
.TE_B(\logical_tile_io_mode_io__5.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(\logical_tile_io_mode_io__5.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT )
);
sky130_fd_sc_hd__dfxtp_1 \logical_tile_io_mode_io__5.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\logical_tile_io_mode_io__4.ccff_tail ),
.Q(\logical_tile_io_mode_io__5.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__inv_1 \logical_tile_io_mode_io__6.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.INV_SOC_DIR (
.A(\logical_tile_io_mode_io__6.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Y(\logical_tile_io_mode_io__6.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__6.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE (
.A(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6]),
.TE_B(\logical_tile_io_mode_io__6.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(top_width_0_height_0__pin_13_lower)
);
sky130_fd_sc_hd__or2b_4 \logical_tile_io_mode_io__6.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE (
.A(\logical_tile_io_mode_io__6.ccff_tail ),
.B_N(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\logical_tile_io_mode_io__6.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__6.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE (
.A(top_width_0_height_0__pin_12_),
.TE_B(\logical_tile_io_mode_io__6.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(\logical_tile_io_mode_io__6.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT )
);
sky130_fd_sc_hd__dfxtp_1 \logical_tile_io_mode_io__6.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_2_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\logical_tile_io_mode_io__5.ccff_tail ),
.Q(\logical_tile_io_mode_io__6.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__inv_1 \logical_tile_io_mode_io__7.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.INV_SOC_DIR (
.A(\logical_tile_io_mode_io__7.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Y(\logical_tile_io_mode_io__7.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__7.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE (
.A(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7]),
.TE_B(\logical_tile_io_mode_io__7.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(top_width_0_height_0__pin_15_lower)
);
sky130_fd_sc_hd__or2b_4 \logical_tile_io_mode_io__7.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE (
.A(\logical_tile_io_mode_io__7.ccff_tail ),
.B_N(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\logical_tile_io_mode_io__7.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__7.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE (
.A(top_width_0_height_0__pin_14_),
.TE_B(\logical_tile_io_mode_io__7.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(\logical_tile_io_mode_io__7.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT )
);
sky130_fd_sc_hd__dfxtp_1 \logical_tile_io_mode_io__7.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_2_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\logical_tile_io_mode_io__6.ccff_tail ),
.Q(\logical_tile_io_mode_io__7.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__inv_1 \logical_tile_io_mode_io__8.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.INV_SOC_DIR (
.A(\logical_tile_io_mode_io__8.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Y(\logical_tile_io_mode_io__8.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__8.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.IN_PROTECT_GATE (
.A(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8]),
.TE_B(\logical_tile_io_mode_io__8.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.SOC_DIR_N ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(top_width_0_height_0__pin_17_lower)
);
sky130_fd_sc_hd__or2b_4 \logical_tile_io_mode_io__8.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.ISOL_EN_GATE (
.A(ccff_tail),
.B_N(IO_ISOL_N),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\logical_tile_io_mode_io__8.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR )
);
sky130_fd_sc_hd__ebufn_4 \logical_tile_io_mode_io__8.ltile_phy_iopad_0.EMBEDDED_IO_HD_0_.OUT_PROTECT_GATE (
.A(top_width_0_height_0__pin_16_),
.TE_B(\logical_tile_io_mode_io__8.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.Z(\logical_tile_io_mode_io__8.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT )
);
sky130_fd_sc_hd__dfxtp_1 \logical_tile_io_mode_io__8.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_2_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\logical_tile_io_mode_io__7.ccff_tail ),
.Q(ccff_tail),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_0.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(ccff_head),
.Q(\mem_top_ipin_0.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_0.sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(\clknet_2_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_0.mem_out[0] ),
.Q(\mem_top_ipin_0.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_0.sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(\clknet_2_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_0.mem_out[1] ),
.Q(\mem_top_ipin_0.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_0.sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(\clknet_2_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_0.mem_out[2] ),
.Q(\mem_top_ipin_0.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_1.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_0_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_0.ccff_tail ),
.Q(\mem_top_ipin_1.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_1.sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(\clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_1.mem_out[0] ),
.Q(\mem_top_ipin_1.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_1.sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(\clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_1.mem_out[1] ),
.Q(\mem_top_ipin_1.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_1.sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(\clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_1.mem_out[2] ),
.Q(\mem_top_ipin_1.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_2.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_1.ccff_tail ),
.Q(\mem_top_ipin_2.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_2.sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(\clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_2.mem_out[0] ),
.Q(\mem_top_ipin_2.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_2.sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(\clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_2.mem_out[1] ),
.Q(\mem_top_ipin_2.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_2.sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(\clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_2.mem_out[2] ),
.Q(\mem_top_ipin_2.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_3.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_2.ccff_tail ),
.Q(\mem_top_ipin_3.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_3.sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(\clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_3.mem_out[0] ),
.Q(\mem_top_ipin_3.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_3.sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(\clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_3.mem_out[1] ),
.Q(\mem_top_ipin_3.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_3.sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(\clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_3.mem_out[2] ),
.Q(\mem_top_ipin_3.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_4.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_3.ccff_tail ),
.Q(\mem_top_ipin_4.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_4.sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(\clknet_2_1_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_4.mem_out[0] ),
.Q(\mem_top_ipin_4.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_4.sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(\clknet_2_2_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_4.mem_out[1] ),
.Q(\mem_top_ipin_4.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_4.sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(\clknet_2_2_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_4.mem_out[2] ),
.Q(\mem_top_ipin_4.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_5.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_2_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_4.ccff_tail ),
.Q(\mem_top_ipin_5.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_5.sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(\clknet_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_5.mem_out[0] ),
.Q(\mem_top_ipin_5.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_5.sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(\clknet_2_2_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_5.mem_out[1] ),
.Q(\mem_top_ipin_5.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_5.sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(\clknet_2_2_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_5.mem_out[2] ),
.Q(\mem_top_ipin_5.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_6.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_2_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_5.ccff_tail ),
.Q(\mem_top_ipin_6.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_6.sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(\clknet_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_6.mem_out[0] ),
.Q(\mem_top_ipin_6.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_6.sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(\clknet_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_6.mem_out[1] ),
.Q(\mem_top_ipin_6.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_6.sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(\clknet_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_6.mem_out[2] ),
.Q(\mem_top_ipin_6.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_7.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_6.ccff_tail ),
.Q(\mem_top_ipin_7.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_7.sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(\clknet_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_7.mem_out[0] ),
.Q(\mem_top_ipin_7.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_7.sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(\clknet_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_7.mem_out[1] ),
.Q(\mem_top_ipin_7.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_7.sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(\clknet_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_7.mem_out[2] ),
.Q(\mem_top_ipin_7.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_8.sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(\clknet_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_7.ccff_tail ),
.Q(\mem_top_ipin_8.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_8.sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(\clknet_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_8.mem_out[0] ),
.Q(\mem_top_ipin_8.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_8.sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(\clknet_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_8.mem_out[1] ),
.Q(\mem_top_ipin_8.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__dfxtp_1 \mem_top_ipin_8.sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(\clknet_2_3_0_logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk ),
.D(\mem_top_ipin_8.mem_out[2] ),
.Q(\logical_tile_io_mode_io__0.ccff_head ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_0.mux_l1_in_0_ (
.A0(chanx_right_in[0]),
.A1(chanx_left_in[0]),
.S(\mem_top_ipin_0.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_0_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_0.mux_l1_in_1_ (
.A0(chanx_right_in[2]),
.A1(chanx_left_in[2]),
.S(\mem_top_ipin_0.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_1_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_0.mux_l1_in_2_ (
.A0(chanx_right_in[4]),
.A1(chanx_left_in[4]),
.S(\mem_top_ipin_0.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_2_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_0.mux_l2_in_0_ (
.A0(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_1_X ),
.A1(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_0_X ),
.S(\mem_top_ipin_0.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_3_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_0.mux_l2_in_1_ (
.A0(chanx_left_in[10]),
.A1(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_2_X ),
.S(\mem_top_ipin_0.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_4_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_0.mux_l2_in_2_ (
.A0(chanx_left_in[16]),
.A1(chanx_right_in[10]),
.S(\mem_top_ipin_0.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_5_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_0.mux_l2_in_3_ (
.A0(_00_),
.A1(chanx_right_in[16]),
.S(\mem_top_ipin_0.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_6_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_0.mux_l3_in_0_ (
.A0(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_4_X ),
.A1(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_3_X ),
.S(\mem_top_ipin_0.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_7_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_0.mux_l3_in_1_ (
.A0(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_6_X ),
.A1(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_5_X ),
.S(\mem_top_ipin_0.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_8_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_0.mux_l4_in_0_ (
.A0(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_8_X ),
.A1(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_7_X ),
.S(\mem_top_ipin_0.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_9_X )
);
sky130_fd_sc_hd__buf_4 \mux_top_ipin_0.sky130_fd_sc_hd__buf_4_0_ (
.A(\mux_top_ipin_0.sky130_fd_sc_hd__mux2_1_9_X ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(bottom_grid_pin_0_)
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_1.mux_l1_in_0_ (
.A0(chanx_right_in[1]),
.A1(chanx_left_in[1]),
.S(\mem_top_ipin_1.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_0_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_1.mux_l1_in_1_ (
.A0(chanx_right_in[3]),
.A1(chanx_left_in[3]),
.S(\mem_top_ipin_1.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_1_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_1.mux_l1_in_2_ (
.A0(chanx_right_in[5]),
.A1(chanx_left_in[5]),
.S(\mem_top_ipin_1.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_2_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_1.mux_l2_in_0_ (
.A0(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_1_X ),
.A1(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_0_X ),
.S(\mem_top_ipin_1.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_3_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_1.mux_l2_in_1_ (
.A0(chanx_left_in[11]),
.A1(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_2_X ),
.S(\mem_top_ipin_1.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_4_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_1.mux_l2_in_2_ (
.A0(chanx_left_in[17]),
.A1(chanx_right_in[11]),
.S(\mem_top_ipin_1.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_5_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_1.mux_l2_in_3_ (
.A0(_01_),
.A1(chanx_right_in[17]),
.S(\mem_top_ipin_1.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_6_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_1.mux_l3_in_0_ (
.A0(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_4_X ),
.A1(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_3_X ),
.S(\mem_top_ipin_1.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_7_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_1.mux_l3_in_1_ (
.A0(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_6_X ),
.A1(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_5_X ),
.S(\mem_top_ipin_1.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_8_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_1.mux_l4_in_0_ (
.A0(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_8_X ),
.A1(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_7_X ),
.S(\mem_top_ipin_1.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_9_X )
);
sky130_fd_sc_hd__buf_4 \mux_top_ipin_1.sky130_fd_sc_hd__buf_4_0_ (
.A(\mux_top_ipin_1.sky130_fd_sc_hd__mux2_1_9_X ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(bottom_grid_pin_2_)
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_2.mux_l1_in_0_ (
.A0(chanx_right_in[0]),
.A1(chanx_left_in[0]),
.S(\mem_top_ipin_2.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_0_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_2.mux_l1_in_1_ (
.A0(chanx_right_in[2]),
.A1(chanx_left_in[2]),
.S(\mem_top_ipin_2.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_1_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_2.mux_l1_in_2_ (
.A0(chanx_right_in[6]),
.A1(chanx_left_in[6]),
.S(\mem_top_ipin_2.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_2_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_2.mux_l2_in_0_ (
.A0(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_1_X ),
.A1(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_0_X ),
.S(\mem_top_ipin_2.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_3_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_2.mux_l2_in_1_ (
.A0(chanx_left_in[12]),
.A1(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_2_X ),
.S(\mem_top_ipin_2.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_4_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_2.mux_l2_in_2_ (
.A0(chanx_left_in[18]),
.A1(chanx_right_in[12]),
.S(\mem_top_ipin_2.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_5_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_2.mux_l2_in_3_ (
.A0(_02_),
.A1(chanx_right_in[18]),
.S(\mem_top_ipin_2.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_6_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_2.mux_l3_in_0_ (
.A0(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_4_X ),
.A1(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_3_X ),
.S(\mem_top_ipin_2.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_7_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_2.mux_l3_in_1_ (
.A0(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_6_X ),
.A1(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_5_X ),
.S(\mem_top_ipin_2.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_8_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_2.mux_l4_in_0_ (
.A0(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_8_X ),
.A1(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_7_X ),
.S(\mem_top_ipin_2.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_9_X )
);
sky130_fd_sc_hd__buf_4 \mux_top_ipin_2.sky130_fd_sc_hd__buf_4_0_ (
.A(\mux_top_ipin_2.sky130_fd_sc_hd__mux2_1_9_X ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(bottom_grid_pin_4_)
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_3.mux_l1_in_0_ (
.A0(chanx_right_in[1]),
.A1(chanx_left_in[1]),
.S(\mem_top_ipin_3.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_0_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_3.mux_l1_in_1_ (
.A0(chanx_right_in[3]),
.A1(chanx_left_in[3]),
.S(\mem_top_ipin_3.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_1_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_3.mux_l1_in_2_ (
.A0(chanx_right_in[7]),
.A1(chanx_left_in[7]),
.S(\mem_top_ipin_3.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_2_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_3.mux_l2_in_0_ (
.A0(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_1_X ),
.A1(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_0_X ),
.S(\mem_top_ipin_3.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_3_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_3.mux_l2_in_1_ (
.A0(chanx_left_in[13]),
.A1(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_2_X ),
.S(\mem_top_ipin_3.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_4_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_3.mux_l2_in_2_ (
.A0(chanx_left_in[19]),
.A1(chanx_right_in[13]),
.S(\mem_top_ipin_3.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_5_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_3.mux_l2_in_3_ (
.A0(_03_),
.A1(chanx_right_in[19]),
.S(\mem_top_ipin_3.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_6_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_3.mux_l3_in_0_ (
.A0(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_4_X ),
.A1(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_3_X ),
.S(\mem_top_ipin_3.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_7_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_3.mux_l3_in_1_ (
.A0(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_6_X ),
.A1(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_5_X ),
.S(\mem_top_ipin_3.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_8_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_3.mux_l4_in_0_ (
.A0(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_8_X ),
.A1(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_7_X ),
.S(\mem_top_ipin_3.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_9_X )
);
sky130_fd_sc_hd__buf_4 \mux_top_ipin_3.sky130_fd_sc_hd__buf_4_0_ (
.A(\mux_top_ipin_3.sky130_fd_sc_hd__mux2_1_9_X ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(bottom_grid_pin_6_)
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_4.mux_l1_in_0_ (
.A0(chanx_right_in[0]),
.A1(chanx_left_in[0]),
.S(\mem_top_ipin_4.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_0_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_4.mux_l1_in_1_ (
.A0(chanx_right_in[2]),
.A1(chanx_left_in[2]),
.S(\mem_top_ipin_4.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_1_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_4.mux_l1_in_2_ (
.A0(chanx_right_in[4]),
.A1(chanx_left_in[4]),
.S(\mem_top_ipin_4.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_2_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_4.mux_l2_in_0_ (
.A0(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_1_X ),
.A1(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_0_X ),
.S(\mem_top_ipin_4.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_3_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_4.mux_l2_in_1_ (
.A0(chanx_left_in[8]),
.A1(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_2_X ),
.S(\mem_top_ipin_4.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_4_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_4.mux_l2_in_2_ (
.A0(chanx_left_in[14]),
.A1(chanx_right_in[8]),
.S(\mem_top_ipin_4.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_5_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_4.mux_l2_in_3_ (
.A0(_04_),
.A1(chanx_right_in[14]),
.S(\mem_top_ipin_4.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_6_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_4.mux_l3_in_0_ (
.A0(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_4_X ),
.A1(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_3_X ),
.S(\mem_top_ipin_4.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_7_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_4.mux_l3_in_1_ (
.A0(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_6_X ),
.A1(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_5_X ),
.S(\mem_top_ipin_4.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_8_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_4.mux_l4_in_0_ (
.A0(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_8_X ),
.A1(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_7_X ),
.S(\mem_top_ipin_4.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_9_X )
);
sky130_fd_sc_hd__buf_4 \mux_top_ipin_4.sky130_fd_sc_hd__buf_4_0_ (
.A(\mux_top_ipin_4.sky130_fd_sc_hd__mux2_1_9_X ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(bottom_grid_pin_8_)
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_5.mux_l1_in_0_ (
.A0(chanx_right_in[1]),
.A1(chanx_left_in[1]),
.S(\mem_top_ipin_5.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_0_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_5.mux_l1_in_1_ (
.A0(chanx_right_in[3]),
.A1(chanx_left_in[3]),
.S(\mem_top_ipin_5.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_1_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_5.mux_l1_in_2_ (
.A0(chanx_right_in[5]),
.A1(chanx_left_in[5]),
.S(\mem_top_ipin_5.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_2_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_5.mux_l2_in_0_ (
.A0(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_1_X ),
.A1(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_0_X ),
.S(\mem_top_ipin_5.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_3_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_5.mux_l2_in_1_ (
.A0(chanx_left_in[9]),
.A1(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_2_X ),
.S(\mem_top_ipin_5.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_4_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_5.mux_l2_in_2_ (
.A0(chanx_left_in[15]),
.A1(chanx_right_in[9]),
.S(\mem_top_ipin_5.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_5_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_5.mux_l2_in_3_ (
.A0(_05_),
.A1(chanx_right_in[15]),
.S(\mem_top_ipin_5.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_6_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_5.mux_l3_in_0_ (
.A0(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_4_X ),
.A1(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_3_X ),
.S(\mem_top_ipin_5.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_7_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_5.mux_l3_in_1_ (
.A0(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_6_X ),
.A1(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_5_X ),
.S(\mem_top_ipin_5.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_8_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_5.mux_l4_in_0_ (
.A0(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_8_X ),
.A1(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_7_X ),
.S(\mem_top_ipin_5.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_9_X )
);
sky130_fd_sc_hd__buf_4 \mux_top_ipin_5.sky130_fd_sc_hd__buf_4_0_ (
.A(\mux_top_ipin_5.sky130_fd_sc_hd__mux2_1_9_X ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(bottom_grid_pin_10_)
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_6.mux_l1_in_0_ (
.A0(chanx_right_in[0]),
.A1(chanx_left_in[0]),
.S(\mem_top_ipin_6.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_0_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_6.mux_l1_in_1_ (
.A0(chanx_right_in[2]),
.A1(chanx_left_in[2]),
.S(\mem_top_ipin_6.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_1_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_6.mux_l1_in_2_ (
.A0(chanx_right_in[6]),
.A1(chanx_left_in[6]),
.S(\mem_top_ipin_6.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_2_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_6.mux_l2_in_0_ (
.A0(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_1_X ),
.A1(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_0_X ),
.S(\mem_top_ipin_6.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_3_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_6.mux_l2_in_1_ (
.A0(chanx_left_in[10]),
.A1(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_2_X ),
.S(\mem_top_ipin_6.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_4_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_6.mux_l2_in_2_ (
.A0(chanx_left_in[16]),
.A1(chanx_right_in[10]),
.S(\mem_top_ipin_6.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_5_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_6.mux_l2_in_3_ (
.A0(_06_),
.A1(chanx_right_in[16]),
.S(\mem_top_ipin_6.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_6_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_6.mux_l3_in_0_ (
.A0(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_4_X ),
.A1(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_3_X ),
.S(\mem_top_ipin_6.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_7_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_6.mux_l3_in_1_ (
.A0(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_6_X ),
.A1(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_5_X ),
.S(\mem_top_ipin_6.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_8_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_6.mux_l4_in_0_ (
.A0(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_8_X ),
.A1(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_7_X ),
.S(\mem_top_ipin_6.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_9_X )
);
sky130_fd_sc_hd__buf_4 \mux_top_ipin_6.sky130_fd_sc_hd__buf_4_0_ (
.A(\mux_top_ipin_6.sky130_fd_sc_hd__mux2_1_9_X ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(bottom_grid_pin_12_)
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_7.mux_l1_in_0_ (
.A0(chanx_right_in[1]),
.A1(chanx_left_in[1]),
.S(\mem_top_ipin_7.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_0_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_7.mux_l1_in_1_ (
.A0(chanx_right_in[3]),
.A1(chanx_left_in[3]),
.S(\mem_top_ipin_7.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_1_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_7.mux_l1_in_2_ (
.A0(chanx_right_in[7]),
.A1(chanx_left_in[7]),
.S(\mem_top_ipin_7.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_2_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_7.mux_l2_in_0_ (
.A0(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_1_X ),
.A1(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_0_X ),
.S(\mem_top_ipin_7.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_3_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_7.mux_l2_in_1_ (
.A0(chanx_left_in[11]),
.A1(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_2_X ),
.S(\mem_top_ipin_7.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_4_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_7.mux_l2_in_2_ (
.A0(chanx_left_in[17]),
.A1(chanx_right_in[11]),
.S(\mem_top_ipin_7.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_5_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_7.mux_l2_in_3_ (
.A0(_07_),
.A1(chanx_right_in[17]),
.S(\mem_top_ipin_7.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_6_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_7.mux_l3_in_0_ (
.A0(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_4_X ),
.A1(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_3_X ),
.S(\mem_top_ipin_7.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_7_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_7.mux_l3_in_1_ (
.A0(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_6_X ),
.A1(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_5_X ),
.S(\mem_top_ipin_7.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_8_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_7.mux_l4_in_0_ (
.A0(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_8_X ),
.A1(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_7_X ),
.S(\mem_top_ipin_7.ccff_tail ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_9_X )
);
sky130_fd_sc_hd__buf_4 \mux_top_ipin_7.sky130_fd_sc_hd__buf_4_0_ (
.A(\mux_top_ipin_7.sky130_fd_sc_hd__mux2_1_9_X ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(bottom_grid_pin_14_)
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_8.mux_l1_in_0_ (
.A0(chanx_right_in[0]),
.A1(chanx_left_in[0]),
.S(\mem_top_ipin_8.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_0_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_8.mux_l1_in_1_ (
.A0(chanx_right_in[2]),
.A1(chanx_left_in[2]),
.S(\mem_top_ipin_8.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_1_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_8.mux_l1_in_2_ (
.A0(chanx_right_in[8]),
.A1(chanx_left_in[8]),
.S(\mem_top_ipin_8.mem_out[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_2_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_8.mux_l2_in_0_ (
.A0(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_1_X ),
.A1(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_0_X ),
.S(\mem_top_ipin_8.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_3_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_8.mux_l2_in_1_ (
.A0(chanx_left_in[12]),
.A1(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_2_X ),
.S(\mem_top_ipin_8.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_4_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_8.mux_l2_in_2_ (
.A0(chanx_left_in[18]),
.A1(chanx_right_in[12]),
.S(\mem_top_ipin_8.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_5_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_8.mux_l2_in_3_ (
.A0(_08_),
.A1(chanx_right_in[18]),
.S(\mem_top_ipin_8.mem_out[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_6_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_8.mux_l3_in_0_ (
.A0(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_4_X ),
.A1(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_3_X ),
.S(\mem_top_ipin_8.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_7_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_8.mux_l3_in_1_ (
.A0(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_6_X ),
.A1(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_5_X ),
.S(\mem_top_ipin_8.mem_out[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_8_X )
);
sky130_fd_sc_hd__mux2_1 \mux_top_ipin_8.mux_l4_in_0_ (
.A0(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_8_X ),
.A1(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_7_X ),
.S(\logical_tile_io_mode_io__0.ccff_head ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_9_X )
);
sky130_fd_sc_hd__buf_4 \mux_top_ipin_8.sky130_fd_sc_hd__buf_4_0_ (
.A(\mux_top_ipin_8.sky130_fd_sc_hd__mux2_1_9_X ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(bottom_grid_pin_16_)
);
sky130_fd_sc_hd__buf_8 prog_clk_0_FTB00 (
.A(prog_clk_0_N_in),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(\logical_tile_io_mode_io__0.ltile_phy_iopad_0.EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem.prog_clk )
);
sky130_fd_sc_hd__buf_4 prog_clk_0_W_FTB01 (
.A(prog_clk_0_N_in),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(prog_clk_0_W_out)
);
endmodule