commit | 998d9fc83a47b82f46600089f336186e2ae36a44 | [log] [tgz] |
---|---|---|
author | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Mon Dec 14 19:02:22 2020 +0200 |
committer | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Mon Dec 14 19:02:22 2020 +0200 |
tree | 3c5cb16a0e328c8b1522a232e792c39c6d3b4fb8 | |
parent | 5bbbf16437e7083b84940050bd395963fcd3895c [diff] |
Fix the driver of the user2_vcc_powergood signal
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v index 8cb927f..25e0b8e 100644 --- a/verilog/rtl/mgmt_protect.v +++ b/verilog/rtl/mgmt_protect.v
@@ -330,7 +330,7 @@ .VPB(vccd), .VNB(vssd), `endif - .A(mprj2_vdd_logic1), + .A(mprj2_logic1), .X(user2_vcc_powergood) );