| commit | 7ff44e2e6a1b29193f0bc978ceb3d5e2f92e6ae1 | [log] [tgz] |
|---|---|---|
| author | Manar <manarabdelatty@aucegypt.edu> | Sat Jan 23 16:16:38 2021 +0200 |
| committer | GitHub <noreply@github.com> | Sat Jan 23 16:16:38 2021 +0200 |
| tree | 8d50f90b7a2b9a3b30e075d3dbad18de3377fadb | |
| parent | c258939eee1fa721ab449bb72c69390bbe1283e1 [diff] |
Update README.md
diff --git a/README.md b/README.md index 50a6a67..f98daaa 100644 --- a/README.md +++ b/README.md
@@ -8,7 +8,7 @@ The SoC utilizes the caravel IO ports and logic analyzer probes. Refer to [user_project_wrapper.v](verilog/rtl/user_project_wrapper.v) -| Caravel-IO | Chameloen SoC | Mode +| Caravel-IO | EL2 SoC | Mode | ------------- | ------------- | ------------- | io[13:0] | GPIO | Bi-directional | io[17:14] | flash | Bi-directional