verilog/rtl/multiply_4.v

/* Generated by Yosys 0.9+3743 (git sha1 UNKNOWN, clang 7.0.1-8+deb10u2 -fPIC -Os) */

module multiply_4(
`ifdef USE_POWER_PINS
	vccd1, vssd1,
`endif
	clk, m_in, m_out);
`ifdef USE_POWER_PINS
  inout vccd1;
  inout vssd1;
`endif
  wire [127:0] _00_;
  wire [127:0] _01_;
  wire [127:0] _02_;
  wire [127:0] _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  input clk;
  reg [258:0] m = 259'h00000000000000000000000000000000000000000000000000000000000000000;
  input [258:0] m_in;
  output [129:0] m_out;
  reg overflow;
  wire ovf_in;
  reg [523:0] r = 524'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
  always @(posedge clk)
    m <= m_in;
  always @(posedge clk)
    r <= { m[258:257], _01_, m[0], r[523:131] };
  always @(posedge clk)
    overflow <= ovf_in;
  assign _00_ = $signed({ 64'h0000000000000000, m[64:1] }) * $signed({ 64'h0000000000000000, m[128:65] });
  assign _01_ = _00_ + m[256:129];
  assign _02_ = ~ r[259:132];
  assign _03_ = r[261] ? _02_ : r[259:132];
  assign _04_ = | _03_[63:31];
  assign _05_ = & _03_[63:31];
  assign _06_ = ~ _05_;
  assign _07_ = _04_ & _06_;
  assign _08_ = | _03_[127:63];
  assign _09_ = & _03_[127:63];
  assign _10_ = ~ _09_;
  assign _11_ = _08_ & _10_;
  assign ovf_in = r[260] ? _07_ : _11_;
  assign m_out = { overflow, _03_, r[131] };
endmodule