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foss-eda-tools/third_party/shuttle/sky130/mpw-001/slot-026/ed2f1269eb90f5d3b74e2f3aecedec74590001e0^!/.
commit
ed2f1269eb90f5d3b74e2f3aecedec74590001e0
[log]
author
manarabdelaty <manarabdelatty@aucegypt.edu>
Wed Jan 06 16:16:44 2021 +0200
committer
manarabdelaty <manarabdelatty@aucegypt.edu>
Wed Jan 06 16:16:44 2021 +0200
tree
0ba71d06151ba62f9e5476e398bdc7100ab9e44e
parent
b7e1861538052839e5b9d01a8a546e3e489ed44f [diff]
Removed include directives from caravel.v

diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index ed2a990..de2aaac 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v

@@ -24,7 +24,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 
 module gpio_tb;

diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
index 50ea981..a0176fa 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v

@@ -20,7 +20,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 `include "tbuart.v"
 

diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
index d6e2576..9abcf76 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v

@@ -24,7 +24,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 
 module mem_tb;

diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index ae04001..cc619dd 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v

@@ -17,7 +17,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 
 module mprj_ctrl_tb;

diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
index bb141e1..6b5bc38 100644
--- a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v

@@ -20,7 +20,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 `include "tbuart.v"
 

diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
index 5e63d0f..08d9401 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v

@@ -24,7 +24,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 
 module perf_tb;

diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
index fe5e606..58b70ea 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v

@@ -17,7 +17,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 
 module pll_tb;

diff --git a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
index 40ac3b8..8a122ff 100644
--- a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v

@@ -24,7 +24,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 
 module storage_tb;

diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
index b2e6b49..5be1b5b 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v

@@ -17,7 +17,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 
 module sysctrl_tb;

diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
index 9db1598..9956e19 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v

@@ -24,7 +24,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 
 module timer_tb;

diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
index 61c304f..6fc0501 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v

@@ -24,7 +24,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 
 module timer2_tb;

diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
index 7ac8ebe..ee5df0b 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v

@@ -24,7 +24,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 `include "tbuart.v"
 

diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index 3a98f7a..e644347 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v

@@ -17,7 +17,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 
 module io_ports_tb;

diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
index 8f07fe4..125f842 100644
--- a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v

@@ -17,7 +17,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 `include "tbuart.v"
 

diff --git a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
index a0e7fcf..d004269 100644
--- a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v

@@ -17,7 +17,7 @@
 
 `timescale 1 ns / 1 ps
 
-`include "caravel.v"
+`include "caravel_netlists.v"
 `include "spiflash.v"
 
 module la_test2_tb;

diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index ea844ca..a2cd1e1 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v

@@ -25,71 +25,6 @@
 /*                                                          	*/
 /*--------------------------------------------------------------*/
 
-`timescale 1 ns / 1 ps
-
-`define UNIT_DELAY #1
-
-`ifdef SIM
-
-`define USE_POWER_PINS
-
-`include "defines.v"
-`include "pads.v"
-
-/* NOTE: Need to pass the PDK root directory to iverilog with option -I */
-
-`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
-`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
-`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v"
-
-`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
-`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
-`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
-`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
-
-`ifdef GL
-	`include "gl/mgmt_core.v"
-	`include "gl/digital_pll.v"
-	`include "gl/DFFRAM.v"
-	`include "gl/storage.v"
-	`include "gl/user_id_programming.v"
-	`include "gl/chip_io.v"
-`else
-	`include "mgmt_soc.v"
-	`include "housekeeping_spi.v"
-	`include "caravel_clocking.v"
-	`include "mgmt_core.v"
-	`include "digital_pll.v"
-	`include "DFFRAM.v"
-	`include "DFFRAMBB.v"
-	`include "storage.v"
-	`include "user_id_programming.v"
-	`include "clock_div.v"
-	`include "storage_bridge_wb.v"
-	`include "mprj_io.v"
-	`include "chip_io.v"
-`endif
-
-`include "mprj_logic_high.v"
-`include "mprj2_logic_high.v"
-`include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
-`include "mgmt_protect.v"
-`include "mgmt_protect_hv.v"
-`include "user_project_wrapper.v"
-`include "gpio_control_block.v"
-`include "simple_por.v"
-`include "sram_1rw1r_32_256_8_sky130.v"
-
-/*------------------------------*/
-/* Include user project here	*/
-/*------------------------------*/
-`include "user_proj_example.v"
-
-// `ifdef USE_OPENRAM
-//     `include "sram_1rw1r_32_256_8_sky130.v"
-// `endif
-`endif
-
 module caravel (
     inout vddio,	// Common 3.3V padframe/ESD power
     inout vssio,	// Common padframe/ESD ground

diff --git a/verilog/rtl/caravel_netlists.v b/verilog/rtl/caravel_netlists.v
new file mode 100644
index 0000000..66e6207
--- /dev/null
+++ b/verilog/rtl/caravel_netlists.v

@@ -0,0 +1,88 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1 ns / 1 ps
+
+`define UNIT_DELAY #1
+
+`ifdef SIM
+
+`define USE_POWER_PINS
+
+`include "defines.v"
+`include "pads.v"
+
+/* NOTE: Need to pass the PDK root directory to iverilog with option -I */
+
+`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
+`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
+`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v"
+
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+`ifdef GL
+	`include "gl/mgmt_core.v"
+	`include "gl/digital_pll.v"
+	`include "gl/DFFRAM.v"
+	`include "gl/storage.v"
+	`include "gl/user_id_programming.v"
+	`include "gl/chip_io.v"
+	`include "gl/mprj_logic_high.v"
+    `include "gl/mprj2_logic_high.v"
+	`include "gl/mgmt_protect.v"
+    `include "gl/mgmt_protect_hv.v"
+	`include "gl/gpio_control_block.v"
+	`include "gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
+	`include "gl/user_project_wrapper.v"
+    `include "gl/caravel.v"
+`else
+	`include "mgmt_soc.v"
+	`include "housekeeping_spi.v"
+	`include "caravel_clocking.v"
+	`include "mgmt_core.v"
+	`include "digital_pll.v"
+	`include "DFFRAM.v"
+	`include "DFFRAMBB.v"
+	`include "storage.v"
+	`include "user_id_programming.v"
+	`include "clock_div.v"
+	`include "storage_bridge_wb.v"
+	`include "mprj_io.v"
+	`include "chip_io.v"
+	`include "mprj_logic_high.v"
+    `include "mprj2_logic_high.v"
+	`include "mgmt_protect.v"
+    `include "mgmt_protect_hv.v"
+	`include "gpio_control_block.v"
+    `include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
+	`include "user_project_wrapper.v"
+    `include "caravel.v"
+`endif
+
+`include "simple_por.v"
+`include "sram_1rw1r_32_256_8_sky130.v"
+
+/*------------------------------*/
+/* Include user project here	*/
+/*------------------------------*/
+`include "user_proj_example.v"
+
+// `ifdef USE_OPENRAM
+//     `include "sram_1rw1r_32_256_8_sky130.v"
+// `endif
+`endif