blob: 5568f2b7a12cafe2404b546afb26789b22e96e75 [file] [log] [blame]
Supplementary figures
=====================
GPIO pads - management and user IO
----------------------------------
.. figure:: _static/gpio_pads.svg
:name: gpio_pads_management_and_user_io
:alt: GPIO pads - management and user IO
:align: center
GPIO pad structure - pads 0 (JTAG) and 1 (SDO)
----------------------------------------------
.. figure:: _static/single_gpio_pad_structure_used_for_pad_0_and_pad_1.svg
:name: gpio_pad_structure_pads_0_and_1
:alt: GPIO pad structure - pads 0 (JTAG) and 1 (SDO)
:align: center
GPIO pad structure - all pads except 0 and 1
--------------------------------------------
.. figure:: _static/single_gpio_pad_structure_used_all_pads_except_0_and_1.svg
:name: gpio_pad_structure_all_pads_except_0_and_1
:alt: GPIO pad structure - all pads except 0 and 1
:align: center
Die arrangement and pads
------------------------
.. figure:: _static/die_pads.svg
:name: die_arrangement_and_pads
:alt: Die arrangement and pads
:align: center
Die voltage clamp arrangement
-----------------------------
.. figure:: _static/voltage_clamp_arrangement.svg
:name: voltage_clamp_arrangement
:alt: Voltage clamp arrangement
:align: center
Die to WLCSP bond plan
------------------------
.. figure:: _static/bond_plan.svg
:name: bond_plan
:alt: Die to WLCSP bond plan
:align: center
Power domain splits
-------------------
.. figure:: _static/power_domain_splits.svg
:name: power_domain_splits
:alt: Power domain splits
:align: center
PCB example route pattern
-------------------------
.. figure:: _static/pcb_example_route_pattern.svg
:name: pcb_example_route_pattern
:alt: PCB example route pattern
:align: center