Correct vssa->vssd typo
- corrected the caravel GL netlist by hand
diff --git a/verilog/gl/caravel.v b/verilog/gl/caravel.v
index 12c5649..d8c68f1 100644
--- a/verilog/gl/caravel.v
+++ b/verilog/gl/caravel.v
@@ -3585,7 +3585,7 @@
.X(rstb_l)
);
mgmt_core soc (
- .VGND(vssa),
+ .VGND(vssd),
.VPWR(vccd),
.clock(clock_core),
.core_clk(caravel_clk),
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index c499b54..ea844ca 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -387,7 +387,7 @@
mgmt_core soc (
`ifdef USE_POWER_PINS
.VPWR(vccd),
- .VGND(vssa),
+ .VGND(vssd),
`endif
// GPIO (1 pin)
.gpio_out_pad(gpio_out_core),
diff --git a/verilog/rtl/manifest b/verilog/rtl/manifest
index e6c5cca..9d98a2c 100644
--- a/verilog/rtl/manifest
+++ b/verilog/rtl/manifest
@@ -1,5 +1,5 @@
b2feeb2a098894d5d731a5b011858a471e855d73 caravel_clocking.v
-6d7d0f129f9c0883d85bfa742a5ef3a113268301 caravel.v
+8bcc687573c5a210832e3ebf9bd6d1e741bf3c79 caravel.v
1b9ce3f6b401023bb0beab3c41cae3549c77026d chip_io.v
d772308bd2a72121d7ed9dcdd40c8e6cbbe4b43c clock_div.v
f937b52e53d45bdbe41bcbd07c65b41104c21756 convert_gpio_sigs.v
