Use DFFRAM behavioural when doing RTL simulation In RTL simluation we are doing almost gate level simulation of the DFFRAM which is very slow. Use the behavioural.

diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index 3c9e595..2b1c95b 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v

@@ -23,7 +23,9 @@
 
 // Type and size of soc_mem
 // `define USE_OPENRAM
+`ifndef SIM
 `define USE_CUSTOM_DFFRAM
+`endif
 // don't change the following without double checking addr widths
 `define MEM_WORDS 256
 
@@ -40,4 +42,4 @@
 
 // GPIO conrol default mode and enable
 `define DM_INIT 3'b110
-`define OENB_INIT 1'b1
\ No newline at end of file
+`define OENB_INIT 1'b1