[DV] remove GL option from pll tb

verilog/dv/caravel/mgmt_soc/pll/Makefile

diff --git a/verilog/dv/caravel/mgmt_soc/pll/Makefile b/verilog/dv/caravel/mgmt_soc/pll/Makefile
index f1f19aa..5946dd5 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/pll/Makefile
@@ -35,15 +35,9 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
 	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
 	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
 	$< -o $@ 
-else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
-	$< -o $@ 
-endif
 
 %.vcd: %.vvp
 	vvp $<

verilog/dv/caravel/mgmt_soc/pll/pll_tb.v

diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
index fd0f11e..fe5e606 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
@@ -57,24 +57,17 @@
 			$display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
-		`ifdef GL
-			$display ("Monitor: Timeout, Test PLL (GL) Failed");
-		`else
-			$display ("Monitor: Timeout, Test PLL (RTL) Failed");
-		`endif
-		 $display("%c[0m",27);
+		$display ("Monitor: Timeout, Test PLL (RTL) Failed");
+		$display("%c[0m",27);
 		$finish;
 	end
 
 	// Monitor
 	initial begin
 	    wait(checkbits == 16'hA040);
-		`ifdef GL
-			$display("Monitor: Test PLL (GL) Started");
-		`else
-			$display("Monitor: Test PLL (RTL) Started");
-		`endif
-
+		
+		$display("Monitor: Test PLL (RTL) Started");
+		
 	    wait(checkbits == 16'hA041);
             // $display("   SPI value = 0x%x (should be 0x04)", spivalue);
             // if(spivalue !== 32'h04) begin
@@ -89,12 +82,9 @@
             // end
 
 	    wait(checkbits == 16'hA090);
-		`ifdef GL
-            $display("Monitor: Test PLL (GL) Passed");
-		`else
-		    $display("Monitor: Test PLL (RTL) Passed");
-		`endif
-            $finish;
+
+		$display("Monitor: Test PLL (RTL) Passed");
+		$finish;
 	end
 
 	initial begin