Specify root module in mem_wb Makefile
diff --git a/verilog/dv/wb_utests/mem_wb/Makefile b/verilog/dv/wb_utests/mem_wb/Makefile
index f7dcab3..b018559 100644
--- a/verilog/dv/wb_utests/mem_wb/Makefile
+++ b/verilog/dv/wb_utests/mem_wb/Makefile
@@ -23,7 +23,7 @@
 all:  ${PATTERN:=.vcd}
 
 %.vvp: %_tb.v
-	iverilog -DFUNCTIONAL -I $(PDK_PATH) -I .. -I ../../../rtl \
+	iverilog -s mem_wb_tb -DFUNCTIONAL -I $(PDK_PATH) -I .. -I ../../../rtl \
 	$< -o $@
 
 %.vcd: %.vvp