| commit | 5186c68d29401283325c14e7d6e8846cb5bea57a | [log] [tgz] |
|---|---|---|
| author | manarabdelaty <manarabdelatty@aucegypt.edu> | Tue Jan 05 21:58:19 2021 +0200 |
| committer | manarabdelaty <manarabdelatty@aucegypt.edu> | Tue Jan 05 21:58:19 2021 +0200 |
| tree | 2fc0e6ffcbfb3371d74e6642e5b00acacdf0d15b | |
| parent | 35fdac0b9af8a0c018369f888eb932bbb7ca5a04 [diff] |
Specify root module in mem_wb Makefile
diff --git a/verilog/dv/wb_utests/mem_wb/Makefile b/verilog/dv/wb_utests/mem_wb/Makefile index f7dcab3..b018559 100644 --- a/verilog/dv/wb_utests/mem_wb/Makefile +++ b/verilog/dv/wb_utests/mem_wb/Makefile
@@ -23,7 +23,7 @@ all: ${PATTERN:=.vcd} %.vvp: %_tb.v - iverilog -DFUNCTIONAL -I $(PDK_PATH) -I .. -I ../../../rtl \ + iverilog -s mem_wb_tb -DFUNCTIONAL -I $(PDK_PATH) -I .. -I ../../../rtl \ $< -o $@ %.vcd: %.vvp