| commit | 4078e1ea8049ae5ca6a17c35c60e11f89a78c3f5 | [log] [tgz] |
|---|---|---|
| author | agorararmard <aagouhar@efabless.com> | Tue Jan 05 22:56:53 2021 +0200 |
| committer | agorararmard <aagouhar@efabless.com> | Tue Jan 05 22:56:53 2021 +0200 |
| tree | 2f2723c785cf9ee727b0ab3ba05d56ead3e441f6 | |
| parent | b7e1861538052839e5b9d01a8a546e3e489ed44f [diff] |
[DV] reduce power-up sequence time
diff --git a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v index 1a9c562..cfc82aa 100644 --- a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v +++ b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
@@ -59,7 +59,7 @@ initial begin // Power-up sequence power1 <= 1'b0; - #200; + #1; power1 <= 1'b1; end