[DV] reduce power-up sequence time

verilog/dv/wb_utests/mem_wb/mem_wb_tb.v

diff --git a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
index 1a9c562..cfc82aa 100644
--- a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
+++ b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
@@ -59,7 +59,7 @@
 
 	initial begin		// Power-up sequence
 		power1 <= 1'b0;
-		#200;
+		#1;
 		power1 <= 1'b1;
 	end