[DOC] replace slave and master with responder and controller
diff --git a/docs/source/description.rst b/docs/source/description.rst
index a15516b..1d6b485 100644
--- a/docs/source/description.rst
+++ b/docs/source/description.rst
@@ -19,7 +19,7 @@
* 1 SPI flash controller,
* 1 UART,
-* 1 SPI master,
+* 1 SPI controller,
* 2 counter-timers,
* 1 dedicated GPIO channel,
* 27 shared GPIO channels,
diff --git a/docs/source/housekeeping-spi.rst b/docs/source/housekeeping-spi.rst
index 9d2db0d..f55a10a 100644
--- a/docs/source/housekeeping-spi.rst
+++ b/docs/source/housekeeping-spi.rst
@@ -1,7 +1,7 @@
Housekeeping SPI
================
-The "housekeeping" SPI is an SPI slave that can be accessed from a remote host through a standard 4-pin serial interface.
+The "housekeeping" SPI is an SPI responder that can be accessed from a remote host through a standard 4-pin serial interface.
The SPI implementation is mode 0, with new data on ``SDI`` captured on the ``SCK`` rising edge, and output data presented on the falling edge of ``SCK`` (to be sampled on the next ``SCK`` rising edge).
The SPI pins are shared with user area GPIO.
@@ -73,7 +73,7 @@
* - ``11nnn000``
- Simultaneous Read/Write in n-byte mode (up to 7 bytes)
-.. note:: All other words are reserved and act as no-operation if not defined by the SPI slave module.
+.. note:: All other words are reserved and act as no-operation if not defined by the SPI responder module.
.. _housekeeping_spi_modes:
@@ -120,9 +120,9 @@
Under normal working conditions, the SPI should not need to be accessed unless it is to adjust the clock speed of the CPU.
All other functions are purely for test and debug.
-The housekeeping SPI can be accessed by the CPU from a running program by enabling the SPI master, and enabling the bit that connects the internal SPI master directly to the housekeeping SPI.
+The housekeeping SPI can be accessed by the CPU from a running program by enabling the SPI controller, and enabling the bit that connects the internal SPI controller directly to the housekeeping SPI.
This configuration then allows a program to read, for example, the user project ID of the chip.
-See the :doc:`SPI master description <spi>` for details.
+See the :doc:`SPI controller description <spi>` for details.
.. figure:: _static/housekeeping_spi_register_map.svg
:name: housekeeping_spi_register_map
diff --git a/docs/source/introduction.rst b/docs/source/introduction.rst
index fe58d6c..e8c9070 100644
--- a/docs/source/introduction.rst
+++ b/docs/source/introduction.rst
@@ -19,7 +19,7 @@
* :doc:`description` contains the general information about the Efabless Caravel "harness" SoC,
* :doc:`pinout` describes the pinout of the SoC,
* :doc:`gpio` describes GPIO and its registers,
-* :doc:`housekeeping-spi` describes the SPI slave that can be accessed from a remote host,
+* :doc:`housekeeping-spi` describes the SPI responder that can be accessed from a remote host,
* :doc:`qspi-flash` describes the QSPI flash controller,
* :doc:`external-clock` describes the source external clock for the CPU,
* :doc:`uart` describes the UART interface,
diff --git a/docs/source/irq.rst b/docs/source/irq.rst
index c243bab..e01f862 100644
--- a/docs/source/irq.rst
+++ b/docs/source/irq.rst
@@ -23,7 +23,7 @@
* - 7
- Assignable interrupt (see :ref:`reg_irq7_source`)
* - 9
- - SPI master data available, when enabled (see :ref:`reg_spi_config`)
+ - SPI controller data available, when enabled (see :ref:`reg_spi_config`)
* - 10
- Timer 0 expired, when enabled (see :ref:`reg_timer0_config`)
* - 11
diff --git a/docs/source/memory-mapped-io-summary.rst b/docs/source/memory-mapped-io-summary.rst
index c7e06b8..3f66741 100644
--- a/docs/source/memory-mapped-io-summary.rst
+++ b/docs/source/memory-mapped-io-summary.rst
@@ -47,9 +47,9 @@
* - `0x 23 00 00 08`
- Counter/Timer 1 reset value (:ref:`reg_timer1_data`)
* - `0x 24 00 00 00`
- - SPI master configuration register (:ref:`reg_spi_config`)
+ - SPI controller configuration register (:ref:`reg_spi_config`)
* - `0x 24 00 00 08`
- - SPI master data register (:ref:`reg_spi_data`)
+ - SPI controller data register (:ref:`reg_spi_data`)
* - `0x 25 00 00 00`
- Logic Analyzer Data 0
* - `0x 25 00 00 04`
@@ -94,12 +94,12 @@
- IRQ 7 input source (:ref:`reg_irq7_source`)
* - `0x 30 00 00 0`
- User area base.
- A user project may define additional Wishbone slave modules starting at this address.
+ A user project may define additional Wishbone responder modules starting at this address.
* - `0x 80 00 00 00`
- QSPI controller
* - `0x 90 00 00 00`
- :ref:`storage-area-sram`
* - `0x a0 00 00 00`
- - Any slave 1
+ - Any responder 1
* - `0x b0 00 00 00`
- - Any slave 2
+ - Any responder 2
diff --git a/docs/source/pinout.rst b/docs/source/pinout.rst
index f64590e..3bd3393 100644
--- a/docs/source/pinout.rst
+++ b/docs/source/pinout.rst
@@ -269,25 +269,25 @@
``spi_sdo``
- Digital out
- - Serial interface master data output
+ - Serial interface controller data output
* - F8
- .. _spi_sck:
``spi_sck``
- Digital out
- - Serial interface master clock
+ - Serial interface controller clock
* - E8
- .. _spi_csb:
``spi_csb``
- Digital out
- - Serial interface master chip select
+ - Serial interface controller chip select
* - E9
- .. _spi_sdi:
``spi_sdi``
- Digital in
- - Serial interface masterdata input
+ - Serial interface controller data input
* - C4
- .. _vddio:
diff --git a/docs/source/spi.rst b/docs/source/spi.rst
index 3324095..bb1ca89 100644
--- a/docs/source/spi.rst
+++ b/docs/source/spi.rst
@@ -1,5 +1,5 @@
-SPI Master
-==========
+SPI Controller
+==============
This section describes the SPI configuration registers.
@@ -45,9 +45,9 @@
- Values
* - 15
- Housekeeping
- - 0 - SPI master connected to external pins
+ - 0 - SPI controller connected to external pins
- 1 - SPI master connected directly to housekeeping SPI
+ 1 - SPI controller connected directly to housekeeping SPI
* - 14
- SPI interrupt enable
- 0 - interrupt disabled
@@ -85,7 +85,7 @@
1 - LSB first
* - 7-0
- prescaler
- - count (in master clock cycles) of 1/2 :ref:`SCK <sck>` cycle
+ - count (in controller clock cycles) of 1/2 :ref:`SCK <sck>` cycle
(default value 2). Clock rate formula:
`SPI clock rate = 2 * core_clock / (prescaler + 1)`
@@ -112,7 +112,7 @@
The byte at ``0x24000004`` holds the SPI data (either read or write).
-Reading to and writing from the SPI master is simply a matter of setting the required values in the configuration register, and writing values to or reading from ``reg_spi_data``.
+Reading to and writing from the SPI controller is simply a matter of setting the required values in the configuration register, and writing values to or reading from ``reg_spi_data``.
The protocol is similar to the UART.
A write operation will stall the CPU if an incomplete SPI transmission is still in progress.
@@ -123,4 +123,4 @@
.. note::
- There is no FIFO associated with the SPI master.
+ There is no FIFO associated with the SPI controller.
