Add files to get ready for submission.

openlane/user_project_wrapper/config.tcl

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 963caba..6c86648 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -19,9 +19,13 @@
 
 
 set ::env(CLOCK_PORT) "user_clock2"
-
 set ::env(CLOCK_PERIOD) "15"
 
+set ::env(GLB_RT_TILES) "16"
+
+#set ::env(PL_TARGET_DENSITY) "0.15"
+#set ::env(GLB_RT_ALLOW_CONGESTION) 1
+
 set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
 set ::env(DIODE_INSERTION_STRATEGY) 0
 

openlane/user_project_wrapper/interactive.tcl

diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index 04855a9..6a813f2 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -17,8 +17,11 @@
 
 #add_macro_placement mprj 1150 1700 N
 #add_macro_placement mprj 0 0 N
-add_macro_placement decred_hash_block0 272.00 460.0 S
-add_macro_placement decred_controller_block 1770.72 920.0 S
+add_macro_placement decred_hash_block0 133.28 368.0 S
+add_macro_placement decred_hash_block1 1593.92 368.0 S
+add_macro_placement decred_hash_block2 133.28 1919.58 S
+add_macro_placement decred_hash_block3 1593.92 1919.58 S
+add_macro_placement decred_controller_block 1360.0 1577.8 S
 
 manual_macro_placement f
 

verilog/rtl/decred_top/rtl/src/decred_defines.v

diff --git a/verilog/rtl/decred_top/rtl/src/decred_defines.v b/verilog/rtl/decred_top/rtl/src/decred_defines.v
index 49e6ca3..9329af8 100755
--- a/verilog/rtl/decred_top/rtl/src/decred_defines.v
+++ b/verilog/rtl/decred_top/rtl/src/decred_defines.v
@@ -1,5 +1,5 @@
 // Default setting marked with D for enabled
-`define NUMBER_OF_MACROS 1 // -- value required
+`define NUMBER_OF_MACROS 4 // -- value required
 `define USE_REG_WRITE_TO_HASHMACRO // D-- register write ops to hash macros
 `define USE_VARIABLE_NONCE_OFFSET // D--
 //`define USE_SYSTEM_VERILOG //  -- 

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 86814b1..85619f7 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -14,7 +14,7 @@
  *-------------------------------------------------------------
  */
 
-//`include "decred_top/rtl/src/decred_defines.v"
+`include "decred_top/rtl/src/decred_defines.v"
 
 module user_project_wrapper #(
     parameter BITS = 32
@@ -125,7 +125,6 @@
   );
 
 decred_hash_macro decred_hash_block0 (
-					  
       .CLK(m1_clk_local), 
       .HASH_EN(HASH_EN), 
       .MACRO_WR_SELECT(MACRO_WR_SELECT[0]),
@@ -137,7 +136,42 @@
       .DATA_FROM_HASH(DATA_FROM_HASH)
   );
 
+decred_hash_macro decred_hash_block1 (
+      .CLK(m1_clk_local), 
+      .HASH_EN(HASH_EN), 
+      .MACRO_WR_SELECT(MACRO_WR_SELECT[1]),
+      .DATA_TO_HASH(DATA_TO_HASH),
+      .MACRO_RD_SELECT(MACRO_RD_SELECT[1]),
+      .HASH_ADDR(HASH_ADDR),
+      .THREAD_COUNT(THREAD_COUNT[1]),
+      .DATA_AVAILABLE(DATA_AVAILABLE[1]),
+      .DATA_FROM_HASH(DATA_FROM_HASH)
+  );
 
+decred_hash_macro decred_hash_block2 (
+      .CLK(m1_clk_local), 
+      .HASH_EN(HASH_EN), 
+      .MACRO_WR_SELECT(MACRO_WR_SELECT[2]),
+      .DATA_TO_HASH(DATA_TO_HASH),
+      .MACRO_RD_SELECT(MACRO_RD_SELECT[2]),
+      .HASH_ADDR(HASH_ADDR),
+      .THREAD_COUNT(THREAD_COUNT[2]),
+      .DATA_AVAILABLE(DATA_AVAILABLE[2]),
+      .DATA_FROM_HASH(DATA_FROM_HASH)
+  );
+
+
+decred_hash_macro decred_hash_block3 (
+      .CLK(m1_clk_local), 
+      .HASH_EN(HASH_EN), 
+      .MACRO_WR_SELECT(MACRO_WR_SELECT[3]),
+      .DATA_TO_HASH(DATA_TO_HASH),
+      .MACRO_RD_SELECT(MACRO_RD_SELECT[3]),
+      .HASH_ADDR(HASH_ADDR),
+      .THREAD_COUNT(THREAD_COUNT[3]),
+      .DATA_AVAILABLE(DATA_AVAILABLE[3]),
+      .DATA_FROM_HASH(DATA_FROM_HASH)
+  );
 
 endmodule	// user_project_wrapper
 `default_nettype wire