Add files to get ready for submission.
diff --git a/openlane/decred_controller/final_summary_report.csv b/openlane/decred_controller/final_summary_report.csv
new file mode 100644
index 0000000..e67a457
--- /dev/null
+++ b/openlane/decred_controller/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/decred_controller,decred_controller,decred_controller,0h3m15s,0.04,32050.0,64100.0,60,475.45,1282,0,0,0,0,0,0,0,2,0,44343,9277,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,32686448,0.0,33.43,31.56,1.41,0.0,-1,1277,1308,277,308,0,0,0,1282,43,88,34,13,106,68,10,342,225,202,11,130,435,7,572,66.66666666666667,15.0,15.0,1,5,50,1,153.6,153.18,0.61,0.15,sky130_fd_sc_hd,4,3
diff --git a/openlane/decred_hash_macro/final_summary_report.csv b/openlane/decred_hash_macro/final_summary_report.csv
new file mode 100644
index 0000000..f72cbeb
--- /dev/null
+++ b/openlane/decred_hash_macro/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/decred_hash_macro,decred_hash_macro,decred_hash_macro,0h38m20s,1.2,40070.0,80140.0,-1,1502.34,48084,0,0,0,0,0,0,0,7,0,3478206,465061,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,2847300970,0.0,66.58,60.22,40.65,31.38,-1,48080,48102,7760,7782,0,0,0,48084,1006,2327,477,1172,3012,1177,1406,13771,7386,6617,30,718,15160,0,15878,66.66666666666667,15.0,15.0,1,5,50,1,153.6,153.18,0.61,0.15,sky130_fd_sc_hd,4,0
diff --git a/openlane/decred_top/final_summary_report.csv b/openlane/decred_top/final_summary_report.csv
new file mode 100644
index 0000000..4c25cce
--- /dev/null
+++ b/openlane/decred_top/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/decred_top,decred_top,decred_top,0h10m58s,9.52,0.21008403361344535,0.4201680672268907,0,3425.22,2,0,0,0,0,0,0,0,0,9,92701,283,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,0.26,0.3,0.02,0.03,-1,49,49,49,49,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,3400,106097,0,109497,66.66666666666667,15.0,15.0,3,5,50,1,153.6,153.18,0.15,0.15,sky130_fd_sc_hd,4,3
