| commit | 503e46d0c6da1cf57a54c4d4c20c382f431c4eeb | [log] [tgz] |
|---|---|---|
| author | DrAceX <dracex@hotmail.com> | Sat Dec 05 00:21:02 2020 -0500 |
| committer | DrAceX <dracex@hotmail.com> | Sat Dec 05 00:21:02 2020 -0500 |
| tree | e8186061159207959ec25d65d5c9297c1ca1c6b6 | |
| parent | 8fb06b77d52b8720e334ac0b132016ef7268b02a [diff] |
Change list: - standardized clock net names - converted FPGA to use clock_div block - moved resync to reg_bank as single point of CDC - fixed some basic whitespace cleanup - removed BYPASS_THIS_ASIC - created define for number of hash_macros - simplify macro selection - remove async resets
Follow the steps at https://github.com/efabless/openlane#quick-start. Note that as of the time of this writing, the develop branch of open lane was used (i.e., git clone https://github.com/efabless/openlane.git --branch develop). If the docker is run manually, you'll need to specify rc5 instead of rc4.
After make test succeeds, proceed to check out step next.
cd openlane/designs git clone https://github.com/SweeperAA/skywater130_decred_miner.git ./caravel cd caravel make uncompress
At this point, there are two ways build the decred ASIC flow. At the time of this writing, each option has it's own deficiencies but you can get some intermediate results.
Option 1: Build the macro independent of the caravel chip harness user space area.
cd caravel/openlane make decred_top
Option 2: Build the entire user space together with decred.
cd caravel/openlane make user_project_wrapper