tree e8186061159207959ec25d65d5c9297c1ca1c6b6
parent 8fb06b77d52b8720e334ac0b132016ef7268b02a
author DrAceX <dracex@hotmail.com> 1607145662 -0500
committer DrAceX <dracex@hotmail.com> 1607145662 -0500

Change list:
 - standardized clock net names
 - converted FPGA to use clock_div block
 - moved resync to reg_bank as single point of CDC
 - fixed some basic whitespace cleanup
 - removed BYPASS_THIS_ASIC
 - created define for number of hash_macros
 - simplify macro selection
 - remove async resets