Add caravel level DV tests, which required minor module renaming (and rebuilding) in decred_controller.v.
diff --git a/gds/caravel.gds.gz b/gds/caravel.gds.gz index 03ce608..ef370a6 100644 --- a/gds/caravel.gds.gz +++ b/gds/caravel.gds.gz Binary files differ
diff --git a/gds/caravel.mag b/gds/caravel.mag index e0ae518..4828cbb 100644 --- a/gds/caravel.mag +++ b/gds/caravel.mag
@@ -1,7 +1,7 @@ magic tech sky130A magscale 1 2 -timestamp 1608821425 +timestamp 1608867834 << checkpaint >> rect -1260 -1260 718860 1038860 << metal1 >> @@ -80750,187 +80750,187 @@ rect 459478 40175 459520 40411 rect 454976 40133 459520 40175 use user_id_programming user_id_value ../mag -timestamp 1608821425 +timestamp 1608867834 transform 1 0 656624 0 1 80926 box 0 0 7109 7077 use storage storage ../mag -timestamp 1608821425 +timestamp 1608867834 transform 1 0 52032 0 1 53156 box 0 0 88934 189234 use mgmt_core soc ../mag -timestamp 1608821425 +timestamp 1608867834 transform 1 0 210422 0 1 53602 box 0 0 430000 180000 use sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped rstb_level ../mag -timestamp 1608821425 +timestamp 1608867834 transform -1 0 137896 0 -1 51956 box -66 -83 5058 5000 use simple_por por ../mag -timestamp 1608821425 +timestamp 1608867834 transform 1 0 654176 0 -1 112880 box 25 11 11344 8338 use mgmt_protect mgmt_buffers ../mag -timestamp 1608821425 +timestamp 1608867834 transform 1 0 212180 0 1 246848 box -1586 -1605 201502 19557 use gpio_control_block gpio_control_bidir\[1\] ../mag -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 166200 box 0 0 33934 18344 use gpio_control_block gpio_control_bidir\[0\] -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 121000 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[36\] -timestamp 1608821425 +timestamp 1608867834 transform 1 0 8567 0 1 245800 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[37\] -timestamp 1608821425 +timestamp 1608867834 transform 1 0 8567 0 1 202600 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[2\] -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 211200 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[3\] -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 256400 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[33\] -timestamp 1608821425 +timestamp 1608867834 transform 1 0 8567 0 1 375400 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[34\] -timestamp 1608821425 +timestamp 1608867834 transform 1 0 8567 0 1 332200 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[35\] -timestamp 1608821425 +timestamp 1608867834 transform 1 0 8567 0 1 289000 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[4\] -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 301400 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[5\] -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 346400 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[7\] -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 479800 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[6\] -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 391600 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[32\] -timestamp 1608821425 +timestamp 1608867834 transform 1 0 8567 0 1 418600 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[31\] -timestamp 1608821425 +timestamp 1608867834 transform 1 0 8567 0 1 546200 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[30\] -timestamp 1608821425 +timestamp 1608867834 transform 1 0 8567 0 1 589400 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[29\] -timestamp 1608821425 +timestamp 1608867834 transform 1 0 8567 0 1 632600 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[9\] -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 568800 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[8\] -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 523800 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[10\] -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 614000 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[28\] -timestamp 1608821425 +timestamp 1608867834 transform 1 0 8567 0 1 675800 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[27\] -timestamp 1608821425 +timestamp 1608867834 transform 1 0 8567 0 1 719000 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[26\] -timestamp 1608821425 +timestamp 1608867834 transform 1 0 8567 0 1 762200 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[13\] -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 749200 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[12\] -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 704200 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[11\] -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 659000 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[25\] -timestamp 1608821425 +timestamp 1608867834 transform 1 0 8567 0 1 805400 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[24\] -timestamp 1608821425 +timestamp 1608867834 transform 1 0 8567 0 1 931224 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[23\] -timestamp 1608821425 +timestamp 1608867834 transform 0 1 97200 -1 0 1029747 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[22\] -timestamp 1608821425 +timestamp 1608867834 transform 0 1 148600 -1 0 1029747 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[21\] -timestamp 1608821425 +timestamp 1608867834 transform 0 1 200000 -1 0 1029747 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[20\] -timestamp 1608821425 +timestamp 1608867834 transform 0 1 251400 -1 0 1029747 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[19\] -timestamp 1608821425 +timestamp 1608867834 transform 0 1 303000 -1 0 1029747 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[18\] -timestamp 1608821425 +timestamp 1608867834 transform 0 1 353400 -1 0 1029747 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[17\] -timestamp 1608821425 +timestamp 1608867834 transform 0 1 420800 -1 0 1029747 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[16\] -timestamp 1608821425 +timestamp 1608867834 transform 0 1 497800 -1 0 1029747 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[15\] -timestamp 1608821425 +timestamp 1608867834 transform 0 1 549200 -1 0 1029747 box 0 0 33934 18344 use gpio_control_block gpio_control_in\[14\] -timestamp 1608821425 +timestamp 1608867834 transform -1 0 708537 0 1 927600 box 0 0 33934 18344 use user_project_wrapper mprj ../mag -timestamp 1608821425 +timestamp 1608867834 transform 1 0 65308 0 1 278716 box -8576 -7506 592500 711442 use chip_io padframe ../mag -timestamp 1608821425 +timestamp 1608867834 transform 1 0 0 0 1 0 box 0 0 717600 1037600 << properties >>
diff --git a/gds/caravel.old.gds.gz b/gds/caravel.old.gds.gz index 9173247..03ce608 100644 --- a/gds/caravel.old.gds.gz +++ b/gds/caravel.old.gds.gz Binary files differ
diff --git a/gds/decred_controller.gds.gz b/gds/decred_controller.gds.gz index 5d627be..bc8c6ea 100644 --- a/gds/decred_controller.gds.gz +++ b/gds/decred_controller.gds.gz Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz index 449637d..472bc30 100644 --- a/gds/user_project_wrapper.gds.gz +++ b/gds/user_project_wrapper.gds.gz Binary files differ
diff --git a/mag/decred_controller.mag b/mag/decred_controller.mag index e0186cf..4f25957 100644 --- a/mag/decred_controller.mag +++ b/mag/decred_controller.mag
@@ -1,7 +1,7 @@ magic tech sky130A magscale 1 2 -timestamp 1608335257 +timestamp 1608864223 << locali >> rect 7941 35479 7975 35785 rect 12265 35479 12299 35785
diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag index 126724e..11c9a6f 100644 --- a/mag/user_project_wrapper.mag +++ b/mag/user_project_wrapper.mag
@@ -1,7 +1,7 @@ magic tech sky130A magscale 1 2 -timestamp 1608818581 +timestamp 1608864388 << locali >> rect 259469 684777 259653 684811 rect 259469 684743 259503 684777 @@ -1298630,23 +1298630,23 @@ rect 569604 -7506 570204 -7504 rect 591900 -7506 592500 -7504 use decred_hash_macro decred_hash_block3 -timestamp 1608818581 +timestamp 1608864388 transform 1 0 319328 0 1 479320 box 0 0 244000 204000 use decred_hash_macro decred_hash_block2 -timestamp 1608818581 +timestamp 1608864388 transform 1 0 16320 0 1 479320 box 0 0 244000 204000 use decred_hash_macro decred_hash_block1 -timestamp 1608818581 +timestamp 1608864388 transform 1 0 319328 0 1 20332 box 0 0 244000 204000 use decred_hash_macro decred_hash_block0 -timestamp 1608818581 +timestamp 1608864388 transform 1 0 16320 0 1 20332 box 0 0 244000 204000 use decred_controller decred_controller_block -timestamp 1608818581 +timestamp 1608864388 transform 1 0 272000 0 1 315928 box 0 0 41000 41000 << labels >>
diff --git a/openlane/decred_controller/config.tcl b/openlane/decred_controller/config.tcl index 64c2e18..b2ff0e8 100755 --- a/openlane/decred_controller/config.tcl +++ b/openlane/decred_controller/config.tcl
@@ -7,7 +7,7 @@ $script_dir/../../verilog/rtl/defines.v \ $script_dir/../../verilog/rtl/decred_top/rtl/src/decred_defines.v \ $script_dir/../../verilog/rtl/decred_top/rtl/src/addressalyzer.v \ - $script_dir/../../verilog/rtl/decred_top/rtl/src/clock_div.v \ + $script_dir/../../verilog/rtl/decred_top/rtl/src/clock_div_simple.v \ $script_dir/../../verilog/rtl/decred_top/rtl/src/decred_controller.v \ $script_dir/../../verilog/rtl/decred_top/rtl/src/register_bank.v \ $script_dir/../../verilog/rtl/decred_top/rtl/src/spi_passthrough.v \
diff --git a/openlane/decred_controller/final_summary_report.csv b/openlane/decred_controller/final_summary_report.csv index 2bd8612..243746d 100644 --- a/openlane/decred_controller/final_summary_report.csv +++ b/openlane/decred_controller/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/decred_controller,decred_controller,decred_controller,0h3m24s,0.042025,35907.198096371205,71814.39619274241,63,492.32,1509,0,0,0,0,0,0,0,3,0,-1,53289,11014,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,37072678,0.0,37.41,35.24,1.96,1.17,-1,1502,1539,302,339,0,0,0,1509,48,32,35,12,105,70,9,460,288,285,12,134,448,7,589,66.66666666666667,15.0,15.0,1,5,50,1,153.6,153.18,0.65,0.15,sky130_fd_sc_hd,4,3 +0,/project/openlane/decred_controller,decred_controller,decred_controller,0h2m56s,0.042025,35098.155859607374,70196.31171921475,61,491.37,1475,0,0,0,0,0,0,0,0,0,-1,50575,10780,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,35079513,0.0,36.83,31.95,1.37,0.0,-1,1472,1503,294,325,0,0,0,1475,48,32,35,12,102,70,9,448,278,273,12,134,448,4,586,66.66666666666667,15.0,15.0,1,5,50,1,153.6,153.18,0.65,0.15,sky130_fd_sc_hd,4,3
diff --git a/verilog/dv/caravel/decred_miner/Makefile b/verilog/dv/caravel/decred_miner/Makefile new file mode 100755 index 0000000..7789bee --- /dev/null +++ b/verilog/dv/caravel/decred_miner/Makefile
@@ -0,0 +1,34 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + +# ---- Test patterns for project striVe ---- + +.SUFFIXES: +.SILENT: clean all + +PATTERNS = host_interface + +all: ${PATTERNS} + for i in ${PATTERNS}; do \ + ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \ + done + +clean: ${PATTERNS} + for i in ${PATTERNS}; do \ + ( cd $$i && make clean ) ; \ + done + +.PHONY: clean all
diff --git a/verilog/dv/caravel/decred_miner/README.md b/verilog/dv/caravel/decred_miner/README.md new file mode 100755 index 0000000..04f3837 --- /dev/null +++ b/verilog/dv/caravel/decred_miner/README.md
@@ -0,0 +1,27 @@ +<!--- +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 +--> +# decred_miner test(s) + +The directory includes a test for the decred_miner + +1) Host Interface Test: + + * Configures the user space pins as outputs, where required + * Initializes the decred_controller and executes a pre-determined test case resulting in the expected solution + * The test runs for approx 45min on slower machines and requires > 5GB disk space +
diff --git a/verilog/dv/caravel/decred_miner/host_interface/Makefile b/verilog/dv/caravel/decred_miner/host_interface/Makefile new file mode 100755 index 0000000..c4d3a49 --- /dev/null +++ b/verilog/dv/caravel/decred_miner/host_interface/Makefile
@@ -0,0 +1,62 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + +FIRMWARE_PATH =../.. +VERILOG_PATH =../../../.. +RTL_PATH =../../../../rtl/decred_top/rtl/src +UPW_PATH =../../../../rtl +IP_PATH=../../../../ip +BEHAVIOURAL_MODELS =../.. + +GCC_PATH?=/opt/riscv32/bin +GCC_PREFIX?=riscv32-unknown-elf +PDK_PATH?=$(PDK_ROOT)/sky130A + +SIM?=RTL + +.SUFFIXES: + +PATTERN = host_interface + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex + iverilog -DFUNCTIONAL -DSIM -DFULL_CHIP_SIM -I$(BEHAVIOURAL_MODELS) \ + -I$(PDK_PATH) -I$(IP_PATH) -I$(RTL_PATH) -I$(UPW_PATH) \ + $< $(RTL_PATH)/*.v -o $@ + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all
diff --git a/verilog/dv/caravel/decred_miner/host_interface/chip_support_tb.v b/verilog/dv/caravel/decred_miner/host_interface/chip_support_tb.v new file mode 100755 index 0000000..0425849 --- /dev/null +++ b/verilog/dv/caravel/decred_miner/host_interface/chip_support_tb.v
@@ -0,0 +1,36 @@ + + parameter REG_MACRO_ADDR = 0; + parameter REG_MACRO_DATA = 1; + parameter REG_MACRO_SEL = 2; + parameter REG_CONTROL = 3; + parameter REG_SPI_ADDR = 4; + parameter REG_MACRO_WREN = 5; + parameter REG_ID = 5; + parameter REG_MACROINFO = 6; + + parameter REG_READ_MACRO = 8'h80; + + parameter REG_ID_VALUE = 8'h11; + + parameter ALL_MACRO_MASK = 8'hFF; + + parameter CPLD_ENONCE_LEN = 8; + + parameter CONTROL_HASH_MASK_START = (1 << 0); + parameter CONTROL_HASH_MASK_STOP = (0 << 0); + parameter CONTROL_PERF_CTR_RUN = (1 << 2); + parameter CONTROL_LED_MASK_OFF = (0 << 3); + parameter CONTROL_LED_MASK_ON = (1 << 3); + parameter CONTROL_CLOCK_OFF = (1 << 4); + parameter CONTROL_CLOCK_ON = (0 << 4); + parameter CONTROL_ID_HIGH = (1 << 5); + parameter CONTROL_ID_LOW = (0 << 5); + + parameter BROADCAST_ADDR_VALUE = 8'h7f; + + parameter HASH_REG_MIDSTATE = 8'h00; + parameter HASH_REG_THRESHOLD = 8'h20; + parameter HASH_REG_HEADERDATA = 8'h24; + parameter HASH_REG_EXTRANONCE = 8'h34; + parameter HASH_REG_NONCEOFFSET = 8'h38; + parameter HASH_REG_STRIDEOFFSET = 8'h3B;
diff --git a/verilog/dv/caravel/decred_miner/host_interface/full_chip_input.dat b/verilog/dv/caravel/decred_miner/host_interface/full_chip_input.dat new file mode 100755 index 0000000..94998fb --- /dev/null +++ b/verilog/dv/caravel/decred_miner/host_interface/full_chip_input.dat
@@ -0,0 +1,15 @@ +36 19 c4 73 // midstate +0c e2 05 81 +72 a5 74 89 +5e 9a 5d 13 +ee c9 a9 dd +38 f3 cd db +21 88 97 8a +ca 07 fb a5 +00 00 00 fc // threshold +dd bb 06 00 // headerdata +ed 23 00 00 +4e 21 98 5e +07 00 00 00 +46 c3 f1 e9 // extranonce +
diff --git a/verilog/dv/caravel/decred_miner/host_interface/host_interface.c b/verilog/dv/caravel/decred_miner/host_interface/host_interface.c new file mode 100755 index 0000000..6e661f2 --- /dev/null +++ b/verilog/dv/caravel/decred_miner/host_interface/host_interface.c
@@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../../defs.h" + +/* + IO Test: + - Configures MPRJ lower 19-27 IO pins as outputs +*/ + +void main() +{ + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + + */ + + // Configure 19-27 IOs as user output + reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + +} +
diff --git a/verilog/dv/caravel/decred_miner/host_interface/host_interface_tb.v b/verilog/dv/caravel/decred_miner/host_interface/host_interface_tb.v new file mode 100755 index 0000000..6a49997 --- /dev/null +++ b/verilog/dv/caravel/decred_miner/host_interface/host_interface_tb.v
@@ -0,0 +1,731 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +`timescale 1 ns / 100 ps + +`include "caravel.v" +`include "spiflash.v" + +module host_interface_tb; + +`include "chip_support_tb.v" + +`ifndef FULL_CHIP_SIM +#error +printf("FULL_CHIP_SIM not defined); +`endif + + reg clock; + reg RSTB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + wire [7:0] mprj_io_0; + + assign mprj_io_0 = mprj_io[7:0]; + + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + parameter MAIN_CLK_HALF_PERIOD = 10; + parameter MAIN_CLK_PERIOD = 2 * MAIN_CLK_HALF_PERIOD; + + parameter SPI_CLK_QTR_PERIOD = 250; + parameter SPI_CLK_HALF_PERIOD = 2 * SPI_CLK_QTR_PERIOD; + parameter SPI_CLK_PERIOD = 2 * SPI_CLK_HALF_PERIOD; + + parameter BUFFER_SIZE = 56; + + //---------------------------------------------------------------- + // Register and Wire declarations. + //---------------------------------------------------------------- + reg tb_main_clk = 0; + reg tb_rst_n = 0; + + reg tb_sclk = 0; + reg tb_scsn = 1; + reg tb_mosi = 0; + + reg [7:0] miso_byte = 8'b0; + wire tb_miso; + wire tb_irq; + + // chain interconnect + wire miso_1_0; + wire miso_2_1; + + wire mosi_0_1; + wire mosi_1_2; + + wire irq_1_0; + wire irq_2_1; + + wire id_1_0; + wire id_2_1; + + wire scsn_0_1; + wire scsn_1_2; + + wire sclk_0_1; + wire sclk_1_2; + + wire rst_n_0_1; + wire rst_n_1_2; + + // globals + reg [7:0] read_memory[BUFFER_SIZE - 1:0]; + reg [7:0] read_memory_copy[BUFFER_SIZE - 1:0]; + reg [7:0] write_memory[BUFFER_SIZE - 1:0]; + reg [7:0] write_memory_copy[BUFFER_SIZE - 1:0]; + reg [7:0] input_data[BUFFER_SIZE - 1:0]; + reg [7:0] selectedDevAddr = 8'h00; + + reg [7:0] threadCount = 8'h00; + reg [7:0] macroCount = 8'h00; + reg [7:0] chainLength = 8'h00; + + reg [31 : 0] cycle_ctr; + reg display_cycle_ctr = 0; + reg display_ctrl_and_ctrs = 0; + reg display_qround = 0; + reg display_state = 0; + + integer file, i; + + assign mprj_io[18:8] = {1'b1, 1'b0, 1'b0, tb_mosi, tb_scsn, 2'b00, 1'b1, tb_main_clk, tb_sclk, tb_rst_n}; + assign scsn_0_1 = mprj_io[19:19]; + assign sclk_0_1 = mprj_io[20:20]; + assign mosi_0_1 = mprj_io[21:21]; + assign rst_n_0_1 = mprj_io[22:22]; + assign tb_miso = mprj_io[25:25]; + assign tb_irq = mprj_io[27:27]; + + //---------------------------------------------------------------- + // clk_gen + // + // Clock generator processes. + //---------------------------------------------------------------- + always + begin : main_clk_gen + #MAIN_CLK_HALF_PERIOD tb_main_clk = !tb_main_clk; + end + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + initial begin + + $dumpfile("host_interface.vcd"); + $dumpvars(0, host_interface_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (25) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end + + cycle_ctr = 0; + + # (MAIN_CLK_PERIOD) + # 300 + + # (0) tb_rst_n = 1'b0; + # (2* SPI_CLK_PERIOD) tb_rst_n = 1'b1; + # (SPI_CLK_HALF_PERIOD) + + # 100 chip_init_chain(); + + # 100 chip_write_nonce_offsets(); + + # 100 disable_asic_hash(); + + # 100 enable_asic_hash_clock(); + + # 0 read_input_data(); + + # 0 write_midstate(); + # 0 write_threshold(); + # 0 write_headerdata(); + # 0 write_extranonce(); + + display_cycle_ctr = 1; + display_ctrl_and_ctrs = 1; + display_qround = 1; + display_state = 1; + + # 0 enable_asic_hashing(); + + // wait for IRQ + wait (tb_irq == 1) #1 ; + + display_cycle_ctr = 0; + display_ctrl_and_ctrs = 0; + display_qround = 0; + display_state = 0; + + chip_find_and_select_next_macro(); + + read_enonce(); + + chip_disable_macro(); + + $display($time,"\t: Test complete"); + + $finish; + end + + initial begin + RSTB <= 1'b0; + #2000; + RSTB <= 1'b1; // Release reset + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + #200; + power3 <= 1'b1; + #200; + power4 <= 1'b1; + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD3V3 = power1; + wire VDD1V8 = power2; + wire USER_VDD3V3 = power3; + wire USER_VDD1V8 = power4; + wire VSS = 1'b0; + + //---------------------------------------------------------------- + // Generic memory interface routines + //---------------------------------------------------------------- + + task set_write_memory_16b ; + input [15:0] value; + + begin + + write_memory[0] = value[7:0]; + write_memory[1] = value[15:8]; + + end + endtask + + task set_write_memory_24b ; + input [23:0] value; + + begin + + write_memory[0] = value[7:0]; + write_memory[1] = value[15:8]; + write_memory[2] = value[23:16]; + + end + endtask + + task copy_write_buffer ; + begin : copy_write_buffer_block + integer i; + + for (i = 0; i < BUFFER_SIZE; i = i + 1) begin + + write_memory_copy[i] = write_memory[i]; + end + end + endtask + + //---------------------------------------------------------------- + // High level support functions. + //---------------------------------------------------------------- + + task read_input_data ; + begin : read_input_data_block + + $readmemh("full_chip_input.dat", input_data); + + end + endtask + + task copy_input_data ; + input [7:0] offset; + input [7:0] length; + + begin : copy_input_data_block + + integer i; + integer source; + + source = offset; + + for (i = 0; i < length; i = i +1) begin + + write_memory[i] = input_data[source]; + source = source + 1; + end + + end + endtask + + task read_enonce ; + begin : read_enonce_block + + integer i; + + chip_read_hashreg(0, CPLD_ENONCE_LEN); + + $display("Enonce read "); + for (i = 0; i < CPLD_ENONCE_LEN; i = i + 1) begin + $display("%x", read_memory_copy[i]); + end + + end + endtask + + task disable_asic_hash ; + begin : disable_asic_hash_block + + reg [7:0] controlByte; + + chip_set_selected_device(BROADCAST_ADDR_VALUE); + + // Turn off LED and clear HASH_EN along while clock is running + controlByte = CONTROL_LED_MASK_OFF | CONTROL_CLOCK_ON | CONTROL_ID_HIGH; + chip_write_controlreg(REG_CONTROL, controlByte); + + // Turn off LED and clear HASH_EN along with clock disable + controlByte = CONTROL_LED_MASK_OFF | CONTROL_CLOCK_OFF | CONTROL_ID_HIGH; + chip_write_controlreg(REG_CONTROL, controlByte); + + end + endtask + + task enable_asic_hash_clock ; + begin : enable_asic_hash_clock_block + + reg [7:0] controlByte; + + chip_set_selected_device(BROADCAST_ADDR_VALUE); + + // Set init status for macros + controlByte = CONTROL_LED_MASK_OFF | CONTROL_HASH_MASK_STOP | CONTROL_CLOCK_OFF | CONTROL_ID_HIGH; + chip_write_controlreg(REG_CONTROL, controlByte); + + controlByte = CONTROL_LED_MASK_OFF | CONTROL_HASH_MASK_STOP | CONTROL_CLOCK_ON | CONTROL_ID_HIGH; + chip_write_controlreg(REG_CONTROL, controlByte); + + end + endtask + + task enable_asic_hashing ; + begin : enable_asic_hashing_block + + reg [7:0] controlByte; + + chip_set_selected_device(BROADCAST_ADDR_VALUE); + + // Turn on LED and set HASH_EN + controlByte = CONTROL_LED_MASK_ON | CONTROL_HASH_MASK_START | CONTROL_CLOCK_ON | CONTROL_ID_HIGH; + chip_write_controlreg(REG_CONTROL, controlByte); + + end + endtask + + task write_midstate ; + begin : write_midstate_block + copy_input_data(0, 32); // prepare write from input file offset,length + chip_write_hashreg(ALL_MACRO_MASK, 8'h00, 32); + end + endtask + + task write_threshold ; + begin : write_threshold_block + copy_input_data(32, 4); // prepare write from input file offset,length + chip_write_hashreg(ALL_MACRO_MASK, 8'h20, 4); + end + endtask + + task write_headerdata ; + begin : write_headerdata_block + copy_input_data(36, 16); // prepare write from input file offset,length + chip_write_hashreg(ALL_MACRO_MASK, 8'h24, 16); + end + endtask + + task write_extranonce ; + begin : write_extranonce_block + copy_input_data(52, 4); // prepare write from input file offset,length + chip_write_hashreg(ALL_MACRO_MASK, 8'h34, 4); + end + endtask + + //---------------------------------------------------------------- + // SPI support routines. + //---------------------------------------------------------------- + + task spi_set_chipselect ; + input value; + + begin + + # 0 tb_scsn = value; + # SPI_CLK_HALF_PERIOD; + + end + endtask + + task spi_send_data ; + input [7:0] data ; + output [7:0] returnByte; + + integer i; + begin + + for (i = 8; i > 0; i = i - 1) begin + # 0 clock_data_bit(data[i - 1], returnByte[i - 1]); + end + # SPI_CLK_HALF_PERIOD; + end + endtask + + task clock_data_bit ; + input data ; + output bitOut; + begin + + # SPI_CLK_QTR_PERIOD tb_mosi = data; + # SPI_CLK_QTR_PERIOD tb_sclk = !tb_sclk; + # SPI_CLK_QTR_PERIOD tb_sclk = !tb_sclk; + bitOut = tb_miso; + # SPI_CLK_QTR_PERIOD tb_sclk = tb_sclk; + + end + endtask + + //---------------------------------------------------------------- + // ASIC interface routines. + //---------------------------------------------------------------- + + task chip_read_memory ; + input [15:0] address ; + input [15:0] len ; + + integer i; + begin : chip_read_mem_block + + reg [7:0] returnByte; + + spi_set_chipselect(0); + + spi_send_data(8'h80 | selectedDevAddr | address[15:8], returnByte); + spi_send_data(address[7:0], returnByte); + spi_send_data(8'hFF, returnByte); + + for (i = 0; i < len; i = i + 1) begin + spi_send_data(8'hFF, read_memory[i]); + end + + spi_set_chipselect(1); + + end + endtask + + task chip_write_memory ; + input [15:0] address ; + input [15:0] len ; + + integer i; + begin : chip_write_mem_block + + reg [7:0] returnByte; + + spi_set_chipselect(0); + + spi_send_data(selectedDevAddr | address[15:8], returnByte); + spi_send_data(address[7:0], returnByte); + + for (i = 0; i < len; i = i + 1) begin + spi_send_data(write_memory[i], read_memory[i]); + end + + spi_set_chipselect(1); + + end + endtask + + task chip_write_controlreg ; + input [7:0] address; + input [7:0] data; + + begin : task_chip_write_controlreg_block + + write_memory[0] = data; + chip_write_memory(address, 1); + + end + endtask + + task chip_read_hashreg ; + input [7:0] address ; + input [7:0] len ; + + begin : chip_read_hashreg_block + + reg [7:0] localAddr; + integer i; + + localAddr = address; + + for (i = 0; i < len; i = i + 1) begin + + chip_write_controlreg(REG_MACRO_ADDR, localAddr); + chip_read_memory(REG_READ_MACRO, 1); + read_memory_copy[i] = read_memory[0]; + + localAddr = localAddr + 1; + + end + end + + endtask + + task chip_write_hashreg ; + input [7:0] macroSelect; + input [7:0] address ; + input [7:0] len ; + + begin : chip_write_hashreg_block + + reg [7:0] localAddr; + integer i; + + localAddr = address; + + copy_write_buffer(); + + chip_write_controlreg(REG_MACRO_WREN, 0); + + for (i = 0; i < len; i = i + 1) begin + + chip_write_controlreg(REG_MACRO_ADDR, localAddr); + chip_write_controlreg(REG_MACRO_DATA, write_memory_copy[i]); + chip_write_controlreg(REG_MACRO_WREN, macroSelect); + chip_write_controlreg(REG_MACRO_WREN, 0); + + localAddr = localAddr + 1; + + end + end + + endtask + + task chip_set_selected_device ; + input [7:0] value ; + begin + selectedDevAddr = value; + end + endtask + + task chip_init_chain ; + + begin : chip_init_chain_block + + reg [7:0] addr; + reg running; + + addr = 0; + running = 1; + chainLength = 0; + + while (running) begin + + if (addr != 0) begin + + chip_write_controlreg(REG_CONTROL, CONTROL_ID_HIGH); + + end + + chip_set_selected_device(0); + addr = addr + 1; + + chip_write_controlreg(REG_SPI_ADDR, addr); + chip_set_selected_device(addr); + + chip_read_memory(REG_ID, 1); + + if (read_memory[0] == REG_ID_VALUE) begin + + chip_write_controlreg(REG_CONTROL, 0); + chainLength = chainLength + 1; + end else begin + + running = 0; + end + + end + + chip_set_selected_device(1); + chip_read_memory(REG_MACROINFO, 1); + + threadCount = read_memory[0] & 8'h0F; + macroCount = ((read_memory[0] >> 4) & 8'h0F); + + chip_set_selected_device(BROADCAST_ADDR_VALUE); + + $display("Detected %d devices with %d macros and %d threads", chainLength, macroCount, threadCount); + + end + endtask + + task chip_write_nonce_offsets ; + begin : chip_write_nonce_offsets_block + + reg [7:0] addr; + reg [23:0] nonceOffset; + reg [15:0] stride; + + integer i; + integer j; + + addr = 1; + nonceOffset = 24'h3feccf; // test mode linked to data input + stride = chainLength * macroCount * threadCount; + for (i = 0; i < chainLength; i = i + 1) begin + + chip_set_selected_device(addr); + addr = addr + 1; + + for (j = 0; j < macroCount; j = j + 1) begin + + set_write_memory_24b(nonceOffset); + chip_write_hashreg((1 << j), HASH_REG_NONCEOFFSET, 3); + + set_write_memory_16b(stride); + chip_write_hashreg((1 << j), HASH_REG_STRIDEOFFSET, 2); + + nonceOffset = nonceOffset + threadCount; + end + end + + chip_set_selected_device(BROADCAST_ADDR_VALUE); + + end + endtask + + task chip_find_and_select_next_macro ; + begin : chip_find_and_select_next_macro_block + + integer i; + reg [7:0] addr; + reg [7:0] activeMacro; + reg [7:0] foundOne; + + addr = 1; + foundOne = 0; + + for (i = 0; (foundOne == 0) && (i < chainLength); i = i + 1) begin + + chip_set_selected_device(addr); + chip_read_memory(REG_MACRO_SEL, 1); + activeMacro = read_memory[0]; + activeMacro = activeMacro & ((activeMacro ^ 8'hFF) + 1); + + if (activeMacro != 0) begin + foundOne = 1; + write_memory[0] = activeMacro; + chip_write_memory(REG_MACRO_SEL, 1); + + $display("Solution found on FPGA: %d Macro: %d", addr, activeMacro); + end + + addr = addr + 1; + end + end + endtask + + task chip_disable_macro ; + begin : chip_disable_macro_block + + reg [7:0] macro; + + macro = 0; + chip_write_memory(REG_MACRO_SEL, 1); + chip_set_selected_device(BROADCAST_ADDR_VALUE); + + end + endtask + + //---------------------------------------------------------------- + // Chip chain device(s) under test. + //---------------------------------------------------------------- + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("host_interface.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule +`default_nettype wire
diff --git a/verilog/rtl/decred_top/rtl/src/clock_div.v b/verilog/rtl/decred_top/rtl/src/clock_div_simple.v similarity index 96% rename from verilog/rtl/decred_top/rtl/src/clock_div.v rename to verilog/rtl/decred_top/rtl/src/clock_div_simple.v index 9c59430..459e99b 100755 --- a/verilog/rtl/decred_top/rtl/src/clock_div.v +++ b/verilog/rtl/decred_top/rtl/src/clock_div_simple.v
@@ -1,6 +1,6 @@ `timescale 1ns / 1ps -module clock_div ( +module clock_div_simple ( input wire iCLK, input wire RST,
diff --git a/verilog/rtl/decred_top/rtl/src/decred_controller.v b/verilog/rtl/decred_top/rtl/src/decred_controller.v index b9d9350..d2503b2 100755 --- a/verilog/rtl/decred_top/rtl/src/decred_controller.v +++ b/verilog/rtl/decred_top/rtl/src/decred_controller.v
@@ -82,7 +82,7 @@ wire s1_clk_local; wire s1_div_output; - clock_div clock_divBlock ( + clock_div_simple clock_divBlock ( .iCLK(m1_clk_local), .clk_out(s1_div_output), .RST(rst_local_m1)
diff --git a/verilog/rtl/decred_top/rtl/src/decred_defines.v b/verilog/rtl/decred_top/rtl/src/decred_defines.v index 9329af8..ef76e1f 100755 --- a/verilog/rtl/decred_top/rtl/src/decred_defines.v +++ b/verilog/rtl/decred_top/rtl/src/decred_defines.v
@@ -3,4 +3,3 @@ `define USE_REG_WRITE_TO_HASHMACRO // D-- register write ops to hash macros `define USE_VARIABLE_NONCE_OFFSET // D-- //`define USE_SYSTEM_VERILOG // -- -//`define FULL_CHIP_SIM // --