Remove verilog parameter and replace with existing define.

verilog/rtl/decred_top/rtl/src/decred.v

diff --git a/verilog/rtl/decred_top/rtl/src/decred.v b/verilog/rtl/decred_top/rtl/src/decred.v
index c923144..cb077ae 100755
--- a/verilog/rtl/decred_top/rtl/src/decred.v
+++ b/verilog/rtl/decred_top/rtl/src/decred.v
@@ -152,8 +152,7 @@
   // //////////////////////////////////////////////////////
   // Interface to regfile
 
-  regBank #(.NUM_OF_MACROS(`NUMBER_OF_MACROS))
-  regBankBlock (
+  regBank regBankBlock (
     .SPI_CLK(SPI_CLK),
     .RST(rst_local),
     .M1_CLK(M1_CLK),