| ,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/decred_top,decred_top,decred_top,0h17m27s,9.52,0.21008403361344535,0.4201680672268907,0,3424.68,2,0,0,0,0,0,0,0,0,9,104126,350,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,0.29,0.33,0.03,0.02,-1,53,53,53,53,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,3400,106097,0,109497,66.66666666666667,15.0,15.0,3,5,50,1,153.6,153.18,0.15,0.15,sky130_fd_sc_hd,4,3 |
