commit 0b92705c47bcf0dcca7f320780e43923f0bbf34e
author SweeperAA <64485414+SweeperAA@users.noreply.github.com> Sun Dec 06 16:46:26 2020 -0500
committer GitHub <noreply@github.com> Sun Dec 06 16:46:26 2020 -0500
tree df3258a6b21bccfef1083fe8f8504aa9621d3870
parent 0150cda2866eaaf6a631e1de434283352bd9fea2

Update user_project_wrapper.v

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index bf32469..30de619 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -98,8 +98,8 @@
 	.ID_toHost(analog_io[16]),
 	.CLK_LED(analog_io[17]),
 	.MISO_toHost(analog_io[18]),
-	.HASH_LED(analog_io[18]),
-	.IRQ_OUT_toHost(analog_io[19])
+	.HASH_LED(analog_io[19]),
+	.IRQ_OUT_toHost(analog_io[20])
     );
 
 endmodule	// user_project_wrapper