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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-024 / c5f6ddbc0ee03c905ee7e232f69c677776bafe21 / . / verilog / rtl / DFFRAMBB.v
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manarabdelaty1f670402021-02-01 05:45:23 -0500[diff] [blame]1// SPDX-FileCopyrightText: 2020 Efabless Corporation
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7// http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14// SPDX-License-Identifier: Apache-2.0
15
16`default_nettype none
17/*
18 Building blocks for DFF based RAM compiler for SKY130A
19 BYTE : 8 memory cells used as a building block for WORD module
20 WORD : 32-bit memory word with select and byte-level WE
21 DEC6x64 : 2x4 Binary Decoder
22 DEC6x64 : 6x64 Binary decoder
23 MUX4x1_32 : 32-bit 4x1 MUX
24 MUX2x1_32 : 32-bit 2x1 MUX
25 SRAM64x32 : Tri-state buffers based 64x32 DFF RAM
26 DFFRAM_COL4 : A single column of 4 SRAM64x32 blocks using 4x1 multiplexors
27*/
28/*
29 Author: Mohamed Shalan (mshalan@aucegypt.edu)
30*/
31
32module BYTE (
33`ifdef USE_POWER_PINS
34 input VPWR,
35 input VGND,
36`endif
37 input CLK,
38 input WE,
39 input SEL,
40 input [7:0] Di,
41 output [7:0] Do
42);
43
44 wire [7:0] q_wire;
45 wire we_wire;
46 wire SEL_B;
47 wire GCLK;
48
49 sky130_fd_sc_hd__inv_1 INV(
50 `ifdef USE_POWER_PINS
51 .VPWR(VPWR),
52 .VGND(VGND),
53 .VPB(VPWR),
54 .VNB(VGND),
55 `endif
56 .Y(SEL_B),
57 .A(SEL)
58 );
59
60 sky130_fd_sc_hd__and2_1 CGAND(
61 `ifdef USE_POWER_PINS
62 .VPWR(VPWR),
63 .VGND(VGND),
64 .VPB(VPWR),
65 .VNB(VGND),
66 `endif
67 .A(SEL),
68 .B(WE),
69 .X(we_wire)
70 );
71
72 sky130_fd_sc_hd__dlclkp_1 CG(
73 `ifdef USE_POWER_PINS
74 .VPWR(VPWR),
75 .VGND(VGND),
76 .VPB(VPWR),
77 .VNB(VGND),
78 `endif
79 .CLK(CLK),
80 .GCLK(GCLK),
81 .GATE(we_wire)
82 );
83
84 generate
85 genvar i;
86 for(i=0; i<8; i=i+1) begin : BIT
87 sky130_fd_sc_hd__dfxtp_1 FF (
88 `ifdef USE_POWER_PINS
89 .VPWR(VPWR),
90 .VGND(VGND),
91 .VPB(VPWR),
92 .VNB(VGND),
93 `endif
94 .D(Di[i]),
95 .Q(q_wire[i]),
96 .CLK(GCLK)
97 );
98
99 sky130_fd_sc_hd__ebufn_2 OBUF (
100 `ifdef USE_POWER_PINS
101 .VPWR(VPWR),
102 .VGND(VGND),
103 .VPB(VPWR),
104 .VNB(VGND),
105 `endif
106 .A(q_wire[i]),
107 .Z(Do[i]),
108 .TE_B(SEL_B)
109 );
110
111 end
112 endgenerate
113
114endmodule
115
116
117module WORD32 (
118`ifdef USE_POWER_PINS
119 input VPWR,
120 input VGND,
121`endif
122 input CLK,
123 input [3:0] WE,
124 input SEL,
125 input [31:0] Di,
126 output [31:0] Do
127);
128
129 BYTE B0 (
130 `ifdef USE_POWER_PINS
131 .VPWR(VPWR),
132 .VGND(VGND),
133 `endif
134 .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) );
135
136 BYTE B1 (
137 `ifdef USE_POWER_PINS
138 .VPWR(VPWR),
139 .VGND(VGND),
140 `endif
141 .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) );
142
143 BYTE B2 (
144 `ifdef USE_POWER_PINS
145 .VPWR(VPWR),
146 .VGND(VGND),
147 `endif
148 .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) );
149
150 BYTE B3 (
151 `ifdef USE_POWER_PINS
152 .VPWR(VPWR),
153 .VGND(VGND),
154 `endif
155 .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) );
156
157endmodule
158
159module DEC1x2 (
160`ifdef USE_POWER_PINS
161 input VPWR,
162 input VGND,
163`endif
164 input EN,
165 input [0:0] A,
166 output [1:0] SEL
167);
168 sky130_fd_sc_hd__and2b_2 AND1 (
169 `ifdef USE_POWER_PINS
170 .VPWR(VPWR),
171 .VGND(VGND),
172 .VPB(VPWR),
173 .VNB(VGND),
174 `endif
175 .X(SEL[0]),
176 .A_N(A),
177 .B(EN)
178 );
179
180 sky130_fd_sc_hd__and2_2 AND3 (
181 `ifdef USE_POWER_PINS
182 .VPWR(VPWR),
183 .VGND(VGND),
184 .VPB(VPWR),
185 .VNB(VGND),
186 `endif
187 .X(SEL[1]),
188 .A(A),
189 .B(A[0])
190 );
191
192endmodule
193
194module DEC2x4 (
195`ifdef USE_POWER_PINS
196 input VPWR,
197 input VGND,
198`endif
199 input EN,
200 input [1:0] A,
201 output [3:0] SEL
202);
203 sky130_fd_sc_hd__nor3b_4 AND0 (
204 `ifdef USE_POWER_PINS
205 .VPWR(VPWR),
206 .VGND(VGND),
207 .VPB(VPWR),
208 .VNB(VGND),
209 `endif
210 .Y(SEL[0]),
211 .A(A[0]),
212 .B(A[1]),
213 .C_N(EN)
214 );
215
216 sky130_fd_sc_hd__and3b_4 AND1 (
217 `ifdef USE_POWER_PINS
218 .VPWR(VPWR),
219 .VGND(VGND),
220 .VPB(VPWR),
221 .VNB(VGND),
222 `endif
223 .X(SEL[1]),
224 .A_N(A[1]),
225 .B(A[0]),
226 .C(EN)
227 );
228
229 sky130_fd_sc_hd__and3b_4 AND2 (
230 `ifdef USE_POWER_PINS
231 .VPWR(VPWR),
232 .VGND(VGND),
233 .VPB(VPWR),
234 .VNB(VGND),
235 `endif
236 .X(SEL[2]),
237 .A_N(A[0]),
238 .B(A[1]),
239 .C(EN)
240 );
241
242 sky130_fd_sc_hd__and3_4 AND3 (
243 `ifdef USE_POWER_PINS
244 .VPWR(VPWR),
245 .VGND(VGND),
246 .VPB(VPWR),
247 .VNB(VGND),
248 `endif
249 .X(SEL[3]),
250 .A(A[1]),
251 .B(A[0]),
252 .C(EN)
253 );
254
255endmodule
256
257module DEC3x8 (
258`ifdef USE_POWER_PINS
259 input VPWR,
260 input VGND,
261`endif
262 input EN,
263 input [2:0] A,
264 output [7:0] SEL
265);
266 sky130_fd_sc_hd__nor4b_2 AND0 (
267 `ifdef USE_POWER_PINS
268 .VPWR(VPWR),
269 .VGND(VGND),
270 .VPB(VPWR),
271 .VNB(VGND),
272 `endif
273 .Y(SEL[0]),
274 .A(A[0]),
275 .B(A[1]),
276 .C(A[2]),
277 .D_N(EN)
278 ); // 000
279
280 sky130_fd_sc_hd__and4bb_2 AND1 (
281 `ifdef USE_POWER_PINS
282 .VPWR(VPWR),
283 .VGND(VGND),
284 .VPB(VPWR),
285 .VNB(VGND),
286 `endif
287 .X(SEL[1]),
288 .A_N(A[2]),
289 .B_N(A[1]),
290 .C(A[0]),
291 .D(EN)
292 ); // 001
293
294 sky130_fd_sc_hd__and4bb_2 AND2 (
295 `ifdef USE_POWER_PINS
296 .VPWR(VPWR),
297 .VGND(VGND),
298 .VPB(VPWR),
299 .VNB(VGND),
300 `endif
301 .X(SEL[2]),
302 .A_N(A[2]),
303 .B_N(A[0]),
304 .C(A[1]),
305 .D(EN)
306 ); // 010
307
308 sky130_fd_sc_hd__and4b_2 AND3 (
309 `ifdef USE_POWER_PINS
310 .VPWR(VPWR),
311 .VGND(VGND),
312 .VPB(VPWR),
313 .VNB(VGND),
314 `endif
315 .X(SEL[3]),
316 .A_N(A[2]),
317 .B(A[1]),
318 .C(A[0]),
319 .D(EN)
320 ); // 011
321
322 sky130_fd_sc_hd__and4bb_2 AND4 (
323 `ifdef USE_POWER_PINS
324 .VPWR(VPWR),
325 .VGND(VGND),
326 .VPB(VPWR),
327 .VNB(VGND),
328 `endif
329 .X(SEL[4]),
330 .A_N(A[0]),
331 .B_N(A[1]),
332 .C(A[2]),
333 .D(EN)
334 ); // 100
335
336 sky130_fd_sc_hd__and4b_2 AND5 (
337 `ifdef USE_POWER_PINS
338 .VPWR(VPWR),
339 .VGND(VGND),
340 .VPB(VPWR),
341 .VNB(VGND),
342 `endif
343 .X(SEL[5]),
344 .A_N(A[1]),
345 .B(A[0]),
346 .C(A[2]),
347 .D(EN)
348 ); // 101
349
350 sky130_fd_sc_hd__and4b_2 AND6 (
351 `ifdef USE_POWER_PINS
352 .VPWR(VPWR),
353 .VGND(VGND),
354 .VPB(VPWR),
355 .VNB(VGND),
356 `endif
357 .X(SEL[6]),
358 .A_N(A[0]),
359 .B(A[1]),
360 .C(A[2]),
361 .D(EN)
362 ); // 110
363
364 sky130_fd_sc_hd__and4_2 AND7 (
365 `ifdef USE_POWER_PINS
366 .VPWR(VPWR),
367 .VGND(VGND),
368 .VPB(VPWR),
369 .VNB(VGND),
370 `endif
371 .X(SEL[7]),
372 .A(A[0]),
373 .B(A[1]),
374 .C(A[2]),
375 .D(EN)
376 ); // 111
377endmodule
378
379
380module DEC6x64 (
381`ifdef USE_POWER_PINS
382 input VPWR,
383 input VGND,
384`endif
385 input EN,
386 input [5:0] A,
387 output [63:0] SEL
388);
389 wire [7:0] SEL0_w ;
390 wire [2:0] A_buf;
391
392 DEC3x8 DEC_L0 (
393 `ifdef USE_POWER_PINS
394 .VPWR(VPWR),
395 .VGND(VGND),
396 `endif
397 .EN(EN),
398 .A(A[5:3]),
399 .SEL(SEL0_w)
400 );
401
402 sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] (
403 `ifdef USE_POWER_PINS
404 .VPWR(VPWR),
405 .VGND(VGND),
406 .VPB(VPWR),
407 .VNB(VGND),
408 `endif
409 .X(A_buf),
410 .A(A[2:0])
411 );
412
413 generate
414 genvar i;
415 for(i=0; i<8; i=i+1) begin : DEC_L1
416 DEC3x8 U (
417 `ifdef USE_POWER_PINS
418 .VPWR(VPWR),
419 .VGND(VGND),
420 `endif
421 .EN(SEL0_w[i]),
422 .A(A_buf),
423 .SEL(SEL[7+8*i: 8*i])
424 );
425 end
426 endgenerate
427endmodule
428
429module MUX2x1_32(
430`ifdef USE_POWER_PINS
431 input VPWR,
432 input VGND,
433`endif
434 input [31:0] A0, A1,
435 input [0:0] S,
436 output [31:0] X
437);
438 sky130_fd_sc_hd__mux2_1 MUX[31:0] (
439 `ifdef USE_POWER_PINS
440 .VPWR(VPWR),
441 .VGND(VGND),
442 .VPB(VPWR),
443 .VNB(VGND),
444 `endif
445 .A0(A0),
446 .A1(A1),
447 .S(S[0]),
448 .X(X)
449 );
450
451endmodule
452
453module MUX4x1_32(
454`ifdef USE_POWER_PINS
455 input VPWR,
456 input VGND,
457`endif
458 input [31:0] A0, A1, A2, A3,
459 input [1:0] S,
460 output [31:0] X
461);
462 sky130_fd_sc_hd__mux4_1 MUX[31:0] (
463 `ifdef USE_POWER_PINS
464 .VPWR(VPWR),
465 .VGND(VGND),
466 .VPB(VPWR),
467 .VNB(VGND),
468 `endif
469 .A0(A0),
470 .A1(A1),
471 .A2(A2),
472 .A3(A3),
473 .S0(S[0]),
474 .S1(S[1]),
475 .X(X)
476 );
477endmodule
478
479module PASS (
480`ifdef USE_POWER_PINS
481 input VPWR,
482 input VGND,
483`endif
484 input [31:0] A,
485 output [31:0] X
486);
487 assign X = A;
488endmodule
489
490module SRAM64x32(
491`ifdef USE_POWER_PINS
492 input VPWR,
493 input VGND,
494`endif
495 input CLK,
496 input [3:0] WE,
497 input EN,
498 input [31:0] Di,
499 output [31:0] Do,
500 input [5:0] A
501);
502
503 wire [63:0] SEL;
504 wire [31:0] Do_pre;
505 wire [31:0] Di_buf;
506 wire CLK_buf;
507 wire [3:0] WE_buf;
508
509 sky130_fd_sc_hd__clkbuf_16 CLKBUF (
510 `ifdef USE_POWER_PINS
511 .VPWR(VPWR),
512 .VGND(VGND),
513 .VPB(VPWR),
514 .VNB(VGND),
515 `endif
516 .X(CLK_buf),
517 .A(CLK)
518 );
519
520 sky130_fd_sc_hd__clkbuf_16 WEBUF[3:0] (
521 `ifdef USE_POWER_PINS
522 .VPWR(VPWR),
523 .VGND(VGND),
524 .VPB(VPWR),
525 .VNB(VGND),
526 `endif
527 .X(WE_buf),
528 .A(WE)
529 );
530
531 sky130_fd_sc_hd__clkbuf_16 DIBUF[31:0] (
532 `ifdef USE_POWER_PINS
533 .VPWR(VPWR),
534 .VGND(VGND),
535 .VPB(VPWR),
536 .VNB(VGND),
537 `endif
538 .X(Di_buf),
539 .A(Di)
540 );
541
542 DEC6x64 DEC (
543 `ifdef USE_POWER_PINS
544 .VPWR(VPWR),
545 .VGND(VGND),
546 `endif
547 .EN(EN),
548 .A(A),
549 .SEL(SEL)
550 );
551
552 generate
553 genvar i;
554 for (i=0; i< 64; i=i+1) begin : WORD
555 WORD32 W (
556 `ifdef USE_POWER_PINS
557 .VPWR(VPWR),
558 .VGND(VGND),
559 `endif
560 .CLK(CLK_buf),
561 .WE(WE_buf),
562 .SEL(SEL[i]),
563 .Di(Di_buf),
564 .Do(Do_pre)
565 );
566 end
567 endgenerate
568
569 // Ensure that the Do_pre lines are not floating when EN = 0
570 wire lo;
571 wire float_buf_en;
572 sky130_fd_sc_hd__clkbuf_4 FBUFENBUF(
573 `ifdef USE_POWER_PINS
574 .VPWR(VPWR),
575 .VGND(VGND),
576 .VPB(VPWR),
577 .VNB(VGND),
578 `endif
579 .X(float_buf_en),
580 .A(EN)
581 );
582
583 sky130_fd_sc_hd__conb_1 TIE (
584 `ifdef USE_POWER_PINS
585 .VPWR(VPWR),
586 .VGND(VGND),
587 .VPB(VPWR),
588 .VNB(VGND),
589 `endif
590 .LO(lo),
591 .HI()
592 );
593
594 sky130_fd_sc_hd__ebufn_4 FLOATBUF[31:0] (
595 `ifdef USE_POWER_PINS
596 .VPWR(VPWR),
597 .VGND(VGND),
598 .VPB(VPWR),
599 .VNB(VGND),
600 `endif
601 .A( lo ),
602 .Z(Do_pre),
603 .TE_B(float_buf_en)
604 );
605
606 generate
607 //genvar i;
608 for(i=0; i<32; i=i+1) begin : OUT
609 sky130_fd_sc_hd__dfxtp_1 FF (
610 `ifdef USE_POWER_PINS
611 .VPWR(VPWR),
612 .VGND(VGND),
613 .VPB(VPWR),
614 .VNB(VGND),
615 `endif
616 .D(Do_pre[i]),
617 .Q(Do[i]),
618 .CLK(CLK)
619 );
620 end
621 endgenerate
622
623endmodule
624
625module DFFRAM_COL4
626(
627`ifdef USE_POWER_PINS
628 VPWR,
629 VGND,
630`endif
631 CLK,
632 WE,
633 EN,
634 Di,
635 Do,
636 A
637);
638
639 input CLK;
640 input [3:0] WE;
641 input EN;
642 input [31:0] Di;
643 output [31:0] Do;
644 input [7:0] A;
645
646`ifdef USE_POWER_PINS
647 input VPWR;
648 input VGND;
649`endif
650
651 wire [31:0] Di_buf;
652 wire [31:0] Do_pre;
653 wire CLK_buf;
654 wire [3:0] WE_buf;
655 wire [5:3] A_buf;
656
657 wire [31:0] Do_B_0_0;
658 wire [31:0] Do_B_0_1;
659 wire [31:0] Do_B_0_2;
660 wire [31:0] Do_B_0_3;
661
662 wire [3:0] row_sel;
663
664 sky130_fd_sc_hd__clkbuf_8 CLKBUF (
665 `ifdef USE_POWER_PINS
666 .VPWR(VPWR),
667 .VGND(VGND),
668 .VPB(VPWR),
669 .VNB(VGND),
670 `endif
671 .X(CLK_buf),
672 .A(CLK)
673 );
674
675 sky130_fd_sc_hd__clkbuf_8 WEBUF[3:0] (
676 `ifdef USE_POWER_PINS
677 .VPWR(VPWR),
678 .VGND(VGND),
679 .VPB(VPWR),
680 .VNB(VGND),
681 `endif
682 .X(WE_buf),
683 .A(WE)
684 );
685
686 sky130_fd_sc_hd__clkbuf_8 DIBUF[31:0] (
687 `ifdef USE_POWER_PINS
688 .VPWR(VPWR),
689 .VGND(VGND),
690 .VPB(VPWR),
691 .VNB(VGND),
692 `endif
693 .X(Di_buf),
694 .A(Di)
695 );
696
697 sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] (
698 `ifdef USE_POWER_PINS
699 .VPWR(VPWR),
700 .VGND(VGND),
701 .VPB(VPWR),
702 .VNB(VGND),
703 `endif
704 .X(A_buf),
705 .A(A[5:3])
706 );
707
708 DEC2x4 DEC (
709 `ifdef USE_POWER_PINS
710 .VPWR(VPWR),
711 .VGND(VGND),
712 `endif
713 .EN(EN),
714 .A(A[7:6]),
715 .SEL(row_sel)
716 );
717
718 SRAM64x32 B_0_0 (
719 `ifdef USE_POWER_PINS
720 .VPWR(VPWR),
721 .VGND(VGND),
722 `endif
723 .CLK(CLK_buf),
724 .WE(WE_buf),
725 .EN(row_sel[0]),
726 .Di(Di_buf),
727 .Do(Do_B_0_0),
728 .A({A_buf,A[2:0]})
729 );
730
731 SRAM64x32 B_0_1 (
732 `ifdef USE_POWER_PINS
733 .VPWR(VPWR),
734 .VGND(VGND),
735 `endif
736 .CLK(CLK_buf),
737 .WE(WE_buf),
738 .EN(row_sel[1]),
739 .Di(Di_buf),
740 .Do(Do_B_0_1),
741 .A({A_buf,A[2:0]})
742 );
743
744 SRAM64x32 B_0_2 (
745 `ifdef USE_POWER_PINS
746 .VPWR(VPWR),
747 .VGND(VGND),
748 `endif
749 .CLK(CLK_buf),
750 .WE(WE_buf),
751 .EN(row_sel[2]),
752 .Di(Di_buf),
753 .Do(Do_B_0_2),
754 .A({A_buf,A[2:0]})
755 );
756
757 SRAM64x32 B_0_3 (
758 `ifdef USE_POWER_PINS
759 .VPWR(VPWR),
760 .VGND(VGND),
761 `endif
762 .CLK(CLK_buf),
763 .WE(WE_buf),
764 .EN(row_sel[3]),
765 .Di(Di_buf),
766 .Do(Do_B_0_3),
767 .A({A_buf,A[2:0]})
768 );
769
770 MUX4x1_32 MUX (
771 `ifdef USE_POWER_PINS
772 .VPWR(VPWR),
773 .VGND(VGND),
774 `endif
775 .A0(Do_B_0_0),
776 .A1(Do_B_0_1),
777 .A2(Do_B_0_2),
778 .A3(Do_B_0_3),
779 .S(A[7:6]),
780 .X(Do)
781 );
782
783endmodule
784