| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,unknown_no_total_runtime_file,-1,0h0m57s,0.19458281444582815,10.2784,0.09729140722291407,-1,535.44,1,0,0,0,0,0,0,0,0,0,-1,-1,602926,1082,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.11,3.04,0.0,0.0,-1,18,636,18,636,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,153.6,153.18,0.35,0.4,sky130_fd_sc_hd,8,0 |
| 0,/project/openlane/user_proj_top,user_proj_top,user_proj_top,Flow_completed,0h6m37s,0h4m10s,35688.88888888888,0.18,17844.44444444444,29,705.85,3212,0,0,0,0,0,0,0,0,0,0,0,88271,24719,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,45404042,0.0,13.26,10.44,0.02,0.0,-1,3022,3284,2902,3164,0,0,0,3212,6,4,9,7,30,0,0,43,73,71,5,314,2146,0,2460,125.0,8.0,8,AREA 0,5,50,1,153.6,153.18,0.82,0,sky130_fd_sc_hd,0,4 |
