verilog/dv/wb_utests/uart_wb/Makefile

.SUFFIXES:

PATTERN = uart_wb

all:  ${PATTERN:=.vcd}

%.vvp: %_tb.v
	iverilog -I .. -I ../../ -I ../../../rtl \
	$< -o $@

%.vcd: %.vvp
	vvp $<

clean:
	rm -f *.vvp *.vcd *.log

.PHONY: clean all