| |
| /----------------------------------------------------------------------------\ |
| | | |
| | yosys -- Yosys Open SYnthesis Suite | |
| | | |
| | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> | |
| | | |
| | Permission to use, copy, modify, and/or distribute this software for any | |
| | purpose with or without fee is hereby granted, provided that the above | |
| | copyright notice and this permission notice appear in all copies. | |
| | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| | | |
| \----------------------------------------------------------------------------/ |
| |
| Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) |
| |
| [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. |
| |
| 1. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/defines.v |
| Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/defines.v' to AST representation. |
| Successfully finished Verilog frontend. |
| |
| 2. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/DFFRAM.v |
| Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/DFFRAM.v' to AST representation. |
| Generating RTLIL representation for module `\DFFRAM'. |
| Successfully finished Verilog frontend. |
| |
| 3. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/digital_pll.v |
| Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/digital_pll.v' to AST representation. |
| Generating RTLIL representation for module `\digital_pll_controller'. |
| Generating RTLIL representation for module `\delay_stage'. |
| Generating RTLIL representation for module `\start_stage'. |
| Generating RTLIL representation for module `\ring_osc2x13'. |
| Generating RTLIL representation for module `\digital_pll'. |
| Successfully finished Verilog frontend. |
| |
| 4. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/defines.v |
| Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/defines.v' to AST representation. |
| Successfully finished Verilog frontend. |
| |
| 5. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v |
| Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v' to AST representation. |
| Generating RTLIL representation for module `\storage_bridge_wb'. |
| Successfully finished Verilog frontend. |
| |
| 6. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/clock_div.v |
| Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v' to AST representation. |
| Generating RTLIL representation for module `\clock_div'. |
| Generating RTLIL representation for module `\odd'. |
| Generating RTLIL representation for module `\even'. |
| Successfully finished Verilog frontend. |
| |
| 7. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v |
| Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v' to AST representation. |
| Generating RTLIL representation for module `\caravel_clocking'. |
| /project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:51: Warning: Identifier `\pll_clk_divided' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:62: Warning: Identifier `\pll_clk90_divided' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:70: Warning: Identifier `\core_ext_clk' is implicitly declared. |
| Successfully finished Verilog frontend. |
| |
| 8. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v |
| Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v' to AST representation. |
| Generating RTLIL representation for module `\mgmt_core'. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:105: Warning: Identifier `\sdo_oenb_state' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:106: Warning: Identifier `\jtag_oenb_state' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:159: Warning: Identifier `\trap' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:167: Warning: Identifier `\irq_spi' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:175: Warning: Identifier `\flash_io2_oeb' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:176: Warning: Identifier `\flash_io3_oeb' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:181: Warning: Identifier `\flash_io2_ieb' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:182: Warning: Identifier `\flash_io3_ieb' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:185: Warning: Identifier `\flash_io2_do' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:186: Warning: Identifier `\flash_io3_do' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:189: Warning: Identifier `\flash_io2_di' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:190: Warning: Identifier `\flash_io3_di' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:192: Warning: Identifier `\pass_thru_reset' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:193: Warning: Identifier `\pass_thru_mgmt_csb' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:194: Warning: Identifier `\pass_thru_mgmt_sck' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:195: Warning: Identifier `\pass_thru_mgmt_sdi' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:196: Warning: Identifier `\pass_thru_mgmt_sdo' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:248: Warning: Identifier `\spi_pll_ena' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v:252: Warning: Identifier `\spi_pll_dco_ena' is implicitly declared. |
| Successfully finished Verilog frontend. |
| |
| 9. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v |
| Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v' to AST representation. |
| Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:190) |
| Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:191) |
| Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:196) |
| Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160) |
| Generating RTLIL representation for module `\picorv32'. |
| Generating RTLIL representation for module `\picorv32_regs'. |
| Generating RTLIL representation for module `\picorv32_pcpi_mul'. |
| Generating RTLIL representation for module `\picorv32_pcpi_fast_mul'. |
| Generating RTLIL representation for module `\picorv32_pcpi_div'. |
| Generating RTLIL representation for module `\picorv32_axi'. |
| Generating RTLIL representation for module `\picorv32_axi_adapter'. |
| Generating RTLIL representation for module `\picorv32_wb'. |
| Generating RTLIL representation for module `\spimemio_wb'. |
| Generating RTLIL representation for module `\spimemio'. |
| Generating RTLIL representation for module `\spimemio_xfer'. |
| Generating RTLIL representation for module `\simpleuart_wb'. |
| /project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:65: Warning: Identifier `\reg_dat_wait' is implicitly declared. |
| Generating RTLIL representation for module `\simpleuart'. |
| /project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:129: Warning: Identifier `\reg_ena_do' is implicitly declared. |
| Generating RTLIL representation for module `\simple_spi_master_wb'. |
| /project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:111: Warning: Identifier `\reg_dat_wait' is implicitly declared. |
| Generating RTLIL representation for module `\simple_spi_master'. |
| Generating RTLIL representation for module `\counter_timer_high_wb'. |
| Generating RTLIL representation for module `\counter_timer_high'. |
| Generating RTLIL representation for module `\counter_timer_low_wb'. |
| Generating RTLIL representation for module `\counter_timer_low'. |
| /project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:171: Warning: Identifier `\loc_enable' is implicitly declared. |
| Generating RTLIL representation for module `\wb_intercon'. |
| Generating RTLIL representation for module `\mem_wb'. |
| Generating RTLIL representation for module `\soc_mem'. |
| Generating RTLIL representation for module `\gpio_wb'. |
| Generating RTLIL representation for module `\gpio'. |
| Generating RTLIL representation for module `\sysctrl_wb'. |
| Generating RTLIL representation for module `\sysctrl'. |
| /project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:113: Warning: Identifier `\pwrgood_sel' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:114: Warning: Identifier `\clk_out_sel' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:115: Warning: Identifier `\trap_out_sel' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:116: Warning: Identifier `\irq_sel' is implicitly declared. |
| Generating RTLIL representation for module `\la_wb'. |
| Generating RTLIL representation for module `\la'. |
| Generating RTLIL representation for module `\mprj_ctrl_wb'. |
| Generating RTLIL representation for module `\mprj_ctrl'. |
| Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:268 |
| /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:166: Warning: Identifier `\selected' is implicitly declared. |
| Generating RTLIL representation for module `\convert_gpio_sigs'. |
| Generating RTLIL representation for module `\mgmt_soc'. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:347: Warning: Identifier `\wb_clk_i' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:348: Warning: Identifier `\wb_rst_i' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:375: Warning: Identifier `\mem_instr' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:477: Warning: Identifier `\ser_tx' is implicitly declared. |
| Generating RTLIL representation for module `\mgmt_soc_regs'. |
| Successfully finished Verilog frontend. |
| |
| 10. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v |
| Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v' to AST representation. |
| Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:128) |
| Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:129) |
| Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:130) |
| Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:132) |
| Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:133) |
| Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:134) |
| Generating RTLIL representation for module `\housekeeping_spi'. |
| Generating RTLIL representation for module `\housekeeping_spi_slave'. |
| Successfully finished Verilog frontend. |
| |
| 11. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 11.1. Analyzing design hierarchy.. |
| Top module: \mgmt_core |
| Used module: \housekeeping_spi |
| Used module: \housekeeping_spi_slave |
| Used module: \mgmt_soc |
| Used module: \wb_intercon |
| Used module: \storage_bridge_wb |
| Used module: \mem_wb |
| Used module: \soc_mem |
| Used module: \mprj_ctrl_wb |
| Used module: \mprj_ctrl |
| Used module: \la_wb |
| Used module: \la |
| Used module: \sysctrl_wb |
| Used module: \sysctrl |
| Used module: \gpio_wb |
| Used module: \gpio |
| Used module: \counter_timer_high_wb |
| Used module: \counter_timer_high |
| Used module: \counter_timer_low_wb |
| Used module: \counter_timer_low |
| Used module: \simple_spi_master_wb |
| Used module: \simple_spi_master |
| Used module: \simpleuart_wb |
| Used module: \simpleuart |
| Used module: \spimemio_wb |
| Used module: \spimemio |
| Used module: \spimemio_xfer |
| Used module: \picorv32_wb |
| Used module: \picorv32 |
| Used module: \mgmt_soc_regs |
| Used module: \convert_gpio_sigs |
| Used module: \caravel_clocking |
| Used module: \clock_div |
| Used module: \odd |
| Used module: \even |
| Parameter \SIZE = 3 |
| |
| 11.2. Executing AST frontend in derive mode using pre-parsed AST for module `\clock_div'. |
| Parameter \SIZE = 3 |
| Generating RTLIL representation for module `$paramod\clock_div\SIZE=3'. |
| Parameter \SIZE = 3 |
| Found cached RTLIL representation for module `$paramod\clock_div\SIZE=3'. |
| Parameter \DW = 32 |
| Parameter \AW = 32 |
| Parameter \NS = 14 |
| Parameter \ADR_MASK = 448'1111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000 |
| Parameter \SLAVE_ADR = 448'0010111100000000000000000000000000101101000000000000000000000000001100000000000000000000000000000010011000000000000000000000000000100101000000000000000000000000001001000000000000000000000000000010001100000000000000000000000000100010000000000000000000000000001000010000000000000000000000000010000000000000000000000000000000010000000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000000000000000000000000000 |
| |
| 11.3. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_intercon'. |
| Parameter \DW = 32 |
| Parameter \AW = 32 |
| Parameter \NS = 14 |
| Parameter \ADR_MASK = 448'1111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000 |
| Parameter \SLAVE_ADR = 448'0010111100000000000000000000000000101101000000000000000000000000001100000000000000000000000000000010011000000000000000000000000000100101000000000000000000000000001001000000000000000000000000000010001100000000000000000000000000100010000000000000000000000000001000010000000000000000000000000010000000000000000000000000000000010000000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000000000000000000000000000 |
| Generating RTLIL representation for module `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon'. |
| Parameter \USER_BLOCKS = 6 |
| Parameter \MGMT_BLOCKS = 2 |
| Parameter \MGMT_BASE_ADR = 16777216 |
| Parameter \USER_BASE_ADR = 33554432 |
| Parameter \MGMT_BLOCKS_ADR = 48'000100000000000000000000000000000000000000000000 |
| Parameter \USER_BLOCKS_ADR = 144'010100000000000000000000010000000000000000000000001100000000000000000000001000000000000000000000000100000000000000000000000000000000000000000000 |
| |
| 11.4. Executing AST frontend in derive mode using pre-parsed AST for module `\storage_bridge_wb'. |
| Parameter \USER_BLOCKS = 6 |
| Parameter \MGMT_BLOCKS = 2 |
| Parameter \MGMT_BASE_ADR = 16777216 |
| Parameter \USER_BASE_ADR = 33554432 |
| Parameter \MGMT_BLOCKS_ADR = 48'000100000000000000000000000000000000000000000000 |
| Parameter \USER_BLOCKS_ADR = 144'010100000000000000000000010000000000000000000000001100000000000000000000001000000000000000000000000100000000000000000000000000000000000000000000 |
| Generating RTLIL representation for module `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb'. |
| Parameter \BASE_ADR = 637534208 |
| |
| 11.5. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl_wb'. |
| Parameter \BASE_ADR = 637534208 |
| Generating RTLIL representation for module `$paramod\mprj_ctrl_wb\BASE_ADR=637534208'. |
| Parameter \BASE_ADR = 620756992 |
| Parameter \LA_DATA_0 = 8'00000000 |
| Parameter \LA_DATA_1 = 8'00000100 |
| Parameter \LA_DATA_3 = 8'00001100 |
| Parameter \LA_ENA_0 = 8'00010000 |
| Parameter \LA_ENA_1 = 8'00010100 |
| Parameter \LA_ENA_2 = 8'00011000 |
| Parameter \LA_ENA_3 = 8'00011100 |
| |
| 11.6. Executing AST frontend in derive mode using pre-parsed AST for module `\la_wb'. |
| Parameter \BASE_ADR = 620756992 |
| Parameter \LA_DATA_0 = 8'00000000 |
| Parameter \LA_DATA_1 = 8'00000100 |
| Parameter \LA_DATA_3 = 8'00001100 |
| Parameter \LA_ENA_0 = 8'00010000 |
| Parameter \LA_ENA_1 = 8'00010100 |
| Parameter \LA_ENA_2 = 8'00011000 |
| Parameter \LA_ENA_3 = 8'00011100 |
| Generating RTLIL representation for module `$paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb'. |
| Parameter \BASE_ADR = 788529152 |
| Parameter \PWRGOOD = 8'00000000 |
| Parameter \CLK_OUT = 8'00000100 |
| Parameter \TRAP_OUT = 8'00001000 |
| Parameter \IRQ_SRC = 8'00001100 |
| |
| 11.7. Executing AST frontend in derive mode using pre-parsed AST for module `\sysctrl_wb'. |
| Parameter \BASE_ADR = 788529152 |
| Parameter \PWRGOOD = 8'00000000 |
| Parameter \CLK_OUT = 8'00000100 |
| Parameter \TRAP_OUT = 8'00001000 |
| Parameter \IRQ_SRC = 8'00001100 |
| Generating RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb'. |
| Parameter \BASE_ADR = 553648128 |
| Parameter \GPIO_DATA = 8'00000000 |
| Parameter \GPIO_ENA = 8'00000100 |
| Parameter \GPIO_PU = 8'00001000 |
| Parameter \GPIO_PD = 8'00001100 |
| |
| 11.8. Executing AST frontend in derive mode using pre-parsed AST for module `\gpio_wb'. |
| Parameter \BASE_ADR = 553648128 |
| Parameter \GPIO_DATA = 8'00000000 |
| Parameter \GPIO_ENA = 8'00000100 |
| Parameter \GPIO_PU = 8'00001000 |
| Parameter \GPIO_PD = 8'00001100 |
| Generating RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb'. |
| Parameter \BASE_ADR = 587202560 |
| Parameter \CONFIG = 8'00000000 |
| Parameter \VALUE = 8'00000100 |
| Parameter \DATA = 8'00001000 |
| |
| 11.9. Executing AST frontend in derive mode using pre-parsed AST for module `\counter_timer_high_wb'. |
| Parameter \BASE_ADR = 587202560 |
| Parameter \CONFIG = 8'00000000 |
| Parameter \VALUE = 8'00000100 |
| Parameter \DATA = 8'00001000 |
| Generating RTLIL representation for module `$paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb'. |
| Parameter \BASE_ADR = 570425344 |
| Parameter \CONFIG = 8'00000000 |
| Parameter \VALUE = 8'00000100 |
| Parameter \DATA = 8'00001000 |
| |
| 11.10. Executing AST frontend in derive mode using pre-parsed AST for module `\counter_timer_low_wb'. |
| Parameter \BASE_ADR = 570425344 |
| Parameter \CONFIG = 8'00000000 |
| Parameter \VALUE = 8'00000100 |
| Parameter \DATA = 8'00001000 |
| Generating RTLIL representation for module `$paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb'. |
| Parameter \BASE_ADR = 603979776 |
| Parameter \CONFIG = 8'00000000 |
| Parameter \DATA = 8'00000100 |
| |
| 11.11. Executing AST frontend in derive mode using pre-parsed AST for module `\simple_spi_master_wb'. |
| Parameter \BASE_ADR = 603979776 |
| Parameter \CONFIG = 8'00000000 |
| Parameter \DATA = 8'00000100 |
| Generating RTLIL representation for module `$paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100'. |
| /project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:111: Warning: Identifier `\reg_dat_wait' is implicitly declared. |
| Parameter \BASE_ADR = 536870912 |
| Parameter \CLK_DIV = 8'00000000 |
| Parameter \DATA = 8'00000100 |
| |
| 11.12. Executing AST frontend in derive mode using pre-parsed AST for module `\simpleuart_wb'. |
| Parameter \BASE_ADR = 536870912 |
| Parameter \CLK_DIV = 8'00000000 |
| Parameter \DATA = 8'00000100 |
| Generating RTLIL representation for module `$paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100'. |
| /project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:65: Warning: Identifier `\reg_dat_wait' is implicitly declared. |
| Parameter \BARREL_SHIFTER = 1 |
| Parameter \COMPRESSED_ISA = 1 |
| Parameter \ENABLE_MUL = 1 |
| Parameter \ENABLE_DIV = 1 |
| Parameter \ENABLE_IRQ = 1 |
| Parameter \ENABLE_IRQ_QREGS = 0 |
| Parameter \PROGADDR_RESET = 268435456 |
| Parameter \PROGADDR_IRQ = 0 |
| Parameter \STACKADDR = 1024 |
| |
| 11.13. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32_wb'. |
| Parameter \BARREL_SHIFTER = 1 |
| Parameter \COMPRESSED_ISA = 1 |
| Parameter \ENABLE_MUL = 1 |
| Parameter \ENABLE_DIV = 1 |
| Parameter \ENABLE_IRQ = 1 |
| Parameter \ENABLE_IRQ_QREGS = 0 |
| Parameter \PROGADDR_RESET = 268435456 |
| Parameter \PROGADDR_IRQ = 0 |
| Parameter \STACKADDR = 1024 |
| Generating RTLIL representation for module `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb'. |
| Parameter \ENABLE_COUNTERS = 1'1 |
| Parameter \ENABLE_COUNTERS64 = 1'1 |
| Parameter \ENABLE_REGS_16_31 = 1'1 |
| Parameter \ENABLE_REGS_DUALPORT = 1'1 |
| Parameter \TWO_STAGE_SHIFT = 1'1 |
| Parameter \BARREL_SHIFTER = 1'0 |
| Parameter \TWO_CYCLE_COMPARE = 1'0 |
| Parameter \TWO_CYCLE_ALU = 1'0 |
| Parameter \COMPRESSED_ISA = 1'0 |
| Parameter \CATCH_MISALIGN = 1'1 |
| Parameter \CATCH_ILLINSN = 1'1 |
| Parameter \ENABLE_PCPI = 1'0 |
| Parameter \ENABLE_MUL = 1'0 |
| Parameter \ENABLE_FAST_MUL = 1'0 |
| Parameter \ENABLE_DIV = 1'0 |
| Parameter \ENABLE_IRQ = 1'0 |
| Parameter \ENABLE_IRQ_QREGS = 1'1 |
| Parameter \ENABLE_IRQ_TIMER = 1'1 |
| Parameter \ENABLE_TRACE = 1'0 |
| Parameter \REGS_INIT_ZERO = 1'0 |
| Parameter \MASKED_IRQ = 0 |
| Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111 |
| Parameter \PROGADDR_RESET = 0 |
| Parameter \PROGADDR_IRQ = 16 |
| Parameter \STACKADDR = 32'11111111111111111111111111111111 |
| |
| 11.14. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'. |
| Parameter \ENABLE_COUNTERS = 1'1 |
| Parameter \ENABLE_COUNTERS64 = 1'1 |
| Parameter \ENABLE_REGS_16_31 = 1'1 |
| Parameter \ENABLE_REGS_DUALPORT = 1'1 |
| Parameter \TWO_STAGE_SHIFT = 1'1 |
| Parameter \BARREL_SHIFTER = 1'0 |
| Parameter \TWO_CYCLE_COMPARE = 1'0 |
| Parameter \TWO_CYCLE_ALU = 1'0 |
| Parameter \COMPRESSED_ISA = 1'0 |
| Parameter \CATCH_MISALIGN = 1'1 |
| Parameter \CATCH_ILLINSN = 1'1 |
| Parameter \ENABLE_PCPI = 1'0 |
| Parameter \ENABLE_MUL = 1'0 |
| Parameter \ENABLE_FAST_MUL = 1'0 |
| Parameter \ENABLE_DIV = 1'0 |
| Parameter \ENABLE_IRQ = 1'0 |
| Parameter \ENABLE_IRQ_QREGS = 1'1 |
| Parameter \ENABLE_IRQ_TIMER = 1'1 |
| Parameter \ENABLE_TRACE = 1'0 |
| Parameter \REGS_INIT_ZERO = 1'0 |
| Parameter \MASKED_IRQ = 0 |
| Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111 |
| Parameter \PROGADDR_RESET = 0 |
| Parameter \PROGADDR_IRQ = 16 |
| Parameter \STACKADDR = 32'11111111111111111111111111111111 |
| Generating RTLIL representation for module `$paramod$4d2dfdcc1db1a7362453fb449ccdda75bb1b39f9\picorv32'. |
| Parameter \WORDS = 256 |
| Parameter \ADR_WIDTH = 8 |
| |
| 11.15. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_mem'. |
| Parameter \WORDS = 256 |
| Parameter \ADR_WIDTH = 8 |
| Generating RTLIL representation for module `$paramod\soc_mem\WORDS=256\ADR_WIDTH=8'. |
| Parameter \BASE_ADR = 553648128 |
| Parameter \GPIO_DATA = 8'00000000 |
| Parameter \GPIO_ENA = 8'00000100 |
| Parameter \GPIO_PU = 8'00001000 |
| Parameter \GPIO_PD = 8'00001100 |
| |
| 11.16. Executing AST frontend in derive mode using pre-parsed AST for module `\gpio'. |
| Parameter \BASE_ADR = 553648128 |
| Parameter \GPIO_DATA = 8'00000000 |
| Parameter \GPIO_ENA = 8'00000100 |
| Parameter \GPIO_PU = 8'00001000 |
| Parameter \GPIO_PD = 8'00001100 |
| Generating RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio'. |
| Parameter \BASE_ADR = 788529152 |
| Parameter \PWRGOOD = 8'00000000 |
| Parameter \CLK_OUT = 8'00000100 |
| Parameter \TRAP_OUT = 8'00001000 |
| Parameter \IRQ_SRC = 8'00001100 |
| |
| 11.17. Executing AST frontend in derive mode using pre-parsed AST for module `\sysctrl'. |
| Parameter \BASE_ADR = 788529152 |
| Parameter \PWRGOOD = 8'00000000 |
| Parameter \CLK_OUT = 8'00000100 |
| Parameter \TRAP_OUT = 8'00001000 |
| Parameter \IRQ_SRC = 8'00001100 |
| Generating RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl'. |
| /project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:113: Warning: Identifier `\pwrgood_sel' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:114: Warning: Identifier `\clk_out_sel' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:115: Warning: Identifier `\trap_out_sel' is implicitly declared. |
| /project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:116: Warning: Identifier `\irq_sel' is implicitly declared. |
| Parameter \BASE_ADR = 570425344 |
| Parameter \LA_DATA_0 = 8'00000000 |
| Parameter \LA_DATA_1 = 8'00000100 |
| Parameter \LA_DATA_2 = 8'00001000 |
| Parameter \LA_DATA_3 = 8'00001100 |
| Parameter \LA_ENA_0 = 8'00010000 |
| Parameter \LA_ENA_1 = 8'00010100 |
| Parameter \LA_ENA_2 = 8'00011000 |
| Parameter \LA_ENA_3 = 8'00011100 |
| |
| 11.18. Executing AST frontend in derive mode using pre-parsed AST for module `\la'. |
| Parameter \BASE_ADR = 570425344 |
| Parameter \LA_DATA_0 = 8'00000000 |
| Parameter \LA_DATA_1 = 8'00000100 |
| Parameter \LA_DATA_2 = 8'00001000 |
| Parameter \LA_DATA_3 = 8'00001100 |
| Parameter \LA_ENA_0 = 8'00010000 |
| Parameter \LA_ENA_1 = 8'00010100 |
| Parameter \LA_ENA_2 = 8'00011000 |
| Parameter \LA_ENA_3 = 8'00011100 |
| Generating RTLIL representation for module `$paramod$499b0a1c054fbe1b70d6dc28b15376e5cd987bff\la'. |
| Parameter \BASE_ADR = 587202560 |
| Parameter \XFER = 8'00000000 |
| Parameter \PWRDATA = 8'00000100 |
| Parameter \IODATA = 8'00001000 |
| Parameter \IOCONFIG = 8'00100000 |
| |
| 11.19. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl'. |
| Parameter \BASE_ADR = 587202560 |
| Parameter \XFER = 8'00000000 |
| Parameter \PWRDATA = 8'00000100 |
| Parameter \IODATA = 8'00001000 |
| Parameter \IOCONFIG = 8'00100000 |
| Generating RTLIL representation for module `$paramod$ed88d8bd975b89882ecfbd510fe3c5e6ac127a6b\mprj_ctrl'. |
| Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:268 |
| /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:166: Warning: Identifier `\selected' is implicitly declared. |
| |
| 11.20. Analyzing design hierarchy.. |
| Top module: \mgmt_core |
| Used module: \housekeeping_spi |
| Used module: \housekeeping_spi_slave |
| Used module: \mgmt_soc |
| Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon |
| Used module: $paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb |
| Used module: \mem_wb |
| Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8 |
| Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208 |
| Used module: \mprj_ctrl |
| Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb |
| Used module: \la |
| Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb |
| Used module: \sysctrl |
| Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb |
| Used module: \gpio |
| Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb |
| Used module: \counter_timer_high |
| Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb |
| Used module: \counter_timer_low |
| Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100 |
| Used module: \simple_spi_master |
| Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100 |
| Used module: \simpleuart |
| Used module: \spimemio_wb |
| Used module: \spimemio |
| Used module: \spimemio_xfer |
| Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb |
| Used module: \picorv32 |
| Used module: \mgmt_soc_regs |
| Used module: \convert_gpio_sigs |
| Used module: \caravel_clocking |
| Used module: $paramod\clock_div\SIZE=3 |
| Used module: \odd |
| Used module: \even |
| Parameter \BASE_ADR = 637534208 |
| Parameter \XFER = 8'00000000 |
| Parameter \PWRDATA = 8'00000100 |
| Parameter \IODATA = 8'00001000 |
| Parameter \IOCONFIG = 8'00100000 |
| |
| 11.21. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl'. |
| Parameter \BASE_ADR = 637534208 |
| Parameter \XFER = 8'00000000 |
| Parameter \PWRDATA = 8'00000100 |
| Parameter \IODATA = 8'00001000 |
| Parameter \IOCONFIG = 8'00100000 |
| Generating RTLIL representation for module `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl'. |
| Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:268 |
| /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:166: Warning: Identifier `\selected' is implicitly declared. |
| Parameter \BASE_ADR = 620756992 |
| Parameter \LA_DATA_0 = 8'00000000 |
| Parameter \LA_DATA_1 = 8'00000100 |
| Parameter \LA_DATA_2 = 8'00001000 |
| Parameter \LA_DATA_3 = 8'00001100 |
| Parameter \LA_ENA_0 = 8'00010000 |
| Parameter \LA_ENA_1 = 8'00010100 |
| Parameter \LA_ENA_2 = 8'00011000 |
| Parameter \LA_ENA_3 = 8'00011100 |
| |
| 11.22. Executing AST frontend in derive mode using pre-parsed AST for module `\la'. |
| Parameter \BASE_ADR = 620756992 |
| Parameter \LA_DATA_0 = 8'00000000 |
| Parameter \LA_DATA_1 = 8'00000100 |
| Parameter \LA_DATA_2 = 8'00001000 |
| Parameter \LA_DATA_3 = 8'00001100 |
| Parameter \LA_ENA_0 = 8'00010000 |
| Parameter \LA_ENA_1 = 8'00010100 |
| Parameter \LA_ENA_2 = 8'00011000 |
| Parameter \LA_ENA_3 = 8'00011100 |
| Generating RTLIL representation for module `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la'. |
| Parameter \BASE_ADR = 788529152 |
| Parameter \PWRGOOD = 8'00000000 |
| Parameter \CLK_OUT = 8'00000100 |
| Parameter \TRAP_OUT = 8'00001000 |
| Parameter \IRQ_SRC = 8'00001100 |
| Found cached RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl'. |
| Parameter \BASE_ADR = 553648128 |
| Parameter \GPIO_DATA = 8'00000000 |
| Parameter \GPIO_ENA = 8'00000100 |
| Parameter \GPIO_PU = 8'00001000 |
| Parameter \GPIO_PD = 8'00001100 |
| Found cached RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio'. |
| Parameter \ENABLE_COUNTERS = 1'1 |
| Parameter \ENABLE_COUNTERS64 = 1'1 |
| Parameter \ENABLE_REGS_16_31 = 1'1 |
| Parameter \ENABLE_REGS_DUALPORT = 1'1 |
| Parameter \TWO_STAGE_SHIFT = 1'1 |
| Parameter \BARREL_SHIFTER = 1'1 |
| Parameter \TWO_CYCLE_COMPARE = 1'0 |
| Parameter \TWO_CYCLE_ALU = 1'0 |
| Parameter \COMPRESSED_ISA = 1'1 |
| Parameter \CATCH_MISALIGN = 1'1 |
| Parameter \CATCH_ILLINSN = 1'1 |
| Parameter \ENABLE_PCPI = 1'0 |
| Parameter \ENABLE_MUL = 1'1 |
| Parameter \ENABLE_FAST_MUL = 1'0 |
| Parameter \ENABLE_DIV = 1'1 |
| Parameter \ENABLE_IRQ = 1'1 |
| Parameter \ENABLE_IRQ_QREGS = 1'0 |
| Parameter \ENABLE_IRQ_TIMER = 1'1 |
| Parameter \ENABLE_TRACE = 1'0 |
| Parameter \REGS_INIT_ZERO = 1'0 |
| Parameter \MASKED_IRQ = 0 |
| Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111 |
| Parameter \PROGADDR_RESET = 268435456 |
| Parameter \PROGADDR_IRQ = 0 |
| Parameter \STACKADDR = 1024 |
| |
| 11.23. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'. |
| Parameter \ENABLE_COUNTERS = 1'1 |
| Parameter \ENABLE_COUNTERS64 = 1'1 |
| Parameter \ENABLE_REGS_16_31 = 1'1 |
| Parameter \ENABLE_REGS_DUALPORT = 1'1 |
| Parameter \TWO_STAGE_SHIFT = 1'1 |
| Parameter \BARREL_SHIFTER = 1'1 |
| Parameter \TWO_CYCLE_COMPARE = 1'0 |
| Parameter \TWO_CYCLE_ALU = 1'0 |
| Parameter \COMPRESSED_ISA = 1'1 |
| Parameter \CATCH_MISALIGN = 1'1 |
| Parameter \CATCH_ILLINSN = 1'1 |
| Parameter \ENABLE_PCPI = 1'0 |
| Parameter \ENABLE_MUL = 1'1 |
| Parameter \ENABLE_FAST_MUL = 1'0 |
| Parameter \ENABLE_DIV = 1'1 |
| Parameter \ENABLE_IRQ = 1'1 |
| Parameter \ENABLE_IRQ_QREGS = 1'0 |
| Parameter \ENABLE_IRQ_TIMER = 1'1 |
| Parameter \ENABLE_TRACE = 1'0 |
| Parameter \REGS_INIT_ZERO = 1'0 |
| Parameter \MASKED_IRQ = 0 |
| Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111 |
| Parameter \PROGADDR_RESET = 268435456 |
| Parameter \PROGADDR_IRQ = 0 |
| Parameter \STACKADDR = 1024 |
| Generating RTLIL representation for module `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32'. |
| |
| 11.24. Analyzing design hierarchy.. |
| Top module: \mgmt_core |
| Used module: \housekeeping_spi |
| Used module: \housekeeping_spi_slave |
| Used module: \mgmt_soc |
| Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon |
| Used module: $paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb |
| Used module: \mem_wb |
| Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8 |
| Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208 |
| Used module: $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl |
| Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb |
| Used module: $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la |
| Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb |
| Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl |
| Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb |
| Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio |
| Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb |
| Used module: \counter_timer_high |
| Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb |
| Used module: \counter_timer_low |
| Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100 |
| Used module: \simple_spi_master |
| Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100 |
| Used module: \simpleuart |
| Used module: \spimemio_wb |
| Used module: \spimemio |
| Used module: \spimemio_xfer |
| Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb |
| Used module: $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32 |
| Used module: \picorv32_pcpi_div |
| Used module: \picorv32_pcpi_mul |
| Used module: \mgmt_soc_regs |
| Used module: \convert_gpio_sigs |
| Used module: \caravel_clocking |
| Used module: $paramod\clock_div\SIZE=3 |
| Used module: \odd |
| Used module: \even |
| |
| 11.25. Analyzing design hierarchy.. |
| Top module: \mgmt_core |
| Used module: \housekeeping_spi |
| Used module: \housekeeping_spi_slave |
| Used module: \mgmt_soc |
| Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon |
| Used module: $paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb |
| Used module: \mem_wb |
| Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8 |
| Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208 |
| Used module: $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl |
| Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb |
| Used module: $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la |
| Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb |
| Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl |
| Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb |
| Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio |
| Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb |
| Used module: \counter_timer_high |
| Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb |
| Used module: \counter_timer_low |
| Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100 |
| Used module: \simple_spi_master |
| Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100 |
| Used module: \simpleuart |
| Used module: \spimemio_wb |
| Used module: \spimemio |
| Used module: \spimemio_xfer |
| Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb |
| Used module: $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32 |
| Used module: \picorv32_pcpi_div |
| Used module: \picorv32_pcpi_mul |
| Used module: \mgmt_soc_regs |
| Used module: \convert_gpio_sigs |
| Used module: \caravel_clocking |
| Used module: $paramod\clock_div\SIZE=3 |
| Used module: \odd |
| Used module: \even |
| Removing unused module `$paramod$ed88d8bd975b89882ecfbd510fe3c5e6ac127a6b\mprj_ctrl'. |
| Removing unused module `$paramod$499b0a1c054fbe1b70d6dc28b15376e5cd987bff\la'. |
| Removing unused module `$paramod$4d2dfdcc1db1a7362453fb449ccdda75bb1b39f9\picorv32'. |
| Removing unused module `\mprj_ctrl'. |
| Removing unused module `\mprj_ctrl_wb'. |
| Removing unused module `\la'. |
| Removing unused module `\la_wb'. |
| Removing unused module `\sysctrl'. |
| Removing unused module `\sysctrl_wb'. |
| Removing unused module `\gpio'. |
| Removing unused module `\gpio_wb'. |
| Removing unused module `\soc_mem'. |
| Removing unused module `\wb_intercon'. |
| Removing unused module `\counter_timer_low_wb'. |
| Removing unused module `\counter_timer_high_wb'. |
| Removing unused module `\simple_spi_master_wb'. |
| Removing unused module `\simpleuart_wb'. |
| Removing unused module `\picorv32_wb'. |
| Removing unused module `\picorv32_axi_adapter'. |
| Removing unused module `\picorv32_axi'. |
| Removing unused module `\picorv32_pcpi_fast_mul'. |
| Removing unused module `\picorv32_regs'. |
| Removing unused module `\picorv32'. |
| Removing unused module `\clock_div'. |
| Removing unused module `\storage_bridge_wb'. |
| Removed 25 unused modules. |
| Mapping positional arguments of cell $paramod\clock_div\SIZE=3.odd_0 (odd). |
| Mapping positional arguments of cell $paramod\clock_div\SIZE=3.even_0 (even). |
| |
| 12. Executing SYNTH pass. |
| |
| 12.1. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 12.1.1. Analyzing design hierarchy.. |
| Top module: \mgmt_core |
| Used module: \housekeeping_spi |
| Used module: \housekeeping_spi_slave |
| Used module: \mgmt_soc |
| Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon |
| Used module: $paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb |
| Used module: \mem_wb |
| Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8 |
| Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208 |
| Used module: $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl |
| Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb |
| Used module: $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la |
| Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb |
| Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl |
| Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb |
| Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio |
| Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb |
| Used module: \counter_timer_high |
| Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb |
| Used module: \counter_timer_low |
| Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100 |
| Used module: \simple_spi_master |
| Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100 |
| Used module: \simpleuart |
| Used module: \spimemio_wb |
| Used module: \spimemio |
| Used module: \spimemio_xfer |
| Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb |
| Used module: $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32 |
| Used module: \picorv32_pcpi_div |
| Used module: \picorv32_pcpi_mul |
| Used module: \mgmt_soc_regs |
| Used module: \convert_gpio_sigs |
| Used module: \caravel_clocking |
| Used module: $paramod\clock_div\SIZE=3 |
| Used module: \odd |
| Used module: \even |
| |
| 12.1.2. Analyzing design hierarchy.. |
| Top module: \mgmt_core |
| Used module: \housekeeping_spi |
| Used module: \housekeeping_spi_slave |
| Used module: \mgmt_soc |
| Used module: $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon |
| Used module: $paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb |
| Used module: \mem_wb |
| Used module: $paramod\soc_mem\WORDS=256\ADR_WIDTH=8 |
| Used module: $paramod\mprj_ctrl_wb\BASE_ADR=637534208 |
| Used module: $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl |
| Used module: $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb |
| Used module: $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la |
| Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb |
| Used module: $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl |
| Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb |
| Used module: $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio |
| Used module: $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb |
| Used module: \counter_timer_high |
| Used module: $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb |
| Used module: \counter_timer_low |
| Used module: $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100 |
| Used module: \simple_spi_master |
| Used module: $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100 |
| Used module: \simpleuart |
| Used module: \spimemio_wb |
| Used module: \spimemio |
| Used module: \spimemio_xfer |
| Used module: $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb |
| Used module: $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32 |
| Used module: \picorv32_pcpi_div |
| Used module: \picorv32_pcpi_mul |
| Used module: \mgmt_soc_regs |
| Used module: \convert_gpio_sigs |
| Used module: \caravel_clocking |
| Used module: $paramod\clock_div\SIZE=3 |
| Used module: \odd |
| Used module: \even |
| Removed 0 unused modules. |
| |
| 12.2. Executing PROC pass (convert processes to netlists). |
| |
| 12.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Found and cleaned up 16 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| Found and cleaned up 1 empty switch in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$8537'. |
| Found and cleaned up 6 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:546$8183'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:546$8183'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8030'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8024'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8018'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8012'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8006'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8000'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7994'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7988'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7982'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7976'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7970'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7964'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7958'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7952'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7946'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7940'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7934'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7928'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7922'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7916'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7910'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7904'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7898'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7892'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7886'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7880'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7874'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7868'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7862'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7856'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7850'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7844'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7838'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7832'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7826'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7820'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7814'. |
| Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7808'. |
| Found and cleaned up 1 empty switch in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$1580'. |
| Cleaned up 62 empty switches. |
| |
| 12.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). |
| Marked 41 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$8523 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$8518 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Marked 8 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$8483 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$8221 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Marked 47 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$8216 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$8192 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$8154 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Removed 2 dead cases from process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$8151 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$8151 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$8146 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$8072 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Marked 8 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:125$8045 in module $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la. |
| Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:118$6633 in module $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl. |
| Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:106$6623 in module $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8030 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8024 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8018 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8012 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8006 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8000 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7994 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7988 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7982 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7976 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7970 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7964 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7958 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7952 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7946 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7940 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7934 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7928 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7922 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7916 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7910 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7904 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7898 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7892 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7886 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7880 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7874 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7868 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7862 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7856 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7850 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7844 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7838 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7832 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7826 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7820 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7814 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7808 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:245$7802 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:245$7796 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 11 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:299$7572 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:223$7565 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:205$7559 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 43 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:182$7557 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$5947 in module $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:41$2751 in module mem_wb. |
| Marked 22 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:185$2114 in module counter_timer_low. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:153$2104 in module counter_timer_low. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:131$2102 in module counter_timer_low. |
| Marked 17 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:179$2053 in module counter_timer_high. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:151$2045 in module counter_timer_high. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:129$2043 in module counter_timer_high. |
| Marked 5 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:351$2008 in module simple_spi_master. |
| Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:338$2002 in module simple_spi_master. |
| Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:319$1996 in module simple_spi_master. |
| Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:283$1985 in module simple_spi_master. |
| Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:239$1968 in module simple_spi_master. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:208$1966 in module simple_spi_master. |
| Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:190$1921 in module simpleuart. |
| Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:147$1911 in module simpleuart. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:134$1909 in module simpleuart. |
| Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863 in module spimemio_xfer. |
| Marked 5 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839 in module spimemio_xfer. |
| Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809 in module spimemio. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:242$1741 in module spimemio. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:64$5299 in module $paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb. |
| Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1661 in module picorv32_pcpi_div. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:29$3640 in module $paramod\clock_div\SIZE=3. |
| Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1618 in module picorv32_pcpi_mul. |
| Marked 16 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606 in module housekeeping_spi_slave. |
| Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:356$3596 in module housekeeping_spi_slave. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:197$3589 in module housekeeping_spi. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:81$858 in module caravel_clocking. |
| Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:32$853 in module caravel_clocking. |
| Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:176$847 in module even. |
| Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:132$839 in module odd. |
| Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:94$831 in module odd. |
| Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:71$825 in module odd. |
| Removed a total of 2 dead cases. |
| |
| 12.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). |
| Removed 24 redundant assignments. |
| Promoted 296 assignments to connections. |
| |
| 12.2.4. Executing PROC_INIT pass (extract init attributes). |
| |
| 12.2.5. Executing PROC_ARST pass (detect async resets in processes). |
| Found async reset \resetn in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:299$7572'. |
| Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:185$2114'. |
| Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:153$2104'. |
| Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:131$2102'. |
| Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:179$2053'. |
| Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:151$2045'. |
| Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:129$2043'. |
| Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:351$2008'. |
| Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:338$2002'. |
| Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:319$1996'. |
| Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:283$1985'. |
| Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:239$1968'. |
| Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:208$1966'. |
| Found async reset \resetb in `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:29$3640'. |
| Found async reset \csb_reset in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| Found async reset \csb_reset in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:356$3596'. |
| Found async reset \RSTB in `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:197$3589'. |
| Found async reset \resetb in `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:81$858'. |
| Found async reset \resetb in `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:32$853'. |
| Found async reset \resetb in `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:176$847'. |
| Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:132$839'. |
| Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:94$831'. |
| Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:71$825'. |
| |
| 12.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| 1/86: $23\next_irq_pending[2:2] |
| 2/86: $22\next_irq_pending[2:2] |
| 3/86: $21\next_irq_pending[2:2] |
| 4/86: $20\next_irq_pending[2:2] |
| 5/86: $19\next_irq_pending[2:2] |
| 6/86: $18\next_irq_pending[2:2] |
| 7/86: $17\next_irq_pending[2:2] |
| 8/86: $16\next_irq_pending[0:0] |
| 9/86: $15\next_irq_pending[0:0] |
| 10/86: $14\next_irq_pending[31:0] [0] |
| 11/86: $14\next_irq_pending[31:0] [31:1] |
| 12/86: $2\next_irq_pending[31:0] [31:2] |
| 13/86: $3\set_mem_do_rdata[0:0] |
| 14/86: $2\next_irq_pending[31:0] [1] |
| 15/86: $3\set_mem_do_wdata[0:0] |
| 16/86: $2\next_irq_pending[31:0] [0] |
| 17/86: $4\set_mem_do_rinst[0:0] |
| 18/86: $3\set_mem_do_rinst[0:0] |
| 19/86: $4\set_mem_do_wdata[0:0] |
| 20/86: $12\next_irq_pending[1:1] |
| 21/86: $11\next_irq_pending[1:1] |
| 22/86: $10\next_irq_pending[1:1] |
| 23/86: $4\set_mem_do_rdata[0:0] |
| 24/86: $8\next_irq_pending[1:1] |
| 25/86: $7\next_irq_pending[1:1] |
| 26/86: $6\next_irq_pending[1:1] |
| 27/86: $5\next_irq_pending[1:1] |
| 28/86: $4\next_irq_pending[1:1] |
| 29/86: $13\next_irq_pending[1:1] |
| 30/86: $5\set_mem_do_rinst[0:0] |
| 31/86: $9\next_irq_pending[1:1] |
| 32/86: $3\next_irq_pending[31:0] |
| 33/86: $3\current_pc[31:0] |
| 34/86: $2\current_pc[31:0] |
| 35/86: $2\set_mem_do_wdata[0:0] |
| 36/86: $2\set_mem_do_rdata[0:0] |
| 37/86: $2\set_mem_do_rinst[0:0] |
| 38/86: $1\next_irq_pending[31:0] |
| 39/86: $1\current_pc[31:0] |
| 40/86: $1\set_mem_do_wdata[0:0] |
| 41/86: $1\set_mem_do_rdata[0:0] |
| 42/86: $1\set_mem_do_rinst[0:0] |
| 43/86: $0\trace_data[35:0] |
| 44/86: $0\count_cycle[63:0] |
| 45/86: $0\pcpi_timeout[0:0] |
| 46/86: $0\trace_valid[0:0] |
| 47/86: $0\do_waitirq[0:0] |
| 48/86: $0\decoder_pseudo_trigger[0:0] |
| 49/86: $0\decoder_trigger[0:0] |
| 50/86: $0\alu_wait_2[0:0] |
| 51/86: $0\alu_wait[0:0] |
| 52/86: $0\reg_out[31:0] |
| 53/86: $0\reg_sh[4:0] |
| 54/86: $0\trap[0:0] |
| 55/86: $0\pcpi_timeout_counter[3:0] |
| 56/86: $0\latched_rd[4:0] |
| 57/86: $0\latched_is_lb[0:0] |
| 58/86: $0\latched_is_lh[0:0] |
| 59/86: $0\latched_is_lu[0:0] |
| 60/86: $0\latched_trace[0:0] |
| 61/86: $0\latched_compr[0:0] |
| 62/86: $0\latched_branch[0:0] |
| 63/86: $0\latched_stalu[0:0] |
| 64/86: $0\latched_store[0:0] |
| 65/86: $0\irq_state[1:0] |
| 66/86: $0\cpu_state[7:0] |
| 67/86: $0\dbg_rs2val_valid[0:0] |
| 68/86: $0\dbg_rs1val_valid[0:0] |
| 69/86: $0\dbg_rs2val[31:0] |
| 70/86: $0\dbg_rs1val[31:0] |
| 71/86: $0\mem_do_wdata[0:0] |
| 72/86: $0\mem_do_rdata[0:0] |
| 73/86: $0\mem_do_rinst[0:0] |
| 74/86: $0\mem_do_prefetch[0:0] |
| 75/86: $0\mem_wordsize[1:0] |
| 76/86: $0\timer[31:0] |
| 77/86: $0\irq_mask[31:0] |
| 78/86: $0\irq_active[0:0] |
| 79/86: $0\irq_delay[0:0] |
| 80/86: $0\reg_op2[31:0] |
| 81/86: $0\reg_op1[31:0] |
| 82/86: $0\reg_next_pc[31:0] |
| 83/86: $0\reg_pc[31:0] |
| 84/86: $0\count_instr[63:0] |
| 85/86: $0\eoi[31:0] |
| 86/86: $0\pcpi_valid[0:0] |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$8537'. |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$8523'. |
| 1/4: $2\cpuregs_write[0:0] |
| 2/4: $2\cpuregs_wrdata[31:0] |
| 3/4: $1\cpuregs_wrdata[31:0] |
| 4/4: $1\cpuregs_write[0:0] |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$8518'. |
| 1/2: $2\clear_prefetched_high_word[0:0] |
| 2/2: $1\clear_prefetched_high_word[0:0] |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$8517'. |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$8495'. |
| 1/2: $1\alu_out[31:0] |
| 2/2: $1\alu_out_0[0:0] |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$8483'. |
| 1/8: $8\dbg_ascii_state[127:0] |
| 2/8: $7\dbg_ascii_state[127:0] |
| 3/8: $6\dbg_ascii_state[127:0] |
| 4/8: $5\dbg_ascii_state[127:0] |
| 5/8: $4\dbg_ascii_state[127:0] |
| 6/8: $3\dbg_ascii_state[127:0] |
| 7/8: $2\dbg_ascii_state[127:0] |
| 8/8: $1\dbg_ascii_state[127:0] |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| 1/76: $0\decoded_rs1[4:0] [4] |
| 2/76: $0\decoded_imm_j[31:0] [10] |
| 3/76: $0\decoded_imm_j[31:0] [7] |
| 4/76: $0\decoded_imm_j[31:0] [6] |
| 5/76: $0\decoded_imm_j[31:0] [3:1] |
| 6/76: $0\decoded_imm_j[31:0] [5] |
| 7/76: $0\decoded_imm_j[31:0] [9:8] |
| 8/76: $0\decoded_imm_j[31:0] [31:20] |
| 9/76: $0\decoded_imm_j[31:0] [4] |
| 10/76: $0\decoded_imm_j[31:0] [11] |
| 11/76: $0\decoded_imm_j[31:0] [0] |
| 12/76: $0\decoded_rs1[4:0] [3:0] |
| 13/76: $0\is_lui_auipc_jal_jalr_addi_add_sub[0:0] |
| 14/76: $0\is_alu_reg_reg[0:0] |
| 15/76: $0\is_alu_reg_imm[0:0] |
| 16/76: $0\is_beq_bne_blt_bge_bltu_bgeu[0:0] |
| 17/76: $0\is_sll_srl_sra[0:0] |
| 18/76: $0\is_sb_sh_sw[0:0] |
| 19/76: $0\is_jalr_addi_slti_sltiu_xori_ori_andi[0:0] |
| 20/76: $0\is_slli_srli_srai[0:0] |
| 21/76: $0\is_lb_lh_lw_lbu_lhu[0:0] |
| 22/76: $0\compressed_instr[0:0] |
| 23/76: $0\is_compare[0:0] |
| 24/76: $0\decoded_imm[31:0] |
| 25/76: $0\decoded_rs2[4:0] |
| 26/76: $0\decoded_imm_j[31:0] [19:12] |
| 27/76: $0\decoded_rd[4:0] |
| 28/76: $0\instr_timer[0:0] |
| 29/76: $0\instr_waitirq[0:0] |
| 30/76: $0\instr_maskirq[0:0] |
| 31/76: $0\instr_retirq[0:0] |
| 32/76: $0\instr_setq[0:0] |
| 33/76: $0\instr_getq[0:0] |
| 34/76: $0\instr_ecall_ebreak[0:0] |
| 35/76: $0\instr_rdinstrh[0:0] |
| 36/76: $0\instr_rdinstr[0:0] |
| 37/76: $0\instr_rdcycleh[0:0] |
| 38/76: $0\instr_rdcycle[0:0] |
| 39/76: $0\instr_and[0:0] |
| 40/76: $0\instr_or[0:0] |
| 41/76: $0\instr_sra[0:0] |
| 42/76: $0\instr_srl[0:0] |
| 43/76: $0\instr_xor[0:0] |
| 44/76: $0\instr_sltu[0:0] |
| 45/76: $0\instr_slt[0:0] |
| 46/76: $0\instr_sll[0:0] |
| 47/76: $0\instr_sub[0:0] |
| 48/76: $0\instr_add[0:0] |
| 49/76: $0\instr_srai[0:0] |
| 50/76: $0\instr_srli[0:0] |
| 51/76: $0\instr_slli[0:0] |
| 52/76: $0\instr_andi[0:0] |
| 53/76: $0\instr_ori[0:0] |
| 54/76: $0\instr_xori[0:0] |
| 55/76: $0\instr_sltiu[0:0] |
| 56/76: $0\instr_slti[0:0] |
| 57/76: $0\instr_addi[0:0] |
| 58/76: $0\instr_sw[0:0] |
| 59/76: $0\instr_sh[0:0] |
| 60/76: $0\instr_sb[0:0] |
| 61/76: $0\instr_lhu[0:0] |
| 62/76: $0\instr_lbu[0:0] |
| 63/76: $0\instr_lw[0:0] |
| 64/76: $0\instr_lh[0:0] |
| 65/76: $0\instr_lb[0:0] |
| 66/76: $0\instr_bgeu[0:0] |
| 67/76: $0\instr_bltu[0:0] |
| 68/76: $0\instr_bge[0:0] |
| 69/76: $0\instr_blt[0:0] |
| 70/76: $0\instr_bne[0:0] |
| 71/76: $0\instr_beq[0:0] |
| 72/76: $0\instr_jalr[0:0] |
| 73/76: $0\instr_jal[0:0] |
| 74/76: $0\instr_auipc[0:0] |
| 75/76: $0\instr_lui[0:0] |
| 76/76: $0\pcpi_insn[31:0] |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$8221'. |
| 1/13: $3\dbg_insn_opcode[31:0] |
| 2/13: $2\dbg_insn_rd[4:0] |
| 3/13: $2\dbg_insn_rs2[4:0] |
| 4/13: $2\dbg_insn_rs1[4:0] |
| 5/13: $2\dbg_insn_opcode[31:0] |
| 6/13: $2\dbg_insn_imm[31:0] |
| 7/13: $2\dbg_ascii_instr[63:0] |
| 8/13: $1\dbg_insn_rd[4:0] |
| 9/13: $1\dbg_insn_rs2[4:0] |
| 10/13: $1\dbg_insn_rs1[4:0] |
| 11/13: $1\dbg_insn_imm[31:0] |
| 12/13: $1\dbg_ascii_instr[63:0] |
| 13/13: $1\dbg_insn_opcode[31:0] |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| 1/8: $0\cached_insn_rd[4:0] |
| 2/8: $0\cached_insn_rs2[4:0] |
| 3/8: $0\cached_insn_rs1[4:0] |
| 4/8: $0\cached_insn_opcode[31:0] |
| 5/8: $0\cached_insn_imm[31:0] |
| 6/8: $0\cached_ascii_instr[63:0] |
| 7/8: $0\dbg_valid_insn[0:0] |
| 8/8: $0\dbg_insn_addr[31:0] |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$8216'. |
| 1/47: $47\new_ascii_instr[63:0] |
| 2/47: $46\new_ascii_instr[63:0] |
| 3/47: $45\new_ascii_instr[63:0] |
| 4/47: $44\new_ascii_instr[63:0] |
| 5/47: $43\new_ascii_instr[63:0] |
| 6/47: $42\new_ascii_instr[63:0] |
| 7/47: $41\new_ascii_instr[63:0] |
| 8/47: $40\new_ascii_instr[63:0] |
| 9/47: $39\new_ascii_instr[63:0] |
| 10/47: $38\new_ascii_instr[63:0] |
| 11/47: $37\new_ascii_instr[63:0] |
| 12/47: $36\new_ascii_instr[63:0] |
| 13/47: $35\new_ascii_instr[63:0] |
| 14/47: $34\new_ascii_instr[63:0] |
| 15/47: $33\new_ascii_instr[63:0] |
| 16/47: $32\new_ascii_instr[63:0] |
| 17/47: $31\new_ascii_instr[63:0] |
| 18/47: $30\new_ascii_instr[63:0] |
| 19/47: $29\new_ascii_instr[63:0] |
| 20/47: $28\new_ascii_instr[63:0] |
| 21/47: $27\new_ascii_instr[63:0] |
| 22/47: $26\new_ascii_instr[63:0] |
| 23/47: $25\new_ascii_instr[63:0] |
| 24/47: $24\new_ascii_instr[63:0] |
| 25/47: $23\new_ascii_instr[63:0] |
| 26/47: $22\new_ascii_instr[63:0] |
| 27/47: $21\new_ascii_instr[63:0] |
| 28/47: $20\new_ascii_instr[63:0] |
| 29/47: $19\new_ascii_instr[63:0] |
| 30/47: $18\new_ascii_instr[63:0] |
| 31/47: $17\new_ascii_instr[63:0] |
| 32/47: $16\new_ascii_instr[63:0] |
| 33/47: $15\new_ascii_instr[63:0] |
| 34/47: $14\new_ascii_instr[63:0] |
| 35/47: $13\new_ascii_instr[63:0] |
| 36/47: $12\new_ascii_instr[63:0] |
| 37/47: $11\new_ascii_instr[63:0] |
| 38/47: $10\new_ascii_instr[63:0] |
| 39/47: $9\new_ascii_instr[63:0] |
| 40/47: $8\new_ascii_instr[63:0] |
| 41/47: $7\new_ascii_instr[63:0] |
| 42/47: $6\new_ascii_instr[63:0] |
| 43/47: $5\new_ascii_instr[63:0] |
| 44/47: $4\new_ascii_instr[63:0] |
| 45/47: $3\new_ascii_instr[63:0] |
| 46/47: $2\new_ascii_instr[63:0] |
| 47/47: $1\new_ascii_instr[63:0] |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$8192'. |
| 1/9: $0\mem_16bit_buffer[15:0] |
| 2/9: $0\prefetched_high_word[0:0] |
| 3/9: $0\mem_la_secondword[0:0] |
| 4/9: $0\mem_state[1:0] |
| 5/9: $0\mem_wstrb[3:0] |
| 6/9: $0\mem_wdata[31:0] |
| 7/9: $0\mem_addr[31:0] |
| 8/9: $0\mem_instr[0:0] |
| 9/9: $0\mem_valid[0:0] |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$8731'. |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$8154'. |
| 1/9: $0\mem_rdata_q[31:0] [31] |
| 2/9: $0\mem_rdata_q[31:0] [7] |
| 3/9: $0\mem_rdata_q[31:0] [24:20] |
| 4/9: $0\mem_rdata_q[31:0] [19:15] |
| 5/9: $0\mem_rdata_q[31:0] [6:0] |
| 6/9: $0\mem_rdata_q[31:0] [14:12] |
| 7/9: $0\mem_rdata_q[31:0] [11:8] |
| 8/9: $0\mem_rdata_q[31:0] [30:25] |
| 9/9: $0\next_insn_opcode[31:0] |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$8151'. |
| 1/5: $3\mem_rdata_word[31:0] |
| 2/5: $2\mem_rdata_word[31:0] |
| 3/5: $1\mem_rdata_word[31:0] |
| 4/5: $1\mem_la_wstrb[3:0] |
| 5/5: $1\mem_la_wdata[31:0] |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$8146'. |
| 1/2: $0\last_mem_valid[0:0] |
| 2/2: $0\mem_la_firstword_reg[0:0] |
| Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$8072'. |
| 1/2: $1\pcpi_int_rd[31:0] |
| 2/2: $1\pcpi_int_wr[0:0] |
| Creating decoders for process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:125$8045'. |
| 1/34: $0\la_ena_3[31:0] [31:24] |
| 2/34: $0\la_ena_3[31:0] [23:16] |
| 3/34: $0\la_ena_3[31:0] [15:8] |
| 4/34: $0\la_ena_3[31:0] [7:0] |
| 5/34: $0\la_ena_2[31:0] [23:16] |
| 6/34: $0\la_ena_2[31:0] [15:8] |
| 7/34: $0\la_ena_2[31:0] [7:0] |
| 8/34: $0\la_ena_1[31:0] [23:16] |
| 9/34: $0\la_ena_1[31:0] [15:8] |
| 10/34: $0\la_ena_1[31:0] [7:0] |
| 11/34: $0\la_ena_0[31:0] [23:16] |
| 12/34: $0\la_ena_0[31:0] [15:8] |
| 13/34: $0\la_ena_0[31:0] [7:0] |
| 14/34: $0\la_data_3[31:0] [23:16] |
| 15/34: $0\la_data_3[31:0] [15:8] |
| 16/34: $0\la_data_3[31:0] [7:0] |
| 17/34: $0\la_data_2[31:0] [23:16] |
| 18/34: $0\la_data_2[31:0] [15:8] |
| 19/34: $0\la_data_2[31:0] [7:0] |
| 20/34: $0\la_data_1[31:0] [23:16] |
| 21/34: $0\la_data_1[31:0] [15:8] |
| 22/34: $0\la_data_1[31:0] [7:0] |
| 23/34: $0\la_data_0[31:0] [23:16] |
| 24/34: $0\la_data_0[31:0] [15:8] |
| 25/34: $0\la_data_0[31:0] [7:0] |
| 26/34: $0\la_ena_1[31:0] [31:24] |
| 27/34: $0\la_ena_0[31:0] [31:24] |
| 28/34: $0\la_data_3[31:0] [31:24] |
| 29/34: $0\la_data_2[31:0] [31:24] |
| 30/34: $0\la_data_1[31:0] [31:24] |
| 31/34: $0\la_data_0[31:0] [31:24] |
| 32/34: $0\la_ena_2[31:0] [31:24] |
| 33/34: $0\iomem_ready[0:0] |
| 34/34: $0\iomem_rdata[31:0] |
| Creating decoders for process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:118$6633'. |
| 1/7: $0\irq_8_inputsrc[0:0] |
| 2/7: $0\irq_7_inputsrc[0:0] |
| 3/7: $0\trap_output_dest[0:0] |
| 4/7: $0\clk2_output_dest[0:0] |
| 5/7: $0\clk1_output_dest[0:0] |
| 6/7: $0\iomem_ready[0:0] |
| 7/7: $0\iomem_rdata[31:0] |
| Creating decoders for process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:106$6623'. |
| 1/6: $0\iomem_ready[0:0] |
| 2/6: $0\iomem_rdata[31:0] |
| 3/6: $0\gpio_pd[0:0] |
| 4/6: $0\gpio_pu[0:0] |
| 5/6: $0\gpio_oeb[0:0] |
| 6/6: $0\gpio[0:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8030'. |
| 1/1: $0\io_ctrl[37][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8024'. |
| 1/1: $0\io_ctrl[36][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8018'. |
| 1/1: $0\io_ctrl[35][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8012'. |
| 1/1: $0\io_ctrl[34][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8006'. |
| 1/1: $0\io_ctrl[33][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8000'. |
| 1/1: $0\io_ctrl[32][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7994'. |
| 1/1: $0\io_ctrl[31][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7988'. |
| 1/1: $0\io_ctrl[30][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7982'. |
| 1/1: $0\io_ctrl[29][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7976'. |
| 1/1: $0\io_ctrl[28][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7970'. |
| 1/1: $0\io_ctrl[27][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7964'. |
| 1/1: $0\io_ctrl[26][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7958'. |
| 1/1: $0\io_ctrl[25][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7952'. |
| 1/1: $0\io_ctrl[24][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7946'. |
| 1/1: $0\io_ctrl[23][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7940'. |
| 1/1: $0\io_ctrl[22][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7934'. |
| 1/1: $0\io_ctrl[21][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7928'. |
| 1/1: $0\io_ctrl[20][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7922'. |
| 1/1: $0\io_ctrl[19][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7916'. |
| 1/1: $0\io_ctrl[18][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7910'. |
| 1/1: $0\io_ctrl[17][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7904'. |
| 1/1: $0\io_ctrl[16][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7898'. |
| 1/1: $0\io_ctrl[15][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7892'. |
| 1/1: $0\io_ctrl[14][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7886'. |
| 1/1: $0\io_ctrl[13][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7880'. |
| 1/1: $0\io_ctrl[12][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7874'. |
| 1/1: $0\io_ctrl[11][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7868'. |
| 1/1: $0\io_ctrl[10][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7862'. |
| 1/1: $0\io_ctrl[9][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7856'. |
| 1/1: $0\io_ctrl[8][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7850'. |
| 1/1: $0\io_ctrl[7][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7844'. |
| 1/1: $0\io_ctrl[6][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7838'. |
| 1/1: $0\io_ctrl[5][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7832'. |
| 1/1: $0\io_ctrl[4][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7826'. |
| 1/1: $0\io_ctrl[3][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7820'. |
| 1/1: $0\io_ctrl[2][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7814'. |
| 1/1: $0\io_ctrl[1][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7808'. |
| 1/1: $0\io_ctrl[0][12:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:245$7802'. |
| 1/1: $0\mgmt_gpio_outr[37:32] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:245$7796'. |
| 1/1: $0\mgmt_gpio_outr[31:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7792'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7787'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7782'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7777'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7772'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7767'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7762'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7757'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7752'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7747'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7742'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7737'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7732'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7727'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7722'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7717'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7712'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7707'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7702'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7697'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7692'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7687'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7682'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7677'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7672'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7667'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7662'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7657'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7652'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7647'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7642'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7637'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7632'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7627'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7622'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7617'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7612'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7607'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7602'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7600'. |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:299$7572'. |
| 1/13: $4$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$7549_DATA[12:0]$7587 |
| 2/13: $3$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$7549_DATA[12:0]$7584 |
| 3/13: $3$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$7549_ADDR[5:0]$7583 |
| 4/13: $2$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$7549_DATA[12:0]$7580 |
| 5/13: $2$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$7549_ADDR[5:0]$7579 |
| 6/13: $1$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$7549_DATA[12:0]$7577 |
| 7/13: $1$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$7549_ADDR[5:0]$7576 |
| 8/13: $0\serial_data_staging[12:0] |
| 9/13: $0\xfer_state[1:0] |
| 10/13: $0\pad_count[5:0] |
| 11/13: $0\xfer_count[3:0] |
| 12/13: $0\serial_resetn[0:0] |
| 13/13: $0\serial_clock[0:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:223$7565'. |
| 1/2: $0\xfer_ctrl[0:0] |
| 2/2: $0\pwr_ctrl_out[3:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:205$7559'. |
| 1/2: $0\iomem_ready[0:0] |
| 2/2: $0\iomem_rdata[31:0] |
| Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:182$7557'. |
| 1/46: $43\iomem_rdata_pre[31:0] |
| 2/46: $42\iomem_rdata_pre[31:0] |
| 3/46: $41\iomem_rdata_pre[31:0] |
| 4/46: $40\iomem_rdata_pre[31:0] |
| 5/46: $39\iomem_rdata_pre[31:0] |
| 6/46: $38\iomem_rdata_pre[31:0] |
| 7/46: $37\iomem_rdata_pre[31:0] |
| 8/46: $36\iomem_rdata_pre[31:0] |
| 9/46: $35\iomem_rdata_pre[31:0] |
| 10/46: $34\iomem_rdata_pre[31:0] |
| 11/46: $33\iomem_rdata_pre[31:0] |
| 12/46: $32\iomem_rdata_pre[31:0] |
| 13/46: $31\iomem_rdata_pre[31:0] |
| 14/46: $30\iomem_rdata_pre[31:0] |
| 15/46: $29\iomem_rdata_pre[31:0] |
| 16/46: $28\iomem_rdata_pre[31:0] |
| 17/46: $27\iomem_rdata_pre[31:0] |
| 18/46: $26\iomem_rdata_pre[31:0] |
| 19/46: $25\iomem_rdata_pre[31:0] |
| 20/46: $24\iomem_rdata_pre[31:0] |
| 21/46: $23\iomem_rdata_pre[31:0] |
| 22/46: $22\iomem_rdata_pre[31:0] |
| 23/46: $21\iomem_rdata_pre[31:0] |
| 24/46: $20\iomem_rdata_pre[31:0] |
| 25/46: $19\iomem_rdata_pre[31:0] |
| 26/46: $18\iomem_rdata_pre[31:0] |
| 27/46: $17\iomem_rdata_pre[31:0] |
| 28/46: $16\iomem_rdata_pre[31:0] |
| 29/46: $15\iomem_rdata_pre[31:0] |
| 30/46: $14\iomem_rdata_pre[31:0] |
| 31/46: $13\iomem_rdata_pre[31:0] |
| 32/46: $12\iomem_rdata_pre[31:0] |
| 33/46: $11\iomem_rdata_pre[31:0] |
| 34/46: $10\iomem_rdata_pre[31:0] |
| 35/46: $9\iomem_rdata_pre[31:0] |
| 36/46: $8\iomem_rdata_pre[31:0] |
| 37/46: $7\iomem_rdata_pre[31:0] |
| 38/46: $6\iomem_rdata_pre[31:0] |
| 39/46: $5\iomem_rdata_pre[31:0] |
| 40/46: $4\iomem_rdata_pre[31:0] |
| 41/46: $3\j[31:0] |
| 42/46: $3\iomem_rdata_pre[31:0] |
| 43/46: $2\iomem_rdata_pre[31:0] |
| 44/46: $2\j[31:0] |
| 45/46: $1\iomem_rdata_pre[31:0] |
| 46/46: $1\j[31:0] |
| Creating decoders for process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$5947'. |
| 1/9: $0\state[1:0] |
| 2/9: $0\wbm_cyc_o[0:0] |
| 3/9: $0\wbm_stb_o[0:0] |
| 4/9: $0\wbm_sel_o[3:0] |
| 5/9: $0\wbm_we_o[0:0] |
| 6/9: $0\wbm_dat_o[31:0] |
| 7/9: $0\wbm_adr_o[31:0] |
| 8/9: $0\mem_rdata[31:0] |
| 9/9: $0\mem_ready[0:0] |
| Creating decoders for process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:41$2751'. |
| 1/2: $0\wb_ack_o[0:0] |
| 2/2: $0\wb_ack_read[0:0] |
| Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:185$2114'. |
| 1/8: $0\value_cur[31:0] [31:24] |
| 2/8: $0\value_cur[31:0] [7:0] |
| 3/8: $0\value_cur[31:0] [15:8] |
| 4/8: $0\value_cur[31:0] [23:16] |
| 5/8: $0\lastenable[0:0] |
| 6/8: $0\stop_out[0:0] |
| 7/8: $0\strobe[0:0] |
| 8/8: $0\irq_out[0:0] |
| Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:153$2104'. |
| 1/4: $0\value_reset[31:0] [15:8] |
| 2/4: $0\value_reset[31:0] [7:0] |
| 3/4: $0\value_reset[31:0] [23:16] |
| 4/4: $0\value_reset[31:0] [31:24] |
| Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:131$2102'. |
| 1/5: $0\chain[0:0] |
| 2/5: $0\irq_ena[0:0] |
| 3/5: $0\updown[0:0] |
| 4/5: $0\oneshot[0:0] |
| 5/5: $0\enable[0:0] |
| Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:179$2053'. |
| 1/7: $0\value_cur[31:0] [31:24] |
| 2/7: $0\value_cur[31:0] [23:16] |
| 3/7: $0\value_cur[31:0] [7:0] |
| 4/7: $0\value_cur[31:0] [15:8] |
| 5/7: $0\lastenable[0:0] |
| 6/7: $0\stop_out[0:0] |
| 7/7: $0\irq_out[0:0] |
| Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:151$2045'. |
| 1/4: $0\value_reset[31:0] [15:8] |
| 2/4: $0\value_reset[31:0] [7:0] |
| 3/4: $0\value_reset[31:0] [23:16] |
| 4/4: $0\value_reset[31:0] [31:24] |
| Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:129$2043'. |
| 1/5: $0\chain[0:0] |
| 2/5: $0\irq_ena[0:0] |
| 3/5: $0\updown[0:0] |
| 4/5: $0\oneshot[0:0] |
| 5/5: $0\enable[0:0] |
| Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:351$2008'. |
| 1/3: $0\rreg[7:0] |
| 2/3: $0\treg[7:0] |
| 3/3: $0\isdo[0:0] |
| Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:338$2002'. |
| 1/1: $0\isck[0:0] |
| Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:319$1996'. |
| 1/2: $0\count[7:0] |
| 2/2: $0\hsck[0:0] |
| Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:283$1985'. |
| 1/4: $0\nbit[2:0] |
| 2/4: $0\icsb[0:0] |
| 3/4: $0\done[0:0] |
| 4/4: $0\state[1:0] |
| Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:239$1968'. |
| 1/4: $0\r_latched[0:0] |
| 2/4: $0\w_latched[0:0] |
| 3/4: $0\d_latched[7:0] |
| 4/4: $0\err_out[0:0] |
| Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:208$1966'. |
| 1/9: $0\hkconn[0:0] |
| 2/9: $0\mode[0:0] |
| 3/9: $0\stream[0:0] |
| 4/9: $0\irqena[0:0] |
| 5/9: $0\mlb[0:0] |
| 6/9: $0\invcsb[0:0] |
| 7/9: $0\invsck[0:0] |
| 8/9: $0\prescaler[7:0] |
| 9/9: $0\enable[0:0] |
| Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:190$1921'. |
| 1/4: $0\send_divcnt[31:0] |
| 2/4: $0\send_dummy[0:0] |
| 3/4: $0\send_bitcnt[3:0] |
| 4/4: $0\send_pattern[9:0] |
| Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:147$1911'. |
| 1/5: $0\recv_divcnt[31:0] |
| 2/5: $0\recv_buf_valid[0:0] |
| 3/5: $0\recv_buf_data[7:0] |
| 4/5: $0\recv_pattern[7:0] |
| 5/5: $0\recv_state[3:0] |
| Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:134$1909'. |
| 1/5: $0\cfg_divider[31:0] [31:24] |
| 2/5: $0\cfg_divider[31:0] [23:16] |
| 3/5: $0\cfg_divider[31:0] [15:8] |
| 4/5: $0\cfg_divider[31:0] [7:0] |
| 5/5: $0\enabled[0:0] |
| Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| 1/14: $0\last_fetch[0:0] |
| 2/14: $0\fetch[0:0] |
| 3/14: $0\xfer_tag[3:0] |
| 4/14: $0\xfer_rd[0:0] |
| 5/14: $0\xfer_qspi[0:0] |
| 6/14: $0\xfer_cont[0:0] |
| 7/14: $0\dummy_count[3:0] |
| 8/14: $0\count[3:0] |
| 9/14: $0\ibuffer[7:0] |
| 10/14: $0\obuffer[7:0] |
| 11/14: $0\xfer_ddr[0:0] |
| 12/14: $0\xfer_dspi[0:0] |
| 13/14: $0\flash_clk[0:0] |
| 14/14: $0\flash_csb[0:0] |
| Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| 1/33: $5\next_count[3:0] |
| 2/33: $5\next_obuffer[7:0] |
| 3/33: $5\next_ibuffer[7:0] |
| 4/33: $4\next_count[3:0] |
| 5/33: $4\next_obuffer[7:0] |
| 6/33: $4\next_ibuffer[7:0] |
| 7/33: $3\next_count[3:0] |
| 8/33: $3\next_obuffer[7:0] |
| 9/33: $3\next_ibuffer[7:0] |
| 10/33: $2\next_fetch[0:0] |
| 11/33: $2\next_count[3:0] |
| 12/33: $2\next_ibuffer[7:0] |
| 13/33: $2\next_obuffer[7:0] |
| 14/33: $2\flash_io0_do[0:0] |
| 15/33: $2\flash_io0_oe[0:0] |
| 16/33: $2\flash_io3_oe[0:0] |
| 17/33: $2\flash_io2_oe[0:0] |
| 18/33: $2\flash_io1_oe[0:0] |
| 19/33: $2\flash_io3_do[0:0] |
| 20/33: $2\flash_io2_do[0:0] |
| 21/33: $2\flash_io1_do[0:0] |
| 22/33: $1\next_fetch[0:0] |
| 23/33: $1\next_count[3:0] |
| 24/33: $1\next_ibuffer[7:0] |
| 25/33: $1\next_obuffer[7:0] |
| 26/33: $1\flash_io3_oe[0:0] |
| 27/33: $1\flash_io2_oe[0:0] |
| 28/33: $1\flash_io1_oe[0:0] |
| 29/33: $1\flash_io0_oe[0:0] |
| 30/33: $1\flash_io3_do[0:0] |
| 31/33: $1\flash_io2_do[0:0] |
| 32/33: $1\flash_io1_do[0:0] |
| 33/33: $1\flash_io0_do[0:0] |
| Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:597$1830'. |
| Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| 1/17: $0\buffer[23:0] [23:16] |
| 2/17: $0\buffer[23:0] [15:8] |
| 3/17: $0\buffer[23:0] [7:0] |
| 4/17: $0\xfer_resetn[0:0] |
| 5/17: $0\rd_inc[0:0] |
| 6/17: $0\rd_wait[0:0] |
| 7/17: $0\rd_valid[0:0] |
| 8/17: $0\rd_addr[23:0] |
| 9/17: $0\din_valid[0:0] |
| 10/17: $0\din_rd[0:0] |
| 11/17: $0\din_ddr[0:0] |
| 12/17: $0\din_qspi[0:0] |
| 13/17: $0\din_cont[0:0] |
| 14/17: $0\din_tag[3:0] |
| 15/17: $0\din_data[7:0] |
| 16/17: $0\rdata[31:0] |
| 17/17: $0\state[3:0] |
| Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:294$1745'. |
| Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:242$1741'. |
| 1/10: $0\softreset[0:0] |
| 2/10: $0\config_do[3:0] |
| 3/10: $0\config_clk[0:0] |
| 4/10: $0\config_csb[0:0] |
| 5/10: $0\config_oe[3:0] |
| 6/10: $0\config_dummy[3:0] |
| 7/10: $0\config_cont[0:0] |
| 8/10: $0\config_qspi[0:0] |
| 9/10: $0\config_ddr[0:0] |
| 10/10: $0\config_en[0:0] |
| Creating decoders for process `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:111$5444'. |
| Creating decoders for process `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:100$5313'. |
| Creating decoders for process `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:64$5299'. |
| 1/2: $0\wb_ack_o[1:0] |
| 2/2: $0\wb_ack_read[1:0] |
| Creating decoders for process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:51$4107'. |
| Creating decoders for process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1661'. |
| 1/9: $0\pcpi_rd[31:0] |
| 2/9: $0\pcpi_wr[0:0] |
| 3/9: $0\pcpi_ready[0:0] |
| 4/9: $0\outsign[0:0] |
| 5/9: $0\running[0:0] |
| 6/9: $0\quotient_msk[31:0] |
| 7/9: $0\quotient[31:0] |
| 8/9: $0\divisor[62:0] |
| 9/9: $0\dividend[31:0] |
| Creating decoders for process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1651'. |
| 1/4: $0\instr_remu[0:0] |
| 2/4: $0\instr_rem[0:0] |
| 3/4: $0\instr_divu[0:0] |
| 4/4: $0\instr_div[0:0] |
| Creating decoders for process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:29$3640'. |
| 1/2: $0\syncN[2:0] |
| 2/2: $0\syncNp[2:0] |
| Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1623'. |
| 1/3: $0\pcpi_ready[0:0] |
| 2/3: $0\pcpi_wr[0:0] |
| 3/3: $0\pcpi_rd[31:0] |
| Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1618'. |
| 1/7: $0\mul_finish[0:0] |
| 2/7: $0\mul_waiting[0:0] |
| 3/7: $0\mul_counter[6:0] |
| 4/7: $0\rdx[63:0] |
| 5/7: $0\rd[63:0] |
| 6/7: $0\rs2[63:0] |
| 7/7: $0\rs1[63:0] |
| Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$1580'. |
| Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$1574'. |
| 1/4: $0\instr_mulhu[0:0] |
| 2/4: $0\instr_mulhsu[0:0] |
| 3/4: $0\instr_mulh[0:0] |
| 4/4: $0\instr_mul[0:0] |
| Creating decoders for process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| 1/14: $1\pass_thru_user[0:0] |
| 2/14: $0\pre_pass_thru_user[0:0] |
| 3/14: $0\pre_pass_thru_mgmt[0:0] |
| 4/14: $0\predata[6:0] |
| 5/14: $0\fixed[2:0] |
| 6/14: $0\readmode[0:0] |
| 7/14: $0\writemode[0:0] |
| 8/14: $0\pass_thru_user_delay[0:0] |
| 9/14: $0\pass_thru_mgmt_delay[0:0] |
| 10/14: $0\rdstb[0:0] |
| 11/14: $0\count[2:0] |
| 12/14: $0\addr[7:0] |
| 13/14: $0\state[2:0] |
| 14/14: $0\pass_thru_mgmt[0:0] |
| Creating decoders for process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:356$3596'. |
| 1/3: $0\sdoenb[0:0] |
| 2/3: $0\ldata[7:0] |
| 3/3: $0\wrstb[0:0] |
| Creating decoders for process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:197$3589'. |
| 1/12: $0\pll_trim[25:0] [25:24] |
| 2/12: $0\pll_trim[25:0] [23:16] |
| 3/12: $0\pll_trim[25:0] [15:8] |
| 4/12: $0\pll_trim[25:0] [7:0] |
| 5/12: $0\irq[0:0] |
| 6/12: $0\pll_bypass[0:0] |
| 7/12: $0\reset_reg[0:0] |
| 8/12: $0\pll_ena[0:0] |
| 9/12: $0\pll_div[4:0] |
| 10/12: $0\pll90_sel[2:0] |
| 11/12: $0\pll_sel[2:0] |
| 12/12: $0\pll_dco_ena[0:0] |
| Creating decoders for process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:81$858'. |
| 1/1: $0\reset_delay[2:0] |
| Creating decoders for process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:32$853'. |
| 1/4: $0\ext_clk_syncd[0:0] |
| 2/4: $0\use_pll_second[0:0] |
| 3/4: $0\use_pll_first[0:0] |
| 4/4: $0\ext_clk_syncd_pre[0:0] |
| Creating decoders for process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:176$847'. |
| 1/2: $0\out_counter[0:0] |
| 2/2: $0\counter[2:0] |
| Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:145$842'. |
| Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:132$839'. |
| 1/1: $0\rst_pulse[0:0] |
| Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:94$831'. |
| 1/3: $0\initial_begin[2:0] |
| 2/3: $0\out_counter2[0:0] |
| 3/3: $0\counter2[2:0] |
| Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:71$825'. |
| 1/2: $0\out_counter[0:0] |
| 2/2: $0\counter[2:0] |
| Creating decoders for process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:854$3528'. |
| 1/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 |
| 2/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_DATA[31:0]$3530 |
| 3/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_ADDR[4:0]$3529 |
| Creating decoders for process `\mgmt_soc.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:333$3521'. |
| |
| 12.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_rs1' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$8537'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_rs2' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$8537'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$8537'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_write' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$8523'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_wrdata' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$8523'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\clear_prefetched_high_word' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$8518'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$8495'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_0' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$8495'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_ascii_state' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$8483'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_opcode' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$8221'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_ascii_instr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$8221'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_imm' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$8221'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rs1' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$8221'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rs2' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$8221'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rd' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$8221'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\new_ascii_instr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$8216'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_add_sub' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$8731'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_shl' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$8731'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_shr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$8731'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_eq' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$8731'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_ltu' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$8731'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_lts' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$8731'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_wdata' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$8151'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_wstrb' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$8151'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_rdata_word' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$8151'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_wr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$8072'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_rd' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$8072'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_wait' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$8072'. |
| No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_ready' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$8072'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_data_arr[0]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_data_arr[1]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[0]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[1]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[2]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[3]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[4]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[5]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[6]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[7]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[8]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[9]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[10]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[11]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[12]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[13]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[14]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[15]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[16]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[17]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[18]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[19]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[20]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[21]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[22]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[23]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[24]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[25]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[26]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[27]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[28]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[29]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[30]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[31]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[32]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[33]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[34]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[35]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[36]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[37]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7428' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7792'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7426' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7787'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7424' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7782'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7422' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7777'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7420' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7772'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7418' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7767'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7416' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7762'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7414' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7757'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7412' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7752'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7410' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7747'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7408' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7742'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7406' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7737'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7404' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7732'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7402' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7727'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7400' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7722'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7398' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7717'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7396' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7712'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7394' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7707'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7392' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7702'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7390' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7697'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7388' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7692'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7386' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7687'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7384' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7682'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7382' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7677'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7380' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7672'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7378' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7667'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7376' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7662'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7374' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7657'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7372' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7652'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7370' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7647'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7368' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7642'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7366' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7637'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7364' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7632'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7362' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7627'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7360' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7622'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7358' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7617'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7356' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7612'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7354' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7607'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:139$7350' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7602'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:138$7349' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7600'. |
| No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_rdata_pre' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:182$7557'. |
| Latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\j' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:182$7557': $auto$proc_dlatch.cc:430:proc_dlatch$15840 |
| No latch inferred for signal `\spimemio_xfer.\flash_io0_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| No latch inferred for signal `\spimemio_xfer.\flash_io1_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| No latch inferred for signal `\spimemio_xfer.\flash_io2_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| No latch inferred for signal `\spimemio_xfer.\flash_io3_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| No latch inferred for signal `\spimemio_xfer.\flash_io0_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| No latch inferred for signal `\spimemio_xfer.\flash_io1_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| No latch inferred for signal `\spimemio_xfer.\flash_io2_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| No latch inferred for signal `\spimemio_xfer.\flash_io3_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| No latch inferred for signal `\spimemio_xfer.\next_obuffer' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| No latch inferred for signal `\spimemio_xfer.\next_ibuffer' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| No latch inferred for signal `\spimemio_xfer.\next_count' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| No latch inferred for signal `\spimemio_xfer.\next_fetch' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| No latch inferred for signal `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.\wb_user_dat_o' from process `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:111$5444'. |
| No latch inferred for signal `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.\j' from process `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:111$5444'. |
| No latch inferred for signal `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.\wb_mgmt_dat_o' from process `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:100$5313'. |
| No latch inferred for signal `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.\i' from process `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:100$5313'. |
| No latch inferred for signal `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.\i' from process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:51$4107'. |
| No latch inferred for signal `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.\wbm_dat_o' from process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:51$4107'. |
| No latch inferred for signal `\picorv32_pcpi_mul.\i' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$1580'. |
| No latch inferred for signal `\picorv32_pcpi_mul.\j' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$1580'. |
| No latch inferred for signal `\picorv32_pcpi_mul.\next_rs1' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$1580'. |
| No latch inferred for signal `\picorv32_pcpi_mul.\next_rs2' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$1580'. |
| No latch inferred for signal `\picorv32_pcpi_mul.\this_rs2' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$1580'. |
| No latch inferred for signal `\picorv32_pcpi_mul.\next_rd' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$1580'. |
| No latch inferred for signal `\picorv32_pcpi_mul.\next_rdx' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$1580'. |
| No latch inferred for signal `\picorv32_pcpi_mul.\next_rdt' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$1580'. |
| No latch inferred for signal `\mgmt_soc.\irq' from process `\mgmt_soc.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:333$3521'. |
| |
| 12.2.8. Executing PROC_DFF pass (convert process syncs to FFs). |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trap' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15841' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15842' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\eoi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15843' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trace_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15844' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trace_data' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15845' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\count_cycle' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15846' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\count_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15847' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15848' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_next_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15849' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_op1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15850' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_op2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15851' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_out' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15852' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_sh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15853' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_delay' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15854' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_active' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15855' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_mask' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15856' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_pending' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15857' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\timer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15858' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wordsize' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15859' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_prefetch' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15860' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_rinst' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15861' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_rdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15862' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15863' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_trigger' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15864' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_trigger_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15865' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_pseudo_trigger' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15866' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_pseudo_trigger_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15867' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs1val' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15868' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs2val' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15869' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs1val_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15870' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs2val_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15871' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpu_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15872' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15873' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_rinst' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15874' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_rdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15875' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15876' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_store' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15877' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_stalu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15878' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_branch' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15879' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_compr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15880' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_trace' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15881' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15882' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15883' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15884' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15885' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\current_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15886' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_timeout_counter' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15887' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_timeout' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15888' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\next_irq_pending' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15889' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\do_waitirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15890' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15891' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_0_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15892' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_wait' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15893' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_wait_2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| created $dff cell `$procdff$15894' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\clear_prefetched_high_word_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$8517'. |
| created $dff cell `$procdff$15895' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_insn' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15896' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lui' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15897' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_auipc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15898' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_jal' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15899' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_jalr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15900' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_beq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15901' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bne' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15902' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_blt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15903' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bge' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15904' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15905' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bgeu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15906' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15907' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15908' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15909' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lbu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15910' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lhu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15911' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15912' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15913' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15914' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_addi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15915' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slti' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15916' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sltiu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15917' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_xori' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15918' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_ori' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15919' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_andi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15920' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slli' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15921' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srli' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15922' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srai' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15923' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_add' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15924' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sub' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15925' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sll' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15926' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15927' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15928' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_xor' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15929' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srl' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15930' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sra' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15931' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_or' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15932' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_and' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15933' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdcycle' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15934' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdcycleh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15935' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdinstr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15936' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdinstrh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15937' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_ecall_ebreak' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15938' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_getq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15939' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_setq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15940' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_retirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15941' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_maskirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15942' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_waitirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15943' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_timer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15944' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15945' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15946' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15947' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15948' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_imm_j' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15949' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\compressed_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15950' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lui_auipc_jal' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15951' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lb_lh_lw_lbu_lhu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15952' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_slli_srli_srai' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15953' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_jalr_addi_slti_sltiu_xori_ori_andi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15954' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sb_sh_sw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15955' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sll_srl_sra' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15956' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lui_auipc_jal_jalr_addi_add_sub' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15957' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_slti_blt_slt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15958' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sltiu_bltu_sltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15959' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_beq_bne_blt_bge_bltu_bgeu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15960' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lbu_lhu_lw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15961' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_alu_reg_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15962' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_alu_reg_reg' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15963' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_compare' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| created $dff cell `$procdff$15964' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_addr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15965' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_ascii_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15966' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15967' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15968' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15969' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15970' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15971' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_next' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15972' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_valid_insn' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15973' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_ascii_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15974' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15975' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15976' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15977' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15978' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| created $dff cell `$procdff$15979' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$8192'. |
| created $dff cell `$procdff$15980' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$8192'. |
| created $dff cell `$procdff$15981' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_addr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$8192'. |
| created $dff cell `$procdff$15982' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$8192'. |
| created $dff cell `$procdff$15983' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wstrb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$8192'. |
| created $dff cell `$procdff$15984' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$8192'. |
| created $dff cell `$procdff$15985' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_secondword' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$8192'. |
| created $dff cell `$procdff$15986' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\prefetched_high_word' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$8192'. |
| created $dff cell `$procdff$15987' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_16bit_buffer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$8192'. |
| created $dff cell `$procdff$15988' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\next_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$8154'. |
| created $dff cell `$procdff$15989' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_rdata_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$8154'. |
| created $dff cell `$procdff$15990' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_firstword_reg' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$8146'. |
| created $dff cell `$procdff$15991' with positive edge clock. |
| Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\last_mem_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$8146'. |
| created $dff cell `$procdff$15992' with positive edge clock. |
| Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\iomem_rdata' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:125$8045'. |
| created $dff cell `$procdff$15993' with positive edge clock. |
| Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\iomem_ready' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:125$8045'. |
| created $dff cell `$procdff$15994' with positive edge clock. |
| Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_0' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:125$8045'. |
| created $dff cell `$procdff$15995' with positive edge clock. |
| Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_1' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:125$8045'. |
| created $dff cell `$procdff$15996' with positive edge clock. |
| Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_2' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:125$8045'. |
| created $dff cell `$procdff$15997' with positive edge clock. |
| Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_3' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:125$8045'. |
| created $dff cell `$procdff$15998' with positive edge clock. |
| Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_0' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:125$8045'. |
| created $dff cell `$procdff$15999' with positive edge clock. |
| Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_1' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:125$8045'. |
| created $dff cell `$procdff$16000' with positive edge clock. |
| Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_2' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:125$8045'. |
| created $dff cell `$procdff$16001' with positive edge clock. |
| Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_3' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:125$8045'. |
| created $dff cell `$procdff$16002' with positive edge clock. |
| Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\iomem_rdata' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:118$6633'. |
| created $dff cell `$procdff$16003' with positive edge clock. |
| Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\iomem_ready' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:118$6633'. |
| created $dff cell `$procdff$16004' with positive edge clock. |
| Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\clk1_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:118$6633'. |
| created $dff cell `$procdff$16005' with positive edge clock. |
| Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\clk2_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:118$6633'. |
| created $dff cell `$procdff$16006' with positive edge clock. |
| Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\trap_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:118$6633'. |
| created $dff cell `$procdff$16007' with positive edge clock. |
| Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\irq_7_inputsrc' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:118$6633'. |
| created $dff cell `$procdff$16008' with positive edge clock. |
| Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\irq_8_inputsrc' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:118$6633'. |
| created $dff cell `$procdff$16009' with positive edge clock. |
| Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:106$6623'. |
| created $dff cell `$procdff$16010' with positive edge clock. |
| Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_oeb' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:106$6623'. |
| created $dff cell `$procdff$16011' with positive edge clock. |
| Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_pu' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:106$6623'. |
| created $dff cell `$procdff$16012' with positive edge clock. |
| Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_pd' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:106$6623'. |
| created $dff cell `$procdff$16013' with positive edge clock. |
| Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\iomem_rdata' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:106$6623'. |
| created $dff cell `$procdff$16014' with positive edge clock. |
| Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\iomem_ready' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:106$6623'. |
| created $dff cell `$procdff$16015' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[37]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8030'. |
| created $dff cell `$procdff$16016' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[36]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8024'. |
| created $dff cell `$procdff$16017' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[35]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8018'. |
| created $dff cell `$procdff$16018' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[34]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8012'. |
| created $dff cell `$procdff$16019' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[33]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8006'. |
| created $dff cell `$procdff$16020' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[32]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8000'. |
| created $dff cell `$procdff$16021' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[31]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7994'. |
| created $dff cell `$procdff$16022' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[30]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7988'. |
| created $dff cell `$procdff$16023' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[29]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7982'. |
| created $dff cell `$procdff$16024' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[28]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7976'. |
| created $dff cell `$procdff$16025' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[27]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7970'. |
| created $dff cell `$procdff$16026' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[26]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7964'. |
| created $dff cell `$procdff$16027' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[25]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7958'. |
| created $dff cell `$procdff$16028' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[24]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7952'. |
| created $dff cell `$procdff$16029' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[23]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7946'. |
| created $dff cell `$procdff$16030' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[22]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7940'. |
| created $dff cell `$procdff$16031' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[21]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7934'. |
| created $dff cell `$procdff$16032' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[20]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7928'. |
| created $dff cell `$procdff$16033' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[19]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7922'. |
| created $dff cell `$procdff$16034' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[18]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7916'. |
| created $dff cell `$procdff$16035' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[17]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7910'. |
| created $dff cell `$procdff$16036' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[16]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7904'. |
| created $dff cell `$procdff$16037' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[15]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7898'. |
| created $dff cell `$procdff$16038' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[14]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7892'. |
| created $dff cell `$procdff$16039' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[13]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7886'. |
| created $dff cell `$procdff$16040' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[12]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7880'. |
| created $dff cell `$procdff$16041' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[11]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7874'. |
| created $dff cell `$procdff$16042' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[10]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7868'. |
| created $dff cell `$procdff$16043' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[9]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7862'. |
| created $dff cell `$procdff$16044' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[8]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7856'. |
| created $dff cell `$procdff$16045' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[7]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7850'. |
| created $dff cell `$procdff$16046' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[6]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7844'. |
| created $dff cell `$procdff$16047' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[5]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7838'. |
| created $dff cell `$procdff$16048' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[4]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7832'. |
| created $dff cell `$procdff$16049' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[3]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7826'. |
| created $dff cell `$procdff$16050' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[2]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7820'. |
| created $dff cell `$procdff$16051' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[1]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7814'. |
| created $dff cell `$procdff$16052' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[0]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7808'. |
| created $dff cell `$procdff$16053' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\mgmt_gpio_outr [37:32]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:245$7802'. |
| created $dff cell `$procdff$16054' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\mgmt_gpio_outr [31:0]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:245$7796'. |
| created $dff cell `$procdff$16055' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_clock' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:299$7572'. |
| created $adff cell `$procdff$16056' with positive edge clock and negative level reset. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_resetn' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:299$7572'. |
| created $adff cell `$procdff$16057' with positive edge clock and negative level reset. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_count' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:299$7572'. |
| created $adff cell `$procdff$16058' with positive edge clock and negative level reset. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\pad_count' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:299$7572'. |
| created $adff cell `$procdff$16059' with positive edge clock and negative level reset. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_state' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:299$7572'. |
| created $adff cell `$procdff$16060' with positive edge clock and negative level reset. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_data_staging' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:299$7572'. |
| created $dff cell `$procdff$16061' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$7549_ADDR' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:299$7572'. |
| created $adff cell `$procdff$16062' with positive edge clock and negative level reset. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$7549_DATA' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:299$7572'. |
| created $adff cell `$procdff$16063' with positive edge clock and negative level reset. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\pwr_ctrl_out' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:223$7565'. |
| created $dff cell `$procdff$16064' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_ctrl' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:223$7565'. |
| created $dff cell `$procdff$16065' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_rdata' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:205$7559'. |
| created $dff cell `$procdff$16066' with positive edge clock. |
| Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_ready' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:205$7559'. |
| created $dff cell `$procdff$16067' with positive edge clock. |
| Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\mem_ready' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$5947'. |
| created $dff cell `$procdff$16068' with positive edge clock. |
| Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\mem_rdata' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$5947'. |
| created $dff cell `$procdff$16069' with positive edge clock. |
| Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_adr_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$5947'. |
| created $dff cell `$procdff$16070' with positive edge clock. |
| Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_dat_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$5947'. |
| created $dff cell `$procdff$16071' with positive edge clock. |
| Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_we_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$5947'. |
| created $dff cell `$procdff$16072' with positive edge clock. |
| Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_sel_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$5947'. |
| created $dff cell `$procdff$16073' with positive edge clock. |
| Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_stb_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$5947'. |
| created $dff cell `$procdff$16074' with positive edge clock. |
| Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_cyc_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$5947'. |
| created $dff cell `$procdff$16075' with positive edge clock. |
| Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\state' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$5947'. |
| created $dff cell `$procdff$16076' with positive edge clock. |
| Creating register for signal `\mem_wb.\wb_ack_o' using process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:41$2751'. |
| created $dff cell `$procdff$16077' with positive edge clock. |
| Creating register for signal `\mem_wb.\wb_ack_read' using process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:41$2751'. |
| created $dff cell `$procdff$16078' with positive edge clock. |
| Creating register for signal `\counter_timer_low.\irq_out' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:185$2114'. |
| created $adff cell `$procdff$16079' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_low.\strobe' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:185$2114'. |
| created $adff cell `$procdff$16080' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_low.\stop_out' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:185$2114'. |
| created $adff cell `$procdff$16081' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_low.\value_cur' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:185$2114'. |
| created $adff cell `$procdff$16082' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_low.\lastenable' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:185$2114'. |
| created $adff cell `$procdff$16083' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_low.\value_reset' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:153$2104'. |
| created $adff cell `$procdff$16084' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_low.\enable' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:131$2102'. |
| created $adff cell `$procdff$16085' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_low.\oneshot' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:131$2102'. |
| created $adff cell `$procdff$16086' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_low.\updown' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:131$2102'. |
| created $adff cell `$procdff$16087' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_low.\irq_ena' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:131$2102'. |
| created $adff cell `$procdff$16088' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_low.\chain' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:131$2102'. |
| created $adff cell `$procdff$16089' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_high.\irq_out' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:179$2053'. |
| created $adff cell `$procdff$16090' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_high.\stop_out' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:179$2053'. |
| created $adff cell `$procdff$16091' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_high.\value_cur' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:179$2053'. |
| created $adff cell `$procdff$16092' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_high.\lastenable' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:179$2053'. |
| created $adff cell `$procdff$16093' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_high.\value_reset' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:151$2045'. |
| created $adff cell `$procdff$16094' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_high.\enable' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:129$2043'. |
| created $adff cell `$procdff$16095' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_high.\oneshot' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:129$2043'. |
| created $adff cell `$procdff$16096' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_high.\updown' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:129$2043'. |
| created $adff cell `$procdff$16097' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_high.\irq_ena' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:129$2043'. |
| created $adff cell `$procdff$16098' with positive edge clock and negative level reset. |
| Creating register for signal `\counter_timer_high.\chain' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:129$2043'. |
| created $adff cell `$procdff$16099' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\isdo' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:351$2008'. |
| created $adff cell `$procdff$16100' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\treg' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:351$2008'. |
| created $adff cell `$procdff$16101' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\rreg' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:351$2008'. |
| created $adff cell `$procdff$16102' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\isck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:338$2002'. |
| created $adff cell `$procdff$16103' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\count' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:319$1996'. |
| created $adff cell `$procdff$16104' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\hsck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:319$1996'. |
| created $adff cell `$procdff$16105' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\state' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:283$1985'. |
| created $adff cell `$procdff$16106' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\done' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:283$1985'. |
| created $adff cell `$procdff$16107' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\icsb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:283$1985'. |
| created $adff cell `$procdff$16108' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\nbit' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:283$1985'. |
| created $adff cell `$procdff$16109' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\err_out' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:239$1968'. |
| created $adff cell `$procdff$16110' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\d_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:239$1968'. |
| created $adff cell `$procdff$16111' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\w_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:239$1968'. |
| created $adff cell `$procdff$16112' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\r_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:239$1968'. |
| created $adff cell `$procdff$16113' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\enable' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:208$1966'. |
| created $adff cell `$procdff$16114' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\prescaler' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:208$1966'. |
| created $adff cell `$procdff$16115' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\invsck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:208$1966'. |
| created $adff cell `$procdff$16116' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\invcsb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:208$1966'. |
| created $adff cell `$procdff$16117' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\mlb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:208$1966'. |
| created $adff cell `$procdff$16118' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\irqena' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:208$1966'. |
| created $adff cell `$procdff$16119' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\stream' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:208$1966'. |
| created $adff cell `$procdff$16120' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\mode' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:208$1966'. |
| created $adff cell `$procdff$16121' with positive edge clock and negative level reset. |
| Creating register for signal `\simple_spi_master.\hkconn' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:208$1966'. |
| created $adff cell `$procdff$16122' with positive edge clock and negative level reset. |
| Creating register for signal `\simpleuart.\send_pattern' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:190$1921'. |
| created $dff cell `$procdff$16123' with positive edge clock. |
| Creating register for signal `\simpleuart.\send_bitcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:190$1921'. |
| created $dff cell `$procdff$16124' with positive edge clock. |
| Creating register for signal `\simpleuart.\send_divcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:190$1921'. |
| created $dff cell `$procdff$16125' with positive edge clock. |
| Creating register for signal `\simpleuart.\send_dummy' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:190$1921'. |
| created $dff cell `$procdff$16126' with positive edge clock. |
| Creating register for signal `\simpleuart.\recv_state' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:147$1911'. |
| created $dff cell `$procdff$16127' with positive edge clock. |
| Creating register for signal `\simpleuart.\recv_divcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:147$1911'. |
| created $dff cell `$procdff$16128' with positive edge clock. |
| Creating register for signal `\simpleuart.\recv_pattern' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:147$1911'. |
| created $dff cell `$procdff$16129' with positive edge clock. |
| Creating register for signal `\simpleuart.\recv_buf_data' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:147$1911'. |
| created $dff cell `$procdff$16130' with positive edge clock. |
| Creating register for signal `\simpleuart.\recv_buf_valid' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:147$1911'. |
| created $dff cell `$procdff$16131' with positive edge clock. |
| Creating register for signal `\simpleuart.\enabled' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:134$1909'. |
| created $dff cell `$procdff$16132' with positive edge clock. |
| Creating register for signal `\simpleuart.\cfg_divider' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:134$1909'. |
| created $dff cell `$procdff$16133' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\flash_csb' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| created $dff cell `$procdff$16134' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\flash_clk' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| created $dff cell `$procdff$16135' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\xfer_dspi' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| created $dff cell `$procdff$16136' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\xfer_ddr' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| created $dff cell `$procdff$16137' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\obuffer' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| created $dff cell `$procdff$16138' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\ibuffer' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| created $dff cell `$procdff$16139' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\count' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| created $dff cell `$procdff$16140' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\dummy_count' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| created $dff cell `$procdff$16141' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\xfer_cont' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| created $dff cell `$procdff$16142' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\xfer_qspi' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| created $dff cell `$procdff$16143' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\xfer_rd' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| created $dff cell `$procdff$16144' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\xfer_tag' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| created $dff cell `$procdff$16145' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\fetch' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| created $dff cell `$procdff$16146' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\last_fetch' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| created $dff cell `$procdff$16147' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\xfer_ddr_q' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:597$1830'. |
| created $dff cell `$procdff$16148' with positive edge clock. |
| Creating register for signal `\spimemio_xfer.\xfer_tag_q' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:597$1830'. |
| created $dff cell `$procdff$16149' with positive edge clock. |
| Creating register for signal `\spimemio.\state' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16150' with positive edge clock. |
| Creating register for signal `\spimemio.\rdata' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16151' with positive edge clock. |
| Creating register for signal `\spimemio.\xfer_resetn' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16152' with positive edge clock. |
| Creating register for signal `\spimemio.\din_valid' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16153' with positive edge clock. |
| Creating register for signal `\spimemio.\din_data' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16154' with positive edge clock. |
| Creating register for signal `\spimemio.\din_tag' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16155' with positive edge clock. |
| Creating register for signal `\spimemio.\din_cont' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16156' with positive edge clock. |
| Creating register for signal `\spimemio.\din_qspi' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16157' with positive edge clock. |
| Creating register for signal `\spimemio.\din_ddr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16158' with positive edge clock. |
| Creating register for signal `\spimemio.\din_rd' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16159' with positive edge clock. |
| Creating register for signal `\spimemio.\buffer' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16160' with positive edge clock. |
| Creating register for signal `\spimemio.\rd_addr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16161' with positive edge clock. |
| Creating register for signal `\spimemio.\rd_valid' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16162' with positive edge clock. |
| Creating register for signal `\spimemio.\rd_wait' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16163' with positive edge clock. |
| Creating register for signal `\spimemio.\rd_inc' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| created $dff cell `$procdff$16164' with positive edge clock. |
| Creating register for signal `\spimemio.\xfer_io0_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:294$1745'. |
| created $dff cell `$procdff$16165' with negative edge clock. |
| Creating register for signal `\spimemio.\xfer_io1_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:294$1745'. |
| created $dff cell `$procdff$16166' with negative edge clock. |
| Creating register for signal `\spimemio.\xfer_io2_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:294$1745'. |
| created $dff cell `$procdff$16167' with negative edge clock. |
| Creating register for signal `\spimemio.\xfer_io3_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:294$1745'. |
| created $dff cell `$procdff$16168' with negative edge clock. |
| Creating register for signal `\spimemio.\softreset' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:242$1741'. |
| created $dff cell `$procdff$16169' with positive edge clock. |
| Creating register for signal `\spimemio.\config_en' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:242$1741'. |
| created $dff cell `$procdff$16170' with positive edge clock. |
| Creating register for signal `\spimemio.\config_ddr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:242$1741'. |
| created $dff cell `$procdff$16171' with positive edge clock. |
| Creating register for signal `\spimemio.\config_qspi' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:242$1741'. |
| created $dff cell `$procdff$16172' with positive edge clock. |
| Creating register for signal `\spimemio.\config_cont' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:242$1741'. |
| created $dff cell `$procdff$16173' with positive edge clock. |
| Creating register for signal `\spimemio.\config_dummy' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:242$1741'. |
| created $dff cell `$procdff$16174' with positive edge clock. |
| Creating register for signal `\spimemio.\config_oe' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:242$1741'. |
| created $dff cell `$procdff$16175' with positive edge clock. |
| Creating register for signal `\spimemio.\config_csb' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:242$1741'. |
| created $dff cell `$procdff$16176' with positive edge clock. |
| Creating register for signal `\spimemio.\config_clk' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:242$1741'. |
| created $dff cell `$procdff$16177' with positive edge clock. |
| Creating register for signal `\spimemio.\config_do' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:242$1741'. |
| created $dff cell `$procdff$16178' with positive edge clock. |
| Creating register for signal `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.\wb_ack_o' using process `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:64$5299'. |
| created $dff cell `$procdff$16179' with positive edge clock. |
| Creating register for signal `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.\wb_ack_read' using process `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:64$5299'. |
| created $dff cell `$procdff$16180' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\pcpi_wr' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1661'. |
| created $dff cell `$procdff$16181' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\pcpi_rd' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1661'. |
| created $dff cell `$procdff$16182' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\pcpi_ready' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1661'. |
| created $dff cell `$procdff$16183' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\dividend' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1661'. |
| created $dff cell `$procdff$16184' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\divisor' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1661'. |
| created $dff cell `$procdff$16185' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\quotient' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1661'. |
| created $dff cell `$procdff$16186' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\quotient_msk' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1661'. |
| created $dff cell `$procdff$16187' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\running' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1661'. |
| created $dff cell `$procdff$16188' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\outsign' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1661'. |
| created $dff cell `$procdff$16189' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\pcpi_wait' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1651'. |
| created $dff cell `$procdff$16190' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\pcpi_wait_q' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1651'. |
| created $dff cell `$procdff$16191' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\instr_div' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1651'. |
| created $dff cell `$procdff$16192' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\instr_divu' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1651'. |
| created $dff cell `$procdff$16193' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\instr_rem' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1651'. |
| created $dff cell `$procdff$16194' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_div.\instr_remu' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1651'. |
| created $dff cell `$procdff$16195' with positive edge clock. |
| Creating register for signal `$paramod\clock_div\SIZE=3.\syncN' using process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:29$3640'. |
| created $adff cell `$procdff$16196' with positive edge clock and negative level reset. |
| Creating register for signal `$paramod\clock_div\SIZE=3.\syncNp' using process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:29$3640'. |
| created $adff cell `$procdff$16197' with positive edge clock and negative level reset. |
| Creating register for signal `\picorv32_pcpi_mul.\pcpi_wr' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1623'. |
| created $dff cell `$procdff$16198' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\pcpi_rd' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1623'. |
| created $dff cell `$procdff$16199' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\pcpi_ready' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1623'. |
| created $dff cell `$procdff$16200' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\rs1' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1618'. |
| created $dff cell `$procdff$16201' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\rs2' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1618'. |
| created $dff cell `$procdff$16202' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\rd' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1618'. |
| created $dff cell `$procdff$16203' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\rdx' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1618'. |
| created $dff cell `$procdff$16204' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\mul_counter' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1618'. |
| created $dff cell `$procdff$16205' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\mul_waiting' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1618'. |
| created $dff cell `$procdff$16206' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\mul_finish' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1618'. |
| created $dff cell `$procdff$16207' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\pcpi_wait' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$1574'. |
| created $dff cell `$procdff$16208' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\instr_mul' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$1574'. |
| created $dff cell `$procdff$16209' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\instr_mulh' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$1574'. |
| created $dff cell `$procdff$16210' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\instr_mulhsu' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$1574'. |
| created $dff cell `$procdff$16211' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\instr_mulhu' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$1574'. |
| created $dff cell `$procdff$16212' with positive edge clock. |
| Creating register for signal `\picorv32_pcpi_mul.\pcpi_wait_q' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$1574'. |
| created $dff cell `$procdff$16213' with positive edge clock. |
| Creating register for signal `\housekeeping_spi_slave.\pass_thru_mgmt' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| created $adff cell `$procdff$16214' with positive edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\state' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| created $adff cell `$procdff$16215' with positive edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\addr' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| created $adff cell `$procdff$16216' with positive edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\count' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| created $adff cell `$procdff$16217' with positive edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\rdstb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| created $adff cell `$procdff$16218' with positive edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\pass_thru_mgmt_delay' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| created $adff cell `$procdff$16219' with positive edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\pass_thru_user' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| created $adff cell `$procdff$16220' with positive edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\pass_thru_user_delay' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| created $adff cell `$procdff$16221' with positive edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\writemode' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| created $adff cell `$procdff$16222' with positive edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\readmode' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| created $adff cell `$procdff$16223' with positive edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\fixed' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| created $adff cell `$procdff$16224' with positive edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\predata' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| created $adff cell `$procdff$16225' with positive edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\pre_pass_thru_mgmt' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| created $adff cell `$procdff$16226' with positive edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\pre_pass_thru_user' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| created $adff cell `$procdff$16227' with positive edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\sdoenb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:356$3596'. |
| created $adff cell `$procdff$16228' with negative edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\wrstb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:356$3596'. |
| created $adff cell `$procdff$16229' with negative edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi_slave.\ldata' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:356$3596'. |
| created $adff cell `$procdff$16230' with negative edge clock and positive level reset. |
| Creating register for signal `\housekeeping_spi.\pll_dco_ena' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:197$3589'. |
| created $adff cell `$procdff$16231' with positive edge clock and negative level reset. |
| Creating register for signal `\housekeeping_spi.\pll_sel' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:197$3589'. |
| created $adff cell `$procdff$16232' with positive edge clock and negative level reset. |
| Creating register for signal `\housekeeping_spi.\pll90_sel' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:197$3589'. |
| created $adff cell `$procdff$16233' with positive edge clock and negative level reset. |
| Creating register for signal `\housekeeping_spi.\pll_div' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:197$3589'. |
| created $adff cell `$procdff$16234' with positive edge clock and negative level reset. |
| Creating register for signal `\housekeeping_spi.\pll_ena' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:197$3589'. |
| created $adff cell `$procdff$16235' with positive edge clock and negative level reset. |
| Creating register for signal `\housekeeping_spi.\pll_trim' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:197$3589'. |
| created $adff cell `$procdff$16236' with positive edge clock and negative level reset. |
| Creating register for signal `\housekeeping_spi.\pll_bypass' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:197$3589'. |
| created $adff cell `$procdff$16237' with positive edge clock and negative level reset. |
| Creating register for signal `\housekeeping_spi.\irq' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:197$3589'. |
| created $adff cell `$procdff$16238' with positive edge clock and negative level reset. |
| Creating register for signal `\housekeeping_spi.\reset_reg' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:197$3589'. |
| created $adff cell `$procdff$16239' with positive edge clock and negative level reset. |
| Creating register for signal `\caravel_clocking.\reset_delay' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:81$858'. |
| created $adff cell `$procdff$16240' with positive edge clock and negative level reset. |
| Creating register for signal `\caravel_clocking.\use_pll_first' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:32$853'. |
| created $adff cell `$procdff$16241' with positive edge clock and negative level reset. |
| Creating register for signal `\caravel_clocking.\use_pll_second' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:32$853'. |
| created $adff cell `$procdff$16242' with positive edge clock and negative level reset. |
| Creating register for signal `\caravel_clocking.\ext_clk_syncd_pre' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:32$853'. |
| created $dff cell `$procdff$16243' with positive edge clock. |
| Creating register for signal `\caravel_clocking.\ext_clk_syncd' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:32$853'. |
| created $adff cell `$procdff$16244' with positive edge clock and negative level reset. |
| Creating register for signal `\even.\counter' using process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:176$847'. |
| created $adff cell `$procdff$16245' with positive edge clock and negative level reset. |
| Creating register for signal `\even.\out_counter' using process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:176$847'. |
| created $adff cell `$procdff$16246' with positive edge clock and negative level reset. |
| Creating register for signal `\odd.\old_N' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:145$842'. |
| created $dff cell `$procdff$16247' with positive edge clock. |
| Creating register for signal `\odd.\rst_pulse' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:132$839'. |
| created $adff cell `$procdff$16248' with positive edge clock and negative level reset. |
| Creating register for signal `\odd.\counter2' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:94$831'. |
| Warning: Async reset value `\N' is not constant! |
| created $dffsr cell `$procdff$16249' with negative edge clock and negative level non-const reset. |
| Creating register for signal `\odd.\out_counter2' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:94$831'. |
| created $adff cell `$procdff$16256' with negative edge clock and negative level reset. |
| Creating register for signal `\odd.\initial_begin' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:94$831'. |
| Warning: Async reset value `$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:90$830_Y [3:1]' is not constant! |
| created $dffsr cell `$procdff$16257' with negative edge clock and negative level non-const reset. |
| Creating register for signal `\odd.\counter' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:71$825'. |
| Warning: Async reset value `\N' is not constant! |
| created $dffsr cell `$procdff$16264' with positive edge clock and negative level non-const reset. |
| Creating register for signal `\odd.\out_counter' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:71$825'. |
| created $adff cell `$procdff$16271' with positive edge clock and negative level reset. |
| Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_ADDR' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:854$3528'. |
| created $dff cell `$procdff$16272' with positive edge clock. |
| Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_DATA' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:854$3528'. |
| created $dff cell `$procdff$16273' with positive edge clock. |
| Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:854$3528'. |
| created $dff cell `$procdff$16274' with positive edge clock. |
| |
| 12.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Found and cleaned up 61 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$8551'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$8537'. |
| Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$8523'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$8523'. |
| Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$8518'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$8518'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$8517'. |
| Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$8495'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$8495'. |
| Found and cleaned up 8 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$8483'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$8483'. |
| Found and cleaned up 22 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$8223'. |
| Found and cleaned up 3 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$8221'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$8221'. |
| Found and cleaned up 5 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$8217'. |
| Found and cleaned up 47 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$8216'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$8216'. |
| Found and cleaned up 16 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$8192'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$8192'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$8731'. |
| Found and cleaned up 19 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$8154'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$8154'. |
| Found and cleaned up 3 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$8151'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$8151'. |
| Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$8146'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$8146'. |
| Found and cleaned up 1 empty switch in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$8072'. |
| Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$8072'. |
| Found and cleaned up 42 empty switches in `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:125$8045'. |
| Removing empty process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:125$8045'. |
| Found and cleaned up 9 empty switches in `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:118$6633'. |
| Removing empty process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:118$6633'. |
| Found and cleaned up 10 empty switches in `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:106$6623'. |
| Removing empty process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:106$6623'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$8036'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8030'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8030'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8024'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8024'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8018'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8018'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8012'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8012'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8006'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8006'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8000'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$8000'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7994'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7994'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7988'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7988'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7982'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7982'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7976'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7976'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7970'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7970'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7964'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7964'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7958'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7958'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7952'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7952'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7946'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7946'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7940'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7940'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7934'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7934'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7928'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7928'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7922'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7922'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7916'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7916'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7910'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7910'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7904'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7904'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7898'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7898'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7892'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7892'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7886'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7886'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7880'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7880'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7874'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7874'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7868'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7868'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7862'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7862'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7856'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7856'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7850'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7850'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7844'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7844'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7838'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7838'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7832'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7832'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7826'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7826'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7820'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7820'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7814'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7814'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7808'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:262$7808'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:245$7802'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:245$7802'. |
| Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:245$7796'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:245$7796'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7792'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7787'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7782'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7777'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7772'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7767'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7762'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7757'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7752'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7747'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7742'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7737'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7732'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7727'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7722'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7717'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7712'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7707'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7702'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7697'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7692'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7687'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7682'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7677'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7672'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7667'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7662'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7657'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7652'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7647'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7642'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7637'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7632'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7627'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7622'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7617'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7612'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7607'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7602'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$7600'. |
| Found and cleaned up 13 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:299$7572'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:299$7572'. |
| Found and cleaned up 6 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:223$7565'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:223$7565'. |
| Found and cleaned up 3 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:205$7559'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:205$7559'. |
| Found and cleaned up 43 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:182$7557'. |
| Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:182$7557'. |
| Found and cleaned up 4 empty switches in `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$5947'. |
| Removing empty process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$5947'. |
| Found and cleaned up 1 empty switch in `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:41$2751'. |
| Removing empty process `mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:41$2751'. |
| Found and cleaned up 25 empty switches in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:185$2114'. |
| Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:185$2114'. |
| Found and cleaned up 4 empty switches in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:153$2104'. |
| Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:153$2104'. |
| Found and cleaned up 1 empty switch in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:131$2102'. |
| Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:131$2102'. |
| Found and cleaned up 26 empty switches in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:179$2053'. |
| Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:179$2053'. |
| Found and cleaned up 4 empty switches in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:151$2045'. |
| Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:151$2045'. |
| Found and cleaned up 1 empty switch in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:129$2043'. |
| Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:129$2043'. |
| Found and cleaned up 6 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:351$2008'. |
| Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:351$2008'. |
| Found and cleaned up 1 empty switch in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:338$2002'. |
| Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:338$2002'. |
| Found and cleaned up 2 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:319$1996'. |
| Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:319$1996'. |
| Found and cleaned up 6 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:283$1985'. |
| Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:283$1985'. |
| Found and cleaned up 9 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:239$1968'. |
| Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:239$1968'. |
| Found and cleaned up 2 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:208$1966'. |
| Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:208$1966'. |
| Found and cleaned up 5 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:190$1921'. |
| Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:190$1921'. |
| Found and cleaned up 7 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:147$1911'. |
| Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:147$1911'. |
| Found and cleaned up 6 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:134$1909'. |
| Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:134$1909'. |
| Found and cleaned up 4 empty switches in `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:696$1863'. |
| Found and cleaned up 5 empty switches in `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:608$1839'. |
| Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:597$1830'. |
| Found and cleaned up 25 empty switches in `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:368$1809'. |
| Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:294$1745'. |
| Found and cleaned up 5 empty switches in `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:242$1741'. |
| Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:242$1741'. |
| Removing empty process `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:111$5444'. |
| Removing empty process `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:100$5313'. |
| Found and cleaned up 1 empty switch in `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:64$5299'. |
| Removing empty process `$paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:64$5299'. |
| Removing empty process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:51$4107'. |
| Found and cleaned up 5 empty switches in `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1661'. |
| Removing empty process `picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1661'. |
| Found and cleaned up 2 empty switches in `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1651'. |
| Removing empty process `picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1651'. |
| Removing empty process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:29$3640'. |
| Found and cleaned up 1 empty switch in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1623'. |
| Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1623'. |
| Found and cleaned up 5 empty switches in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1618'. |
| Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1618'. |
| Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$1580'. |
| Found and cleaned up 2 empty switches in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$1574'. |
| Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$1574'. |
| Found and cleaned up 18 empty switches in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| Removing empty process `housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:398$3606'. |
| Found and cleaned up 6 empty switches in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:356$3596'. |
| Removing empty process `housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:356$3596'. |
| Found and cleaned up 2 empty switches in `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:197$3589'. |
| Removing empty process `housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:197$3589'. |
| Removing empty process `caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:81$858'. |
| Removing empty process `caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:32$853'. |
| Found and cleaned up 2 empty switches in `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:176$847'. |
| Removing empty process `even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:176$847'. |
| Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:145$842'. |
| Found and cleaned up 2 empty switches in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:132$839'. |
| Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:132$839'. |
| Found and cleaned up 4 empty switches in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:94$831'. |
| Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:94$831'. |
| Found and cleaned up 3 empty switches in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:71$825'. |
| Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:71$825'. |
| Found and cleaned up 1 empty switch in `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:854$3528'. |
| Removing empty process `mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:854$3528'. |
| Removing empty process `mgmt_soc.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:333$3521'. |
| Cleaned up 682 empty switches. |
| |
| 12.3. Executing FLATTEN pass (flatten design). |
| Deleting now unused module convert_gpio_sigs. |
| Deleting now unused module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32. |
| Deleting now unused module $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la. |
| Deleting now unused module $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl. |
| Deleting now unused module $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio. |
| Deleting now unused module $paramod\soc_mem\WORDS=256\ADR_WIDTH=8. |
| Deleting now unused module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl. |
| Deleting now unused module $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb. |
| Deleting now unused module $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100. |
| Deleting now unused module $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100. |
| Deleting now unused module mem_wb. |
| Deleting now unused module $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb. |
| Deleting now unused module counter_timer_low. |
| Deleting now unused module $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb. |
| Deleting now unused module counter_timer_high. |
| Deleting now unused module $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb. |
| Deleting now unused module simple_spi_master. |
| Deleting now unused module $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb. |
| Deleting now unused module simpleuart. |
| Deleting now unused module $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb. |
| Deleting now unused module spimemio_xfer. |
| Deleting now unused module spimemio. |
| Deleting now unused module spimemio_wb. |
| Deleting now unused module $paramod\mprj_ctrl_wb\BASE_ADR=637534208. |
| Deleting now unused module $paramod$347a36486d64107f427bd280f21732711140bf7c\storage_bridge_wb. |
| Deleting now unused module $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon. |
| Deleting now unused module picorv32_pcpi_div. |
| Deleting now unused module $paramod\clock_div\SIZE=3. |
| Deleting now unused module picorv32_pcpi_mul. |
| Deleting now unused module housekeeping_spi_slave. |
| Deleting now unused module housekeeping_spi. |
| Deleting now unused module caravel_clocking. |
| Deleting now unused module even. |
| Deleting now unused module odd. |
| Deleting now unused module mgmt_soc_regs. |
| Deleting now unused module mgmt_soc. |
| <suppressed ~37 debug messages> |
| |
| 12.4. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~1078 debug messages> |
| |
| 12.5. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 397 unused cells and 4500 unused wires. |
| <suppressed ~516 debug messages> |
| |
| 12.6. Executing CHECK pass (checking for obvious problems). |
| checking module mgmt_core.. |
| Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.sck: |
| port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7630 ($mux) |
| port Y[0] of cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:191$1957 ($mux) |
| Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.csb: |
| port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7625 ($mux) |
| port Y[0] of cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:190$1953 ($mux) |
| Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.sdo: |
| port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7620 ($mux) |
| port Y[0] of cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:196$1959 ($mux) |
| Warning: multiple conflicting drivers for mgmt_core.\housekeeping.pass_thru_user_sdi: |
| port Y[0] of cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:134$3546 ($mux) |
| port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7660 ($mux) |
| Warning: multiple conflicting drivers for mgmt_core.\housekeeping.pass_thru_user_sck: |
| port Y[0] of cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:133$3544 ($mux) |
| port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7655 ($mux) |
| Warning: multiple conflicting drivers for mgmt_core.\housekeeping.pass_thru_user_csb: |
| port Y[0] of cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:132$3542 ($mux) |
| port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:159$7650 ($mux) |
| Warning: Wire mgmt_core.\pwr_ctrl_out [3] is used but has no driver. |
| Warning: Wire mgmt_core.\pwr_ctrl_out [2] is used but has no driver. |
| Warning: Wire mgmt_core.\pwr_ctrl_out [1] is used but has no driver. |
| Warning: Wire mgmt_core.\pwr_ctrl_out [0] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [31] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [30] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [29] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [28] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [27] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [26] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [25] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [24] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [23] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [22] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [21] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [20] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [19] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [18] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [17] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [16] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [15] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [14] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [13] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [12] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [11] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [10] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [9] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [8] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [7] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [6] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [5] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [4] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [3] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [2] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [1] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [0] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.intercon.wbs_dat_i [387] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.intercon.wbs_dat_i [386] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.cpu.picorv32_core.irq [4] is used but has no driver. |
| found and reported 45 problems. |
| |
| 12.7. Executing OPT pass (performing simple optimizations). |
| |
| 12.7.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| |
| 12.7.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| <suppressed ~2433 debug messages> |
| Removed a total of 811 cells. |
| |
| 12.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Replacing known input bits on port A of cell $flatten\housekeeping.\U1.$procmux$15385: \housekeeping.U1.pre_pass_thru_user -> 1'0 |
| Replacing known input bits on port A of cell $flatten\housekeeping.\U1.$procmux$15411: \housekeeping.U1.pre_pass_thru_mgmt -> 1'0 |
| Replacing known input bits on port A of cell $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15303: \soc.cpu.picorv32_core.pcpi_mul.mul_waiting -> 1'0 |
| Analyzing evaluation results. |
| dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10010. |
| dead port 2/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10014. |
| dead port 7/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10014. |
| dead port 8/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10014. |
| dead port 2/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10198. |
| dead port 7/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10198. |
| dead port 8/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10198. |
| dead port 4/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10248. |
| dead port 5/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10248. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10389. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10398. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$11544. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$11551. |
| dead port 3/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$11577. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8746. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8756. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8758. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8764. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8771. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8773. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8779. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8788. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8808. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8814. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8817. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8830. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8837. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8840. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8853. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8865. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8868. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8877. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8880. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8888. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8890. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8893. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8907. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8909. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8911. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8914. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8927. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8929. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8932. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8944. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8947. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8954. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8956. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8959. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8982. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8984. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8986. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8989. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9011. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9013. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9016. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9035. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9037. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9040. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9059. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9061. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9064. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9085. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9088. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9102. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9105. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9107. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9109. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9112. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9122. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9127. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9130. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9153. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9156. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9158. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9160. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9163. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9175. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9178. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9221. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9234. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9247. |
| dead port 4/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9477. |
| dead port 5/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9477. |
| dead port 2/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9520. |
| dead port 7/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9520. |
| dead port 8/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9520. |
| dead port 4/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9727. |
| dead port 5/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9727. |
| dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9795. |
| dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9810. |
| dead port 2/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9814. |
| dead port 7/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9814. |
| dead port 8/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9814. |
| dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9998. |
| dead port 2/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12848. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12851. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13023. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13026. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13029. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13035. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13038. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13041. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13047. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13050. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13053. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13059. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13062. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13065. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13071. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13074. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13077. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13083. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13086. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13089. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13095. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13098. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13101. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13107. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13110. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13113. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13119. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13122. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13125. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13131. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13134. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13137. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13143. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13146. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13149. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13155. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13158. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13161. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13167. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13170. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13173. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13179. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13182. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13185. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13191. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13194. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13197. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13203. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13206. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13209. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13215. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13218. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13221. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13227. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13230. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13233. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13239. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13242. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13245. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13251. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13254. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13257. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13263. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13266. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13269. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13275. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13278. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13281. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13287. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13290. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13293. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13299. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13302. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13305. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13311. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13314. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13317. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13323. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13326. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13329. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13335. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13338. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13341. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13347. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13350. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13353. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13359. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13362. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13365. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13371. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13374. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13377. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13383. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13386. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13389. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13395. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13398. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13401. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13407. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13410. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13413. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13419. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13422. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13425. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13431. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13434. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13437. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13443. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13446. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13449. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13455. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13458. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13461. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13467. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13470. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13473. |
| dead port 2/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13479. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13482. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13485. |
| dead port 2/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13491. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13494. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13497. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13512. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13515. |
| dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13521. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14622. |
| dead port 1/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14624. |
| dead port 2/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14624. |
| dead port 3/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14624. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14628. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14635. |
| dead port 1/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14637. |
| dead port 2/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14637. |
| dead port 3/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14637. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14641. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14661. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14663. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14672. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14674. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14696. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14698. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14708. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14710. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14720. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14730. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14740. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14750. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14760. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14770. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14778. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14786. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14796. |
| dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14822. |
| Removed 247 multiplexer ports. |
| <suppressed ~580 debug messages> |
| |
| 12.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| New input vector for $reduce_or cell $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:329$8080: { \soc.cpu.picorv32_core.pcpi_mul.pcpi_ready \soc.cpu.picorv32_core.pcpi_div.pcpi_ready } |
| New input vector for $reduce_or cell $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:328$8076: { \soc.cpu.picorv32_core.pcpi_mul.pcpi_wait \soc.cpu.picorv32_core.pcpi_div.pcpi_wait } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10014: { \soc.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$16278 $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$8637_Y $auto$opt_reduce.cc:134:opt_mux$16276 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10198: { \soc.cpu.picorv32_core.is_lui_auipc_jal $auto$opt_reduce.cc:134:opt_mux$16280 $flatten\soc.\cpu.\picorv32_core.$procmux$10015_CTRL } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10248: { \soc.cpu.picorv32_core.is_lui_auipc_jal $auto$opt_reduce.cc:134:opt_mux$16282 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10384: $auto$opt_reduce.cc:134:opt_mux$16284 |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10474: { $flatten\soc.\cpu.\picorv32_core.$procmux$10471_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10489_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10467_CMP $auto$opt_reduce.cc:134:opt_mux$16286 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10492: $auto$opt_reduce.cc:134:opt_mux$16288 |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10560: { $flatten\soc.\cpu.\picorv32_core.$procmux$10471_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10489_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10467_CMP $auto$opt_reduce.cc:134:opt_mux$16290 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10578: { $flatten\soc.\cpu.\picorv32_core.$procmux$10471_CMP $auto$opt_reduce.cc:134:opt_mux$16292 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10626: { $auto$opt_reduce.cc:134:opt_mux$16294 $flatten\soc.\cpu.\picorv32_core.$procmux$10489_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10467_CMP } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10647: $auto$opt_reduce.cc:134:opt_mux$16296 |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10768: { $flatten\soc.\cpu.\picorv32_core.$procmux$10776_CMP $auto$opt_reduce.cc:134:opt_mux$16298 $flatten\soc.\cpu.\picorv32_core.$procmux$10489_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10467_CMP } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10780: $auto$opt_reduce.cc:134:opt_mux$16300 |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10936: $auto$opt_reduce.cc:134:opt_mux$16302 |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11323: { $flatten\soc.\cpu.\picorv32_core.$procmux$10467_CMP $auto$opt_reduce.cc:134:opt_mux$16304 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11338: { $flatten\soc.\cpu.\picorv32_core.$procmux$10467_CMP $auto$opt_reduce.cc:134:opt_mux$16306 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11356: $auto$opt_reduce.cc:134:opt_mux$16308 |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11369: $auto$opt_reduce.cc:134:opt_mux$16310 |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11394: { $auto$opt_reduce.cc:134:opt_mux$16312 $flatten\soc.\cpu.\picorv32_core.$procmux$10489_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10467_CMP } |
| New ctrl vector for $mux cell $flatten\housekeeping.\U1.$procmux$15385: { } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11429: { $flatten\soc.\cpu.\picorv32_core.$procmux$10471_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10467_CMP $auto$opt_reduce.cc:134:opt_mux$16314 } |
| New ctrl vector for $mux cell $flatten\housekeeping.\U1.$procmux$15411: { } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11444: { $flatten\soc.\cpu.\picorv32_core.$procmux$10489_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10467_CMP $auto$opt_reduce.cc:134:opt_mux$16316 $flatten\soc.\cpu.\picorv32_core.$procmux$10475_CMP } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11471: { $flatten\soc.\cpu.\picorv32_core.$procmux$10471_CMP $auto$opt_reduce.cc:134:opt_mux$16318 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11484: $auto$opt_reduce.cc:134:opt_mux$16320 |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11510: { $auto$opt_reduce.cc:134:opt_mux$16324 $flatten\soc.\cpu.\picorv32_core.$procmux$10489_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10467_CMP $auto$opt_reduce.cc:134:opt_mux$16322 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11529: { $flatten\soc.\cpu.\picorv32_core.$procmux$10471_CMP $auto$opt_reduce.cc:134:opt_mux$16326 } |
| New ctrl vector for $mux cell $flatten\housekeeping.\U1.$procmux$15550: { } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8798: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y $auto$opt_reduce.cc:134:opt_mux$16328 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8820: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10029_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10005_CMP $auto$opt_reduce.cc:134:opt_mux$16330 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8843: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y $auto$opt_reduce.cc:134:opt_mux$16332 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9211: { $flatten\soc.\cpu.\picorv32_core.$procmux$10104_CMP $auto$opt_reduce.cc:134:opt_mux$16334 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9224: { $auto$opt_reduce.cc:134:opt_mux$16336 $flatten\soc.\cpu.\picorv32_core.$procmux$10093_CMP } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9237: { $flatten\soc.\cpu.\picorv32_core.$procmux$8802_CMP $auto$opt_reduce.cc:134:opt_mux$16338 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9520: $auto$opt_reduce.cc:134:opt_mux$16340 |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9564: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y $flatten\soc.\cpu.\picorv32_core.$procmux$8802_CMP } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9704: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10029_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10005_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$8802_CMP $auto$opt_reduce.cc:134:opt_mux$16342 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9727: { \soc.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$16344 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9814: { \soc.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$16348 $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$8637_Y $auto$opt_reduce.cc:134:opt_mux$16346 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9988: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10029_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10005_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10243_CMP } |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.\cpuregs.$procmux$15806: |
| Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 |
| New ports: A=1'0, B=1'1, Y=$flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] |
| New connections: $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [31:1] = { $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN[31:0]$3531 [0] } |
| New ctrl vector for $pmux cell $flatten\soc.\simpleuart.\simpleuart.$procmux$14469: $auto$opt_reduce.cc:134:opt_mux$16350 |
| New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$15029: { $flatten\soc.\spimemio.\spimemio.$procmux$14960_CMP $auto$opt_reduce.cc:134:opt_mux$16352 $flatten\soc.\spimemio.\spimemio.$procmux$14946_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14943_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14940_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14937_CMP } |
| New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14611: $auto$opt_reduce.cc:134:opt_mux$16354 |
| New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14756: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14614_CMP $auto$opt_reduce.cc:134:opt_mux$16356 } |
| New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14766: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14614_CMP $auto$opt_reduce.cc:134:opt_mux$16358 } |
| New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14775: $auto$opt_reduce.cc:134:opt_mux$16360 |
| New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14783: $auto$opt_reduce.cc:134:opt_mux$16362 |
| New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14792: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14614_CMP $auto$opt_reduce.cc:134:opt_mux$16364 } |
| New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14818: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14614_CMP $auto$opt_reduce.cc:134:opt_mux$16366 } |
| New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16275: { \soc.cpu.picorv32_core.is_lui_auipc_jal \soc.cpu.picorv32_core.is_slli_srli_srai \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi } |
| New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16277: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer } |
| New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16279: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$8637_Y } |
| New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16281: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer } |
| New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16339: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer \soc.cpu.picorv32_core.is_lui_auipc_jal \soc.cpu.picorv32_core.is_slli_srli_srai \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$8637_Y } |
| New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16343: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer } |
| New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16345: { \soc.cpu.picorv32_core.is_lui_auipc_jal \soc.cpu.picorv32_core.is_slli_srli_srai \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi } |
| New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16347: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer } |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 59 changes. |
| |
| 12.7.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| <suppressed ~312 debug messages> |
| Removed a total of 104 cells. |
| |
| 12.7.6. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 12.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 0 unused cells and 1133 unused wires. |
| <suppressed ~18 debug messages> |
| |
| 12.7.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| |
| 12.7.9. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 12.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Replacing known input bits on port B of cell $flatten\soc.\cpu.\picorv32_core.$procmux$11582: { \soc.cpu.picorv32_core.pcpi_mul.pcpi_wr \soc.cpu.picorv32_core.pcpi_div.pcpi_wr } -> 2'11 |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~599 debug messages> |
| |
| 12.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10357: $auto$opt_reduce.cc:134:opt_mux$16368 |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10662: $auto$opt_reduce.cc:134:opt_mux$16370 |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11367: { $flatten\soc.\cpu.\picorv32_core.$procmux$10491_CMP $auto$opt_reduce.cc:134:opt_mux$16372 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11582: $auto$opt_reduce.cc:134:opt_mux$16374 |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8820: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y $auto$opt_reduce.cc:134:opt_mux$16376 $auto$opt_reduce.cc:134:opt_mux$16330 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9328: $auto$opt_reduce.cc:134:opt_mux$16378 |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9345: { $flatten\soc.\cpu.\picorv32_core.$procmux$8802_CMP $auto$opt_reduce.cc:134:opt_mux$16380 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9773: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10029_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10005_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$8802_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10243_CMP $auto$opt_reduce.cc:134:opt_mux$16382 } |
| New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$14886: $auto$opt_reduce.cc:134:opt_mux$16384 |
| New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$14936: { $flatten\soc.\spimemio.\spimemio.$procmux$14960_CMP $auto$opt_reduce.cc:134:opt_mux$16386 $flatten\soc.\spimemio.\spimemio.$procmux$14937_CMP } |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 10 changes. |
| |
| 12.7.12. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| <suppressed ~15 debug messages> |
| Removed a total of 5 cells. |
| |
| 12.7.13. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 12.7.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 0 unused cells and 5 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 12.7.15. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| |
| 12.7.16. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 12.7.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$11582. |
| Removed 1 multiplexer ports. |
| <suppressed ~599 debug messages> |
| |
| 12.7.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 0 changes. |
| |
| 12.7.19. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 12.7.20. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 12.7.21. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| |
| 12.7.22. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| |
| 12.7.23. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 12.7.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~599 debug messages> |
| |
| 12.7.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 0 changes. |
| |
| 12.7.26. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 12.7.27. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 12.7.28. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| |
| 12.7.29. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| |
| 12.7.30. Finished OPT passes. (There is nothing left to do.) |
| |
| 12.8. Executing FSM pass (extract and optimize FSM). |
| |
| 12.8.1. Executing FSM_DETECT pass (finding FSMs in design). |
| Not marking mgmt_core.$flatten\soc.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:855$3527_EN as FSM state register: |
| Users of register don't seem to benefit from recoding. |
| Found FSM state register mgmt_core.housekeeping.U1.state. |
| Found FSM state register mgmt_core.soc.cpu.picorv32_core.cpu_state. |
| Not marking mgmt_core.soc.cpu.picorv32_core.irq_state as FSM state register: |
| Users of register don't seem to benefit from recoding. |
| Not marking mgmt_core.soc.cpu.picorv32_core.mem_state as FSM state register: |
| Users of register don't seem to benefit from recoding. |
| Found FSM state register mgmt_core.soc.cpu.picorv32_core.mem_wordsize. |
| Found FSM state register mgmt_core.soc.cpu.state. |
| Not marking mgmt_core.soc.mprj_ctrl.mprj_ctrl.xfer_state as FSM state register: |
| Users of register don't seem to benefit from recoding. |
| Found FSM state register mgmt_core.soc.simple_spi_master_inst.spi_master.state. |
| Not marking mgmt_core.soc.spimemio.spimemio.din_tag as FSM state register: |
| Users of register don't seem to benefit from recoding. |
| Found FSM state register mgmt_core.soc.spimemio.spimemio.state. |
| |
| 12.8.2. Executing FSM_EXTRACT pass (extracting FSM from design). |
| Extracting FSM `\housekeeping.U1.state' from module `\mgmt_core'. |
| found $adff cell for state register: $flatten\housekeeping.\U1.$procdff$16215 |
| root of input selection tree: $flatten\housekeeping.\U1.$0\state[2:0] |
| found reset state: 3'000 (from async reset) |
| found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:417$3608_Y |
| found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:349$3592_Y |
| found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:365$3598_Y |
| found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:381$3601_Y |
| found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:458$3625_Y |
| found state code: 3'010 |
| found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:368$3600_Y |
| found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:422$3611_Y |
| found ctrl input: $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:424$3612_Y |
| found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:426$3613_Y |
| found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:428$3614_Y |
| found ctrl input: \housekeeping.U1.pre_pass_thru_mgmt |
| found ctrl input: \housekeeping.U1.pre_pass_thru_user |
| found state code: 3'001 |
| found state code: 3'100 |
| found state code: 3'101 |
| found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:365$3598_Y |
| found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:388$3603_Y |
| found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:388$3604_Y |
| found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:417$3608_Y |
| found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:349$3592_Y |
| ctrl inputs: { $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:458$3625_Y \housekeeping.U1.pre_pass_thru_mgmt \housekeeping.U1.pre_pass_thru_user $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:368$3600_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:381$3601_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:422$3611_Y $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:424$3612_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:426$3613_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:428$3614_Y } |
| ctrl outputs: { $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:349$3592_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:365$3598_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:388$3603_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:388$3604_Y $flatten\housekeeping.\U1.$0\state[2:0] $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:417$3608_Y } |
| transition: 3'000 9'---000000 -> 3'000 8'00000001 |
| transition: 3'000 9'-00010000 -> 3'001 8'00000011 |
| transition: 3'000 9'-01010000 -> 3'100 8'00001001 |
| transition: 3'000 9'-1-010000 -> 3'101 8'00001011 |
| transition: 3'000 9'---0-0001 -> 3'000 8'00000001 |
| transition: 3'000 9'---0-001- -> 3'000 8'00000001 |
| transition: 3'000 9'---0-01-- -> 3'000 8'00000001 |
| transition: 3'000 9'---0-1--- -> 3'000 8'00000001 |
| transition: 3'000 9'---1----- -> 3'000 8'00000001 |
| transition: 3'100 9'--------- -> 3'100 8'00011000 |
| transition: 3'010 9'----0---- -> 3'010 8'01000100 |
| transition: 3'010 9'0---1---- -> 3'010 8'01000100 |
| transition: 3'010 9'1---1---- -> 3'000 8'01000000 |
| transition: 3'001 9'----0---- -> 3'001 8'10000010 |
| transition: 3'001 9'----1---- -> 3'010 8'10000100 |
| transition: 3'101 9'--------- -> 3'101 8'00101010 |
| Extracting FSM `\soc.cpu.picorv32_core.cpu_state' from module `\mgmt_core'. |
| found $dff cell for state register: $flatten\soc.\cpu.\picorv32_core.$procdff$15872 |
| root of input selection tree: $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1933$8719_Y |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1917$8702_Y |
| found ctrl input: \soc.cpu.wb_rst_i |
| found ctrl input: $auto$opt_reduce.cc:134:opt_mux$16378 |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$10243_CMP |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$8802_CMP |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$10005_CMP |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$10029_CMP |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$8683_Y |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1867$8687_Y |
| found state code: 8'01000000 |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1826$8665_Y |
| found ctrl input: \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu |
| found ctrl input: \soc.cpu.picorv32_core.mem_done |
| found ctrl input: \soc.cpu.picorv32_core.is_sb_sh_sw |
| found ctrl input: \soc.cpu.picorv32_core.instr_trap |
| found state code: 8'00001000 |
| found state code: 8'00000010 |
| found ctrl input: \soc.cpu.picorv32_core.pcpi_int_ready |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1600$8619_Y |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1603$8623_Y |
| found state code: 8'10000000 |
| found ctrl input: $auto$opt_reduce.cc:134:opt_mux$16276 |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$8637_Y |
| found ctrl input: $auto$opt_reduce.cc:134:opt_mux$16278 |
| found state code: 8'00000001 |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1533$8598_Y |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1543$8606_Y |
| found ctrl input: \soc.cpu.picorv32_core.decoder_trigger |
| found ctrl input: \soc.cpu.picorv32_core.instr_jal |
| found state code: 8'00100000 |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$8712_Y |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$8705_Y |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1920$8709_Y |
| found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$10243_CMP |
| found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$10104_CMP |
| found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$10093_CMP |
| found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$10029_CMP |
| found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$10005_CMP |
| found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$8806_CMP |
| found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$8802_CMP |
| found ctrl output: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y |
| ctrl inputs: { $auto$opt_reduce.cc:134:opt_mux$16276 $auto$opt_reduce.cc:134:opt_mux$16278 $auto$opt_reduce.cc:134:opt_mux$16378 \soc.cpu.picorv32_core.pcpi_int_ready \soc.cpu.picorv32_core.mem_done \soc.cpu.picorv32_core.instr_jal \soc.cpu.picorv32_core.instr_trap \soc.cpu.picorv32_core.decoder_trigger \soc.cpu.picorv32_core.is_sb_sh_sw \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1533$8598_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1543$8606_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1600$8619_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1603$8623_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$8637_Y $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1826$8665_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$8683_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1867$8687_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1917$8702_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$8705_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1920$8709_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$8712_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1933$8719_Y \soc.cpu.wb_rst_i } |
| ctrl outputs: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] $flatten\soc.\cpu.\picorv32_core.$procmux$8802_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$8806_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10005_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10029_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10093_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10104_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10243_CMP } |
| transition: 8'10000000 24'------------------0---00 -> 8'10000000 16'0100000000100000 |
| transition: 8'10000000 24'------------------0---01 -> 8'01000000 16'0010000000100000 |
| transition: 8'10000000 24'------------------10-000 -> 8'10000000 16'0100000000100000 |
| transition: 8'10000000 24'------------------10-001 -> 8'01000000 16'0010000000100000 |
| transition: 8'10000000 24'------------------11000- -> 8'10000000 16'0100000000100000 |
| transition: 8'10000000 24'------------------111000 -> 8'10000000 16'0100000000100000 |
| transition: 8'10000000 24'------------------111001 -> 8'01000000 16'0010000000100000 |
| transition: 8'10000000 24'------------------1-010- -> 8'10000000 16'0100000000100000 |
| transition: 8'10000000 24'------------------101100 -> 8'10000000 16'0100000000100000 |
| transition: 8'10000000 24'------------------101101 -> 8'01000000 16'0010000000100000 |
| transition: 8'10000000 24'------------------111100 -> 8'10000000 16'0100000000100000 |
| transition: 8'10000000 24'------------------111101 -> 8'01000000 16'0010000000100000 |
| transition: 8'10000000 24'--------------------0-1- -> 8'10000000 16'0100000000100000 |
| transition: 8'10000000 24'------------------0-1-10 -> 8'10000000 16'0100000000100000 |
| transition: 8'10000000 24'------------------0-1-11 -> 8'01000000 16'0010000000100000 |
| transition: 8'10000000 24'------------------101010 -> 8'10000000 16'0100000000100000 |
| transition: 8'10000000 24'------------------101011 -> 8'01000000 16'0010000000100000 |
| transition: 8'10000000 24'------------------111010 -> 8'10000000 16'0100000000100000 |
| transition: 8'10000000 24'------------------111011 -> 8'01000000 16'0010000000100000 |
| transition: 8'10000000 24'------------------101110 -> 8'10000000 16'0100000000100000 |
| transition: 8'10000000 24'------------------101111 -> 8'01000000 16'0010000000100000 |
| transition: 8'10000000 24'------------------111110 -> 8'10000000 16'0100000000100000 |
| transition: 8'10000000 24'------------------111111 -> 8'01000000 16'0010000000100000 |
| transition: 8'01000000 24'-------0--00------0---00 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-----0-1--00------0---00 -> 8'00100000 16'1001000000000000 |
| transition: 8'01000000 24'-----1-1--00------0---00 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------01------0---00 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------1-------0---00 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'------------------0---01 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-------0--00------10-000 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-----0-1--00------10-000 -> 8'00100000 16'1001000000000000 |
| transition: 8'01000000 24'-----1-1--00------10-000 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------01------10-000 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------1-------10-000 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'------------------10-001 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'------------------11000- -> 8'10000000 16'1100000000000000 |
| transition: 8'01000000 24'-------0--00------111000 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-----0-1--00------111000 -> 8'00100000 16'1001000000000000 |
| transition: 8'01000000 24'-----1-1--00------111000 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------01------111000 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------1-------111000 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'------------------111001 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'------------------1-010- -> 8'10000000 16'1100000000000000 |
| transition: 8'01000000 24'-------0--00------101100 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-----0-1--00------101100 -> 8'00100000 16'1001000000000000 |
| transition: 8'01000000 24'-----1-1--00------101100 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------01------101100 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------1-------101100 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'------------------101101 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-------0--00------111100 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-----0-1--00------111100 -> 8'00100000 16'1001000000000000 |
| transition: 8'01000000 24'-----1-1--00------111100 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------01------111100 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------1-------111100 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'------------------111101 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'--------------------0-1- -> 8'10000000 16'1100000000000000 |
| transition: 8'01000000 24'-------0--00------0-1-10 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-----0-1--00------0-1-10 -> 8'00100000 16'1001000000000000 |
| transition: 8'01000000 24'-----1-1--00------0-1-10 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------01------0-1-10 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------1-------0-1-10 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'------------------0-1-11 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-------0--00------101010 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-----0-1--00------101010 -> 8'00100000 16'1001000000000000 |
| transition: 8'01000000 24'-----1-1--00------101010 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------01------101010 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------1-------101010 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'------------------101011 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-------0--00------111010 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-----0-1--00------111010 -> 8'00100000 16'1001000000000000 |
| transition: 8'01000000 24'-----1-1--00------111010 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------01------111010 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------1-------111010 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'------------------111011 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-------0--00------101110 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-----0-1--00------101110 -> 8'00100000 16'1001000000000000 |
| transition: 8'01000000 24'-----1-1--00------101110 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------01------101110 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------1-------101110 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'------------------101111 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-------0--00------111110 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'-----0-1--00------111110 -> 8'00100000 16'1001000000000000 |
| transition: 8'01000000 24'-----1-1--00------111110 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------01------111110 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'----------1-------111110 -> 8'01000000 16'1010000000000000 |
| transition: 8'01000000 24'------------------111111 -> 8'01000000 16'1010000000000000 |
| transition: 8'00100000 24'00----0-0-----0---0---00 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'00------1-----0---0---00 -> 8'00000010 16'0000000100001000 |
| transition: 8'00100000 24'---0--1-----0-----0---00 -> 8'00100000 16'0001000000001000 |
| transition: 8'00100000 24'---0--1-----10----0---00 -> 8'10000000 16'0100000000001000 |
| transition: 8'00100000 24'---0--1-----11----0---00 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'---1--1-----------0---00 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'-1----------------0---00 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'--------------1---0---00 -> 8'00000001 16'0000000010001000 |
| transition: 8'00100000 24'1-----------------0---00 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'------------------0---01 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'00----0-0-----0---10-000 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'00------1-----0---10-000 -> 8'00000010 16'0000000100001000 |
| transition: 8'00100000 24'---0--1-----0-----10-000 -> 8'00100000 16'0001000000001000 |
| transition: 8'00100000 24'---0--1-----10----10-000 -> 8'10000000 16'0100000000001000 |
| transition: 8'00100000 24'---0--1-----11----10-000 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'---1--1-----------10-000 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'-1----------------10-000 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'--------------1---10-000 -> 8'00000001 16'0000000010001000 |
| transition: 8'00100000 24'1-----------------10-000 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'------------------10-001 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'------------------11000- -> 8'10000000 16'0100000000001000 |
| transition: 8'00100000 24'00----0-0-----0---111000 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'00------1-----0---111000 -> 8'00000010 16'0000000100001000 |
| transition: 8'00100000 24'---0--1-----0-----111000 -> 8'00100000 16'0001000000001000 |
| transition: 8'00100000 24'---0--1-----10----111000 -> 8'10000000 16'0100000000001000 |
| transition: 8'00100000 24'---0--1-----11----111000 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'---1--1-----------111000 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'-1----------------111000 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'--------------1---111000 -> 8'00000001 16'0000000010001000 |
| transition: 8'00100000 24'1-----------------111000 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'------------------111001 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'------------------1-010- -> 8'10000000 16'0100000000001000 |
| transition: 8'00100000 24'00----0-0-----0---101100 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'00------1-----0---101100 -> 8'00000010 16'0000000100001000 |
| transition: 8'00100000 24'---0--1-----0-----101100 -> 8'00100000 16'0001000000001000 |
| transition: 8'00100000 24'---0--1-----10----101100 -> 8'10000000 16'0100000000001000 |
| transition: 8'00100000 24'---0--1-----11----101100 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'---1--1-----------101100 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'-1----------------101100 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'--------------1---101100 -> 8'00000001 16'0000000010001000 |
| transition: 8'00100000 24'1-----------------101100 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'------------------101101 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'00----0-0-----0---111100 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'00------1-----0---111100 -> 8'00000010 16'0000000100001000 |
| transition: 8'00100000 24'---0--1-----0-----111100 -> 8'00100000 16'0001000000001000 |
| transition: 8'00100000 24'---0--1-----10----111100 -> 8'10000000 16'0100000000001000 |
| transition: 8'00100000 24'---0--1-----11----111100 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'---1--1-----------111100 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'-1----------------111100 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'--------------1---111100 -> 8'00000001 16'0000000010001000 |
| transition: 8'00100000 24'1-----------------111100 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'------------------111101 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'--------------------0-1- -> 8'10000000 16'0100000000001000 |
| transition: 8'00100000 24'00----0-0-----0---0-1-10 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'00------1-----0---0-1-10 -> 8'00000010 16'0000000100001000 |
| transition: 8'00100000 24'---0--1-----0-----0-1-10 -> 8'00100000 16'0001000000001000 |
| transition: 8'00100000 24'---0--1-----10----0-1-10 -> 8'10000000 16'0100000000001000 |
| transition: 8'00100000 24'---0--1-----11----0-1-10 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'---1--1-----------0-1-10 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'-1----------------0-1-10 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'--------------1---0-1-10 -> 8'00000001 16'0000000010001000 |
| transition: 8'00100000 24'1-----------------0-1-10 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'------------------0-1-11 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'00----0-0-----0---101010 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'00------1-----0---101010 -> 8'00000010 16'0000000100001000 |
| transition: 8'00100000 24'---0--1-----0-----101010 -> 8'00100000 16'0001000000001000 |
| transition: 8'00100000 24'---0--1-----10----101010 -> 8'10000000 16'0100000000001000 |
| transition: 8'00100000 24'---0--1-----11----101010 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'---1--1-----------101010 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'-1----------------101010 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'--------------1---101010 -> 8'00000001 16'0000000010001000 |
| transition: 8'00100000 24'1-----------------101010 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'------------------101011 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'00----0-0-----0---111010 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'00------1-----0---111010 -> 8'00000010 16'0000000100001000 |
| transition: 8'00100000 24'---0--1-----0-----111010 -> 8'00100000 16'0001000000001000 |
| transition: 8'00100000 24'---0--1-----10----111010 -> 8'10000000 16'0100000000001000 |
| transition: 8'00100000 24'---0--1-----11----111010 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'---1--1-----------111010 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'-1----------------111010 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'--------------1---111010 -> 8'00000001 16'0000000010001000 |
| transition: 8'00100000 24'1-----------------111010 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'------------------111011 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'00----0-0-----0---101110 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'00------1-----0---101110 -> 8'00000010 16'0000000100001000 |
| transition: 8'00100000 24'---0--1-----0-----101110 -> 8'00100000 16'0001000000001000 |
| transition: 8'00100000 24'---0--1-----10----101110 -> 8'10000000 16'0100000000001000 |
| transition: 8'00100000 24'---0--1-----11----101110 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'---1--1-----------101110 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'-1----------------101110 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'--------------1---101110 -> 8'00000001 16'0000000010001000 |
| transition: 8'00100000 24'1-----------------101110 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'------------------101111 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'00----0-0-----0---111110 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'00------1-----0---111110 -> 8'00000010 16'0000000100001000 |
| transition: 8'00100000 24'---0--1-----0-----111110 -> 8'00100000 16'0001000000001000 |
| transition: 8'00100000 24'---0--1-----10----111110 -> 8'10000000 16'0100000000001000 |
| transition: 8'00100000 24'---0--1-----11----111110 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'---1--1-----------111110 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'-1----------------111110 -> 8'01000000 16'0010000000001000 |
| transition: 8'00100000 24'--------------1---111110 -> 8'00000001 16'0000000010001000 |
| transition: 8'00100000 24'1-----------------111110 -> 8'00001000 16'0000010000001000 |
| transition: 8'00100000 24'------------------111111 -> 8'01000000 16'0010000000001000 |
| transition: 8'00001000 24'---------0--------0---00 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'----0----1--------0---00 -> 8'00001000 16'0000010001000000 |
| transition: 8'00001000 24'----1----1--------0---00 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'------------------0---01 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'---------0--------10-000 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'----0----1--------10-000 -> 8'00001000 16'0000010001000000 |
| transition: 8'00001000 24'----1----1--------10-000 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'------------------10-001 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'------------------11000- -> 8'10000000 16'0100000001000000 |
| transition: 8'00001000 24'---------0--------111000 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'----0----1--------111000 -> 8'00001000 16'0000010001000000 |
| transition: 8'00001000 24'----1----1--------111000 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'------------------111001 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'------------------1-010- -> 8'10000000 16'0100000001000000 |
| transition: 8'00001000 24'---------0--------101100 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'----0----1--------101100 -> 8'00001000 16'0000010001000000 |
| transition: 8'00001000 24'----1----1--------101100 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'------------------101101 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'---------0--------111100 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'----0----1--------111100 -> 8'00001000 16'0000010001000000 |
| transition: 8'00001000 24'----1----1--------111100 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'------------------111101 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'--------------------0-1- -> 8'10000000 16'0100000001000000 |
| transition: 8'00001000 24'---------0--------0-1-10 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'----0----1--------0-1-10 -> 8'00001000 16'0000010001000000 |
| transition: 8'00001000 24'----1----1--------0-1-10 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'------------------0-1-11 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'---------0--------101010 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'----0----1--------101010 -> 8'00001000 16'0000010001000000 |
| transition: 8'00001000 24'----1----1--------101010 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'------------------101011 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'---------0--------111010 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'----0----1--------111010 -> 8'00001000 16'0000010001000000 |
| transition: 8'00001000 24'----1----1--------111010 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'------------------111011 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'---------0--------101110 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'----0----1--------101110 -> 8'00001000 16'0000010001000000 |
| transition: 8'00001000 24'----1----1--------101110 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'------------------101111 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'---------0--------111110 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'----0----1--------111110 -> 8'00001000 16'0000010001000000 |
| transition: 8'00001000 24'----1----1--------111110 -> 8'01000000 16'0010000001000000 |
| transition: 8'00001000 24'------------------111111 -> 8'01000000 16'0010000001000000 |
| transition: 8'00000010 24'----------------0-0---00 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------100---00 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------110---00 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'------------------0---01 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'----------------0-10-000 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------1010-000 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------1110-000 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'------------------10-001 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'------------------11000- -> 8'10000000 16'0100000000000010 |
| transition: 8'00000010 24'----------------0-111000 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------10111000 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------11111000 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'------------------111001 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'------------------1-010- -> 8'10000000 16'0100000000000010 |
| transition: 8'00000010 24'----------------0-101100 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------10101100 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------11101100 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'------------------101101 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'----------------0-111100 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------10111100 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------11111100 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'------------------111101 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'--------------------0-1- -> 8'10000000 16'0100000000000010 |
| transition: 8'00000010 24'----------------0-0-1-10 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------100-1-10 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------110-1-10 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'------------------0-1-11 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'----------------0-101010 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------10101010 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------11101010 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'------------------101011 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'----------------0-111010 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------10111010 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------11111010 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'------------------111011 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'----------------0-101110 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------10101110 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------11101110 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'------------------101111 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'----------------0-111110 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------10111110 -> 8'00000010 16'0000000100000010 |
| transition: 8'00000010 24'----------------11111110 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000010 24'------------------111111 -> 8'01000000 16'0010000000000010 |
| transition: 8'00000001 24'----------------0-0---00 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------100---00 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------110---00 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'------------------0---01 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'----------------0-10-000 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------1010-000 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------1110-000 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'------------------10-001 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'------------------11000- -> 8'10000000 16'0100000000000100 |
| transition: 8'00000001 24'----------------0-111000 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------10111000 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------11111000 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'------------------111001 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'------------------1-010- -> 8'10000000 16'0100000000000100 |
| transition: 8'00000001 24'----------------0-101100 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------10101100 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------11101100 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'------------------101101 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'----------------0-111100 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------10111100 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------11111100 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'------------------111101 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'--------------------0-1- -> 8'10000000 16'0100000000000100 |
| transition: 8'00000001 24'----------------0-0-1-10 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------100-1-10 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------110-1-10 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'------------------0-1-11 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'----------------0-101010 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------10101010 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------11101010 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'------------------101011 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'----------------0-111010 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------10111010 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------11111010 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'------------------111011 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'----------------0-101110 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------10101110 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------11101110 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'------------------101111 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'----------------0-111110 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------10111110 -> 8'00000001 16'0000000010000100 |
| transition: 8'00000001 24'----------------11111110 -> 8'01000000 16'0010000000000100 |
| transition: 8'00000001 24'------------------111111 -> 8'01000000 16'0010000000000100 |
| Extracting FSM `\soc.cpu.picorv32_core.mem_wordsize' from module `\mgmt_core'. |
| found $dff cell for state register: $flatten\soc.\cpu.\picorv32_core.$procdff$15859 |
| root of input selection tree: $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0] |
| found ctrl input: \soc.cpu.wb_rst_i |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$10093_CMP |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$10104_CMP |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$8683_Y |
| found ctrl input: \soc.cpu.picorv32_core.mem_do_rdata |
| found ctrl input: \soc.cpu.picorv32_core.instr_lw |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1882$8692_Y |
| found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1881$8691_Y |
| found state code: 2'00 |
| found state code: 2'01 |
| found state code: 2'10 |
| found ctrl input: \soc.cpu.picorv32_core.mem_do_wdata |
| found ctrl input: \soc.cpu.picorv32_core.instr_sw |
| found ctrl input: \soc.cpu.picorv32_core.instr_sh |
| found ctrl input: \soc.cpu.picorv32_core.instr_sb |
| found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$11545_CMP |
| found ctrl output: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$8710_Y |
| found ctrl output: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$8703_Y |
| ctrl inputs: { \soc.cpu.picorv32_core.mem_do_rdata \soc.cpu.picorv32_core.mem_do_wdata \soc.cpu.picorv32_core.instr_lw \soc.cpu.picorv32_core.instr_sb \soc.cpu.picorv32_core.instr_sh \soc.cpu.picorv32_core.instr_sw $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$8683_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1881$8691_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1882$8692_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10093_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10104_CMP \soc.cpu.wb_rst_i } |
| ctrl outputs: { $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0] $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$8703_Y $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$8710_Y $flatten\soc.\cpu.\picorv32_core.$procmux$11545_CMP } |
| transition: 2'00 13'------0---000 -> 2'00 5'00100 |
| transition: 2'00 13'------1-----0 -> 2'00 5'00100 |
| transition: 2'00 13'-------0---10 -> 2'00 5'00100 |
| transition: 2'00 13'-0-000-1---10 -> INVALID_STATE(2'xx) 5'xx100 <ignored invalid transition!> |
| transition: 2'00 13'-0-1---1---10 -> 2'10 5'10100 |
| transition: 2'00 13'-0--1--1---10 -> 2'01 5'01100 |
| transition: 2'00 13'-0---1-1---10 -> 2'00 5'00100 |
| transition: 2'00 13'-1-----1---10 -> 2'00 5'00100 |
| transition: 2'00 13'-------0--1-0 -> 2'00 5'00100 |
| transition: 2'00 13'0-0----1001-0 -> INVALID_STATE(2'xx) 5'xx100 <ignored invalid transition!> |
| transition: 2'00 13'0------11-1-0 -> 2'10 5'10100 |
| transition: 2'00 13'0------1-11-0 -> 2'01 5'01100 |
| transition: 2'00 13'0-1----1--1-0 -> 2'00 5'00100 |
| transition: 2'00 13'1------1--1-0 -> 2'00 5'00100 |
| transition: 2'00 13'------------1 -> 2'00 5'00100 |
| transition: 2'10 13'------0---000 -> 2'10 5'10001 |
| transition: 2'10 13'------1-----0 -> 2'00 5'00001 |
| transition: 2'10 13'-------0---10 -> 2'10 5'10001 |
| transition: 2'10 13'-0-000-1---10 -> INVALID_STATE(2'xx) 5'xx001 <ignored invalid transition!> |
| transition: 2'10 13'-0-1---1---10 -> 2'10 5'10001 |
| transition: 2'10 13'-0--1--1---10 -> 2'01 5'01001 |
| transition: 2'10 13'-0---1-1---10 -> 2'00 5'00001 |
| transition: 2'10 13'-1-----1---10 -> 2'10 5'10001 |
| transition: 2'10 13'-------0--1-0 -> 2'10 5'10001 |
| transition: 2'10 13'0-0----1001-0 -> INVALID_STATE(2'xx) 5'xx001 <ignored invalid transition!> |
| transition: 2'10 13'0------11-1-0 -> 2'10 5'10001 |
| transition: 2'10 13'0------1-11-0 -> 2'01 5'01001 |
| transition: 2'10 13'0-1----1--1-0 -> 2'00 5'00001 |
| transition: 2'10 13'1------1--1-0 -> 2'10 5'10001 |
| transition: 2'10 13'------------1 -> 2'10 5'10001 |
| transition: 2'01 13'------0---000 -> 2'01 5'01010 |
| transition: 2'01 13'------1-----0 -> 2'00 5'00010 |
| transition: 2'01 13'-------0---10 -> 2'01 5'01010 |
| transition: 2'01 13'-0-000-1---10 -> INVALID_STATE(2'xx) 5'xx010 <ignored invalid transition!> |
| transition: 2'01 13'-0-1---1---10 -> 2'10 5'10010 |
| transition: 2'01 13'-0--1--1---10 -> 2'01 5'01010 |
| transition: 2'01 13'-0---1-1---10 -> 2'00 5'00010 |
| transition: 2'01 13'-1-----1---10 -> 2'01 5'01010 |
| transition: 2'01 13'-------0--1-0 -> 2'01 5'01010 |
| transition: 2'01 13'0-0----1001-0 -> INVALID_STATE(2'xx) 5'xx010 <ignored invalid transition!> |
| transition: 2'01 13'0------11-1-0 -> 2'10 5'10010 |
| transition: 2'01 13'0------1-11-0 -> 2'01 5'01010 |
| transition: 2'01 13'0-1----1--1-0 -> 2'00 5'00010 |
| transition: 2'01 13'1------1--1-0 -> 2'01 5'01010 |
| transition: 2'01 13'------------1 -> 2'01 5'01010 |
| Extracting FSM `\soc.cpu.state' from module `\mgmt_core'. |
| found $dff cell for state register: $flatten\soc.\cpu.$procdff$16076 |
| root of input selection tree: $flatten\soc.\cpu.$0\state[1:0] |
| found reset state: 2'00 (guessed from mux tree) |
| found ctrl input: \soc.cpu.wb_rst_i |
| found ctrl input: $flatten\soc.\cpu.$procmux$13540_CMP |
| found ctrl input: $flatten\soc.\cpu.$procmux$13544_CMP |
| found state code: 2'00 |
| found ctrl input: \soc.cpu.wbm_ack_i |
| found state code: 2'10 |
| found ctrl input: \soc.cpu.picorv32_core.mem_valid |
| found state code: 2'01 |
| found ctrl output: $flatten\soc.\cpu.$procmux$13540_CMP |
| found ctrl output: $flatten\soc.\cpu.$procmux$13544_CMP |
| found ctrl output: $flatten\soc.\cpu.$procmux$13631_CMP |
| ctrl inputs: { \soc.cpu.picorv32_core.mem_valid \soc.cpu.wbm_ack_i \soc.cpu.wb_rst_i } |
| ctrl outputs: { $flatten\soc.\cpu.$procmux$13631_CMP $flatten\soc.\cpu.$procmux$13544_CMP $flatten\soc.\cpu.$procmux$13540_CMP $flatten\soc.\cpu.$0\state[1:0] } |
| transition: 2'00 3'0-0 -> 2'00 5'01000 |
| transition: 2'00 3'1-0 -> 2'01 5'01001 |
| transition: 2'00 3'--1 -> 2'00 5'01000 |
| transition: 2'10 3'--0 -> 2'00 5'10000 |
| transition: 2'10 3'--1 -> 2'00 5'10000 |
| transition: 2'01 3'-00 -> 2'01 5'00101 |
| transition: 2'01 3'-10 -> 2'10 5'00110 |
| transition: 2'01 3'--1 -> 2'00 5'00100 |
| Extracting FSM `\soc.simple_spi_master_inst.spi_master.state' from module `\mgmt_core'. |
| found $adff cell for state register: $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16106 |
| root of input selection tree: $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0] |
| found reset state: 2'00 (from async reset) |
| found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:290$1987_Y |
| found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:247$1970_Y |
| found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:247$1971_Y |
| found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:308$1994_Y |
| found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:303$1993_Y |
| found state code: 2'01 |
| found state code: 2'11 |
| found state code: 2'10 |
| found ctrl input: \soc.simple_spi_master_inst.spi_master.w_latched |
| found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:308$1994_Y |
| found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:290$1987_Y |
| found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:247$1971_Y |
| found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:247$1970_Y |
| ctrl inputs: { \soc.simple_spi_master_inst.spi_master.w_latched $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:303$1993_Y } |
| ctrl outputs: { $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:247$1970_Y $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:247$1971_Y $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0] $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:290$1987_Y $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:308$1994_Y } |
| transition: 2'00 2'0- -> 2'00 6'000010 |
| transition: 2'00 2'1- -> 2'01 6'000110 |
| transition: 2'10 2'-0 -> 2'01 6'010100 |
| transition: 2'10 2'-1 -> 2'11 6'011100 |
| transition: 2'01 2'-- -> 2'10 6'101000 |
| transition: 2'11 2'-- -> 2'00 6'000001 |
| Extracting FSM `\soc.spimemio.spimemio.state' from module `\mgmt_core'. |
| found $dff cell for state register: $flatten\soc.\spimemio.\spimemio.$procdff$16150 |
| root of input selection tree: $flatten\soc.\spimemio.\spimemio.$0\state[3:0] |
| found reset state: 4'0000 (guessed from mux tree) |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:372$1811_Y |
| found ctrl input: \soc.spimemio.spimemio.jump |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$14937_CMP |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$14940_CMP |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$14943_CMP |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$14946_CMP |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$14949_CMP |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$14952_CMP |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$14955_CMP |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$14960_CMP |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$14907_CMP |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$14887_CMP |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$14966_CMP |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$14890_CMP |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$14969_CMP |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:511$1829_Y |
| found ctrl input: \soc.spimemio.spimemio.xfer.din_ready |
| found state code: 4'1001 |
| found state code: 4'1100 |
| found state code: 4'1011 |
| found state code: 4'1010 |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:471$1825_Y |
| found state code: 4'1000 |
| found state code: 4'0111 |
| found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:215$1732_Y |
| found state code: 4'0110 |
| found state code: 4'0101 |
| found ctrl input: \soc.spimemio.spimemio.dout_valid |
| found state code: 4'0100 |
| found state code: 4'0011 |
| found state code: 4'0010 |
| found state code: 4'0001 |
| found ctrl input: \soc.spimemio.spimemio.config_cont |
| found state code: 4'0000 |
| found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$14969_CMP |
| found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$14966_CMP |
| found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$14960_CMP |
| found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$14955_CMP |
| found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$14952_CMP |
| found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$14949_CMP |
| found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$14946_CMP |
| found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$14943_CMP |
| found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$14940_CMP |
| found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$14937_CMP |
| found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$14907_CMP |
| found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$14890_CMP |
| found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$14887_CMP |
| ctrl inputs: { \soc.spimemio.spimemio.dout_valid \soc.spimemio.spimemio.jump \soc.spimemio.spimemio.config_cont $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:215$1732_Y $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:372$1811_Y $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:471$1825_Y $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:511$1829_Y \soc.spimemio.spimemio.xfer.din_ready } |
| ctrl outputs: { $flatten\soc.\spimemio.\spimemio.$0\state[3:0] $flatten\soc.\spimemio.\spimemio.$procmux$14887_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14890_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14907_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14937_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14940_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14943_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14946_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14949_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14952_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14955_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14960_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14966_CMP $flatten\soc.\spimemio.\spimemio.$procmux$14969_CMP } |
| transition: 4'0000 8'-0--0--0 -> 4'0000 17'00000000000000001 |
| transition: 4'0000 8'-0--0--1 -> 4'0001 17'00010000000000001 |
| transition: 4'0000 8'-10-0--- -> 4'0100 17'01000000000000001 |
| transition: 4'0000 8'-11-0--- -> 4'0101 17'01010000000000001 |
| transition: 4'0000 8'----1--- -> 4'0000 17'00000000000000001 |
| transition: 4'1000 8'-0--0--0 -> 4'1000 17'10000000000100000 |
| transition: 4'1000 8'-0--0--1 -> 4'1001 17'10010000000100000 |
| transition: 4'1000 8'-10-0--- -> 4'0100 17'01000000000100000 |
| transition: 4'1000 8'-11-0--- -> 4'0101 17'01010000000100000 |
| transition: 4'1000 8'----1--- -> 4'0000 17'00000000000100000 |
| transition: 4'0100 8'-0--0--0 -> 4'0100 17'01000010000000000 |
| transition: 4'0100 8'-0--0--1 -> 4'0101 17'01010010000000000 |
| transition: 4'0100 8'-10-0--- -> 4'0100 17'01000010000000000 |
| transition: 4'0100 8'-11-0--- -> 4'0101 17'01010010000000000 |
| transition: 4'0100 8'----1--- -> 4'0000 17'00000010000000000 |
| transition: 4'1100 8'-0--0-0- -> 4'1100 17'11000001000000000 |
| transition: 4'1100 8'-0--0-10 -> 4'1100 17'11000001000000000 |
| transition: 4'1100 8'-0--0-11 -> 4'1001 17'10010001000000000 |
| transition: 4'1100 8'-10-0--- -> 4'0100 17'01000001000000000 |
| transition: 4'1100 8'-11-0--- -> 4'0101 17'01010001000000000 |
| transition: 4'1100 8'----1--- -> 4'0000 17'00000001000000000 |
| transition: 4'0010 8'-0--0--0 -> 4'0010 17'00100000000000010 |
| transition: 4'0010 8'-0--0--1 -> 4'0011 17'00110000000000010 |
| transition: 4'0010 8'-10-0--- -> 4'0100 17'01000000000000010 |
| transition: 4'0010 8'-11-0--- -> 4'0101 17'01010000000000010 |
| transition: 4'0010 8'----1--- -> 4'0000 17'00000000000000010 |
| transition: 4'1010 8'-0--0--0 -> 4'1010 17'10100000010000000 |
| transition: 4'1010 8'-0--0--1 -> 4'1011 17'10110000010000000 |
| transition: 4'1010 8'-10-0--- -> 4'0100 17'01000000010000000 |
| transition: 4'1010 8'-11-0--- -> 4'0101 17'01010000010000000 |
| transition: 4'1010 8'----1--- -> 4'0000 17'00000000010000000 |
| transition: 4'0110 8'-0--0--0 -> 4'0110 17'01100000000001000 |
| transition: 4'0110 8'-0--0--1 -> 4'0111 17'01110000000001000 |
| transition: 4'0110 8'-10-0--- -> 4'0100 17'01000000000001000 |
| transition: 4'0110 8'-11-0--- -> 4'0101 17'01010000000001000 |
| transition: 4'0110 8'----1--- -> 4'0000 17'00000000000001000 |
| transition: 4'0001 8'00--0--- -> 4'0001 17'00010100000000000 |
| transition: 4'0001 8'10--0--- -> 4'0010 17'00100100000000000 |
| transition: 4'0001 8'-10-0--- -> 4'0100 17'01000100000000000 |
| transition: 4'0001 8'-11-0--- -> 4'0101 17'01010100000000000 |
| transition: 4'0001 8'----1--- -> 4'0000 17'00000100000000000 |
| transition: 4'1001 8'-0--0--0 -> 4'1001 17'10010000001000000 |
| transition: 4'1001 8'-0--0--1 -> 4'1010 17'10100000001000000 |
| transition: 4'1001 8'-10-0--- -> 4'0100 17'01000000001000000 |
| transition: 4'1001 8'-11-0--- -> 4'0101 17'01010000001000000 |
| transition: 4'1001 8'----1--- -> 4'0000 17'00000000001000000 |
| transition: 4'0101 8'-0-00--- -> 4'0101 17'01010000000000100 |
| transition: 4'0101 8'-0-10--0 -> 4'0101 17'01010000000000100 |
| transition: 4'0101 8'-0-10--1 -> 4'0110 17'01100000000000100 |
| transition: 4'0101 8'-10-0--- -> 4'0100 17'01000000000000100 |
| transition: 4'0101 8'-11-0--- -> 4'0101 17'01010000000000100 |
| transition: 4'0101 8'----1--- -> 4'0000 17'00000000000000100 |
| transition: 4'0011 8'00--0--- -> 4'0011 17'00111000000000000 |
| transition: 4'0011 8'10--0--- -> 4'0100 17'01001000000000000 |
| transition: 4'0011 8'-10-0--- -> 4'0100 17'01001000000000000 |
| transition: 4'0011 8'-11-0--- -> 4'0101 17'01011000000000000 |
| transition: 4'0011 8'----1--- -> 4'0000 17'00001000000000000 |
| transition: 4'1011 8'-0--0--0 -> 4'1011 17'10110000100000000 |
| transition: 4'1011 8'-0--0--1 -> 4'1100 17'11000000100000000 |
| transition: 4'1011 8'-10-0--- -> 4'0100 17'01000000100000000 |
| transition: 4'1011 8'-11-0--- -> 4'0101 17'01010000100000000 |
| transition: 4'1011 8'----1--- -> 4'0000 17'00000000100000000 |
| transition: 4'0111 8'-0--0--0 -> 4'0111 17'01110000000010000 |
| transition: 4'0111 8'-0--00-1 -> 4'1001 17'10010000000010000 |
| transition: 4'0111 8'-0--01-1 -> 4'1000 17'10000000000010000 |
| transition: 4'0111 8'-10-0--- -> 4'0100 17'01000000000010000 |
| transition: 4'0111 8'-11-0--- -> 4'0101 17'01010000000010000 |
| transition: 4'0111 8'----1--- -> 4'0000 17'00000000000010000 |
| |
| 12.8.3. Executing FSM_OPT pass (simple optimizations of FSMs). |
| Optimizing FSM `$fsm$\soc.spimemio.spimemio.state$16420' from module `\mgmt_core'. |
| Optimizing FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$16414' from module `\mgmt_core'. |
| Optimizing FSM `$fsm$\soc.cpu.state$16409' from module `\mgmt_core'. |
| Merging pattern 3'--0 and 3'--1 from group (1 0 5'10000). |
| Merging pattern 3'--1 and 3'--0 from group (1 0 5'10000). |
| Optimizing FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$16404' from module `\mgmt_core'. |
| Optimizing FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$16394' from module `\mgmt_core'. |
| Merging pattern 24'------------------111000 and 24'------------------111010 from group (0 0 16'0100000000100000). |
| Merging pattern 24'------------------101100 and 24'------------------101110 from group (0 0 16'0100000000100000). |
| Merging pattern 24'------------------111100 and 24'------------------111110 from group (0 0 16'0100000000100000). |
| Merging pattern 24'------------------111010 and 24'------------------111000 from group (0 0 16'0100000000100000). |
| Merging pattern 24'------------------101110 and 24'------------------101100 from group (0 0 16'0100000000100000). |
| Merging pattern 24'------------------111110 and 24'------------------111100 from group (0 0 16'0100000000100000). |
| Merging pattern 24'------------------1110-0 and 24'------------------1111-0 from group (0 0 16'0100000000100000). |
| Merging pattern 24'------------------1111-0 and 24'------------------1110-0 from group (0 0 16'0100000000100000). |
| Merging pattern 24'------------------111001 and 24'------------------111011 from group (0 1 16'0010000000100000). |
| Merging pattern 24'------------------101101 and 24'------------------101111 from group (0 1 16'0010000000100000). |
| Merging pattern 24'------------------111101 and 24'------------------111111 from group (0 1 16'0010000000100000). |
| Merging pattern 24'------------------111011 and 24'------------------111001 from group (0 1 16'0010000000100000). |
| Merging pattern 24'------------------101111 and 24'------------------101101 from group (0 1 16'0010000000100000). |
| Merging pattern 24'------------------111111 and 24'------------------111101 from group (0 1 16'0010000000100000). |
| Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (0 1 16'0010000000100000). |
| Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (0 1 16'0010000000100000). |
| Merging pattern 24'-------0--00------111000 and 24'-------0--00------111010 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-----1-1--00------111000 and 24'-----1-1--00------111010 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------01------111000 and 24'----------01------111010 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------1-------111000 and 24'----------1-------111010 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-------0--00------101100 and 24'-------0--00------101110 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-----1-1--00------101100 and 24'-----1-1--00------101110 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------01------101100 and 24'----------01------101110 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------1-------101100 and 24'----------1-------101110 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-------0--00------111100 and 24'-------0--00------111110 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-----1-1--00------111100 and 24'-----1-1--00------111110 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------01------111100 and 24'----------01------111110 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------1-------111100 and 24'----------1-------111110 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-------0--00------111010 and 24'-------0--00------111000 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-----1-1--00------111010 and 24'-----1-1--00------111000 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------01------111010 and 24'----------01------111000 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------1-------111010 and 24'----------1-------111000 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-------0--00------101110 and 24'-------0--00------101100 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-----1-1--00------101110 and 24'-----1-1--00------101100 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------01------101110 and 24'----------01------101100 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------1-------101110 and 24'----------1-------101100 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-------0--00------111110 and 24'-------0--00------111100 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-----1-1--00------111110 and 24'-----1-1--00------111100 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------01------111110 and 24'----------01------111100 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------1-------111110 and 24'----------1-------111100 from group (1 1 16'1010000000000000). |
| Merging pattern 24'------------------111001 and 24'------------------111011 from group (1 1 16'1010000000000000). |
| Merging pattern 24'------------------101101 and 24'------------------101111 from group (1 1 16'1010000000000000). |
| Merging pattern 24'------------------111101 and 24'------------------111111 from group (1 1 16'1010000000000000). |
| Merging pattern 24'------------------111011 and 24'------------------111001 from group (1 1 16'1010000000000000). |
| Merging pattern 24'------------------101111 and 24'------------------101101 from group (1 1 16'1010000000000000). |
| Merging pattern 24'------------------111111 and 24'------------------111101 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-------0--00------1110-0 and 24'-------0--00------1111-0 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-----1-1--00------1110-0 and 24'-----1-1--00------1111-0 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------01------1110-0 and 24'----------01------1111-0 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------1-------1110-0 and 24'----------1-------1111-0 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-------0--00------1111-0 and 24'-------0--00------1110-0 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-----1-1--00------1111-0 and 24'-----1-1--00------1110-0 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------01------1111-0 and 24'----------01------1110-0 from group (1 1 16'1010000000000000). |
| Merging pattern 24'----------1-------1111-0 and 24'----------1-------1110-0 from group (1 1 16'1010000000000000). |
| Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (1 1 16'1010000000000000). |
| Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (1 1 16'1010000000000000). |
| Merging pattern 24'-----0-1--00------111000 and 24'-----0-1--00------111010 from group (1 2 16'1001000000000000). |
| Merging pattern 24'-----0-1--00------101100 and 24'-----0-1--00------101110 from group (1 2 16'1001000000000000). |
| Merging pattern 24'-----0-1--00------111100 and 24'-----0-1--00------111110 from group (1 2 16'1001000000000000). |
| Merging pattern 24'-----0-1--00------111010 and 24'-----0-1--00------111000 from group (1 2 16'1001000000000000). |
| Merging pattern 24'-----0-1--00------101110 and 24'-----0-1--00------101100 from group (1 2 16'1001000000000000). |
| Merging pattern 24'-----0-1--00------111110 and 24'-----0-1--00------111100 from group (1 2 16'1001000000000000). |
| Merging pattern 24'-----0-1--00------1110-0 and 24'-----0-1--00------1111-0 from group (1 2 16'1001000000000000). |
| Merging pattern 24'-----0-1--00------1111-0 and 24'-----0-1--00------1110-0 from group (1 2 16'1001000000000000). |
| Merging pattern 24'---0--1-----10----111000 and 24'---0--1-----10----111010 from group (2 0 16'0100000000001000). |
| Merging pattern 24'---0--1-----10----101100 and 24'---0--1-----10----101110 from group (2 0 16'0100000000001000). |
| Merging pattern 24'---0--1-----10----111100 and 24'---0--1-----10----111110 from group (2 0 16'0100000000001000). |
| Merging pattern 24'---0--1-----10----111010 and 24'---0--1-----10----111000 from group (2 0 16'0100000000001000). |
| Merging pattern 24'---0--1-----10----101110 and 24'---0--1-----10----101100 from group (2 0 16'0100000000001000). |
| Merging pattern 24'---0--1-----10----111110 and 24'---0--1-----10----111100 from group (2 0 16'0100000000001000). |
| Merging pattern 24'---0--1-----10----1110-0 and 24'---0--1-----10----1111-0 from group (2 0 16'0100000000001000). |
| Merging pattern 24'---0--1-----10----1111-0 and 24'---0--1-----10----1110-0 from group (2 0 16'0100000000001000). |
| Merging pattern 24'---0--1-----11----111000 and 24'---0--1-----11----111010 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---1--1-----------111000 and 24'---1--1-----------111010 from group (2 1 16'0010000000001000). |
| Merging pattern 24'-1----------------111000 and 24'-1----------------111010 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---0--1-----11----101100 and 24'---0--1-----11----101110 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---1--1-----------101100 and 24'---1--1-----------101110 from group (2 1 16'0010000000001000). |
| Merging pattern 24'-1----------------101100 and 24'-1----------------101110 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---0--1-----11----111100 and 24'---0--1-----11----111110 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---1--1-----------111100 and 24'---1--1-----------111110 from group (2 1 16'0010000000001000). |
| Merging pattern 24'-1----------------111100 and 24'-1----------------111110 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---0--1-----11----111010 and 24'---0--1-----11----111000 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---1--1-----------111010 and 24'---1--1-----------111000 from group (2 1 16'0010000000001000). |
| Merging pattern 24'-1----------------111010 and 24'-1----------------111000 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---0--1-----11----101110 and 24'---0--1-----11----101100 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---1--1-----------101110 and 24'---1--1-----------101100 from group (2 1 16'0010000000001000). |
| Merging pattern 24'-1----------------101110 and 24'-1----------------101100 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---0--1-----11----111110 and 24'---0--1-----11----111100 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---1--1-----------111110 and 24'---1--1-----------111100 from group (2 1 16'0010000000001000). |
| Merging pattern 24'-1----------------111110 and 24'-1----------------111100 from group (2 1 16'0010000000001000). |
| Merging pattern 24'------------------111001 and 24'------------------111011 from group (2 1 16'0010000000001000). |
| Merging pattern 24'------------------101101 and 24'------------------101111 from group (2 1 16'0010000000001000). |
| Merging pattern 24'------------------111101 and 24'------------------111111 from group (2 1 16'0010000000001000). |
| Merging pattern 24'------------------111011 and 24'------------------111001 from group (2 1 16'0010000000001000). |
| Merging pattern 24'------------------101111 and 24'------------------101101 from group (2 1 16'0010000000001000). |
| Merging pattern 24'------------------111111 and 24'------------------111101 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---0--1-----11----1110-0 and 24'---0--1-----11----1111-0 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---1--1-----------1110-0 and 24'---1--1-----------1111-0 from group (2 1 16'0010000000001000). |
| Merging pattern 24'-1----------------1110-0 and 24'-1----------------1111-0 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---0--1-----11----1111-0 and 24'---0--1-----11----1110-0 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---1--1-----------1111-0 and 24'---1--1-----------1110-0 from group (2 1 16'0010000000001000). |
| Merging pattern 24'-1----------------1111-0 and 24'-1----------------1110-0 from group (2 1 16'0010000000001000). |
| Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (2 1 16'0010000000001000). |
| Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (2 1 16'0010000000001000). |
| Merging pattern 24'---0--1-----0-----111000 and 24'---0--1-----0-----111010 from group (2 2 16'0001000000001000). |
| Merging pattern 24'---0--1-----0-----101100 and 24'---0--1-----0-----101110 from group (2 2 16'0001000000001000). |
| Merging pattern 24'---0--1-----0-----111100 and 24'---0--1-----0-----111110 from group (2 2 16'0001000000001000). |
| Merging pattern 24'---0--1-----0-----111010 and 24'---0--1-----0-----111000 from group (2 2 16'0001000000001000). |
| Merging pattern 24'---0--1-----0-----101110 and 24'---0--1-----0-----101100 from group (2 2 16'0001000000001000). |
| Merging pattern 24'---0--1-----0-----111110 and 24'---0--1-----0-----111100 from group (2 2 16'0001000000001000). |
| Merging pattern 24'---0--1-----0-----1110-0 and 24'---0--1-----0-----1111-0 from group (2 2 16'0001000000001000). |
| Merging pattern 24'---0--1-----0-----1111-0 and 24'---0--1-----0-----1110-0 from group (2 2 16'0001000000001000). |
| Merging pattern 24'00----0-0-----0---111000 and 24'00----0-0-----0---111010 from group (2 3 16'0000010000001000). |
| Merging pattern 24'1-----------------111000 and 24'1-----------------111010 from group (2 3 16'0000010000001000). |
| Merging pattern 24'00----0-0-----0---101100 and 24'00----0-0-----0---101110 from group (2 3 16'0000010000001000). |
| Merging pattern 24'1-----------------101100 and 24'1-----------------101110 from group (2 3 16'0000010000001000). |
| Merging pattern 24'00----0-0-----0---111100 and 24'00----0-0-----0---111110 from group (2 3 16'0000010000001000). |
| Merging pattern 24'1-----------------111100 and 24'1-----------------111110 from group (2 3 16'0000010000001000). |
| Merging pattern 24'00----0-0-----0---111010 and 24'00----0-0-----0---111000 from group (2 3 16'0000010000001000). |
| Merging pattern 24'1-----------------111010 and 24'1-----------------111000 from group (2 3 16'0000010000001000). |
| Merging pattern 24'00----0-0-----0---101110 and 24'00----0-0-----0---101100 from group (2 3 16'0000010000001000). |
| Merging pattern 24'1-----------------101110 and 24'1-----------------101100 from group (2 3 16'0000010000001000). |
| Merging pattern 24'00----0-0-----0---111110 and 24'00----0-0-----0---111100 from group (2 3 16'0000010000001000). |
| Merging pattern 24'1-----------------111110 and 24'1-----------------111100 from group (2 3 16'0000010000001000). |
| Merging pattern 24'00----0-0-----0---1110-0 and 24'00----0-0-----0---1111-0 from group (2 3 16'0000010000001000). |
| Merging pattern 24'1-----------------1110-0 and 24'1-----------------1111-0 from group (2 3 16'0000010000001000). |
| Merging pattern 24'00----0-0-----0---1111-0 and 24'00----0-0-----0---1110-0 from group (2 3 16'0000010000001000). |
| Merging pattern 24'1-----------------1111-0 and 24'1-----------------1110-0 from group (2 3 16'0000010000001000). |
| Merging pattern 24'00------1-----0---111000 and 24'00------1-----0---111010 from group (2 4 16'0000000100001000). |
| Merging pattern 24'00------1-----0---101100 and 24'00------1-----0---101110 from group (2 4 16'0000000100001000). |
| Merging pattern 24'00------1-----0---111100 and 24'00------1-----0---111110 from group (2 4 16'0000000100001000). |
| Merging pattern 24'00------1-----0---111010 and 24'00------1-----0---111000 from group (2 4 16'0000000100001000). |
| Merging pattern 24'00------1-----0---101110 and 24'00------1-----0---101100 from group (2 4 16'0000000100001000). |
| Merging pattern 24'00------1-----0---111110 and 24'00------1-----0---111100 from group (2 4 16'0000000100001000). |
| Merging pattern 24'00------1-----0---1110-0 and 24'00------1-----0---1111-0 from group (2 4 16'0000000100001000). |
| Merging pattern 24'00------1-----0---1111-0 and 24'00------1-----0---1110-0 from group (2 4 16'0000000100001000). |
| Merging pattern 24'--------------1---111000 and 24'--------------1---111010 from group (2 5 16'0000000010001000). |
| Merging pattern 24'--------------1---101100 and 24'--------------1---101110 from group (2 5 16'0000000010001000). |
| Merging pattern 24'--------------1---111100 and 24'--------------1---111110 from group (2 5 16'0000000010001000). |
| Merging pattern 24'--------------1---111010 and 24'--------------1---111000 from group (2 5 16'0000000010001000). |
| Merging pattern 24'--------------1---101110 and 24'--------------1---101100 from group (2 5 16'0000000010001000). |
| Merging pattern 24'--------------1---111110 and 24'--------------1---111100 from group (2 5 16'0000000010001000). |
| Merging pattern 24'--------------1---1110-0 and 24'--------------1---1111-0 from group (2 5 16'0000000010001000). |
| Merging pattern 24'--------------1---1111-0 and 24'--------------1---1110-0 from group (2 5 16'0000000010001000). |
| Merging pattern 24'---------0--------111000 and 24'---------0--------111010 from group (3 1 16'0010000001000000). |
| Merging pattern 24'----1----1--------111000 and 24'----1----1--------111010 from group (3 1 16'0010000001000000). |
| Merging pattern 24'---------0--------101100 and 24'---------0--------101110 from group (3 1 16'0010000001000000). |
| Merging pattern 24'----1----1--------101100 and 24'----1----1--------101110 from group (3 1 16'0010000001000000). |
| Merging pattern 24'---------0--------111100 and 24'---------0--------111110 from group (3 1 16'0010000001000000). |
| Merging pattern 24'----1----1--------111100 and 24'----1----1--------111110 from group (3 1 16'0010000001000000). |
| Merging pattern 24'---------0--------111010 and 24'---------0--------111000 from group (3 1 16'0010000001000000). |
| Merging pattern 24'----1----1--------111010 and 24'----1----1--------111000 from group (3 1 16'0010000001000000). |
| Merging pattern 24'---------0--------101110 and 24'---------0--------101100 from group (3 1 16'0010000001000000). |
| Merging pattern 24'----1----1--------101110 and 24'----1----1--------101100 from group (3 1 16'0010000001000000). |
| Merging pattern 24'---------0--------111110 and 24'---------0--------111100 from group (3 1 16'0010000001000000). |
| Merging pattern 24'----1----1--------111110 and 24'----1----1--------111100 from group (3 1 16'0010000001000000). |
| Merging pattern 24'------------------111001 and 24'------------------111011 from group (3 1 16'0010000001000000). |
| Merging pattern 24'------------------101101 and 24'------------------101111 from group (3 1 16'0010000001000000). |
| Merging pattern 24'------------------111101 and 24'------------------111111 from group (3 1 16'0010000001000000). |
| Merging pattern 24'------------------111011 and 24'------------------111001 from group (3 1 16'0010000001000000). |
| Merging pattern 24'------------------101111 and 24'------------------101101 from group (3 1 16'0010000001000000). |
| Merging pattern 24'------------------111111 and 24'------------------111101 from group (3 1 16'0010000001000000). |
| Merging pattern 24'---------0--------1110-0 and 24'---------0--------1111-0 from group (3 1 16'0010000001000000). |
| Merging pattern 24'----1----1--------1110-0 and 24'----1----1--------1111-0 from group (3 1 16'0010000001000000). |
| Merging pattern 24'---------0--------1111-0 and 24'---------0--------1110-0 from group (3 1 16'0010000001000000). |
| Merging pattern 24'----1----1--------1111-0 and 24'----1----1--------1110-0 from group (3 1 16'0010000001000000). |
| Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (3 1 16'0010000001000000). |
| Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (3 1 16'0010000001000000). |
| Merging pattern 24'----0----1--------111000 and 24'----0----1--------111010 from group (3 3 16'0000010001000000). |
| Merging pattern 24'----0----1--------101100 and 24'----0----1--------101110 from group (3 3 16'0000010001000000). |
| Merging pattern 24'----0----1--------111100 and 24'----0----1--------111110 from group (3 3 16'0000010001000000). |
| Merging pattern 24'----0----1--------111010 and 24'----0----1--------111000 from group (3 3 16'0000010001000000). |
| Merging pattern 24'----0----1--------101110 and 24'----0----1--------101100 from group (3 3 16'0000010001000000). |
| Merging pattern 24'----0----1--------111110 and 24'----0----1--------111100 from group (3 3 16'0000010001000000). |
| Merging pattern 24'----0----1--------1110-0 and 24'----0----1--------1111-0 from group (3 3 16'0000010001000000). |
| Merging pattern 24'----0----1--------1111-0 and 24'----0----1--------1110-0 from group (3 3 16'0000010001000000). |
| Merging pattern 24'----------------11111000 and 24'----------------11111010 from group (4 1 16'0010000000000010). |
| Merging pattern 24'----------------11101100 and 24'----------------11101110 from group (4 1 16'0010000000000010). |
| Merging pattern 24'----------------11111100 and 24'----------------11111110 from group (4 1 16'0010000000000010). |
| Merging pattern 24'----------------11111010 and 24'----------------11111000 from group (4 1 16'0010000000000010). |
| Merging pattern 24'----------------11101110 and 24'----------------11101100 from group (4 1 16'0010000000000010). |
| Merging pattern 24'----------------11111110 and 24'----------------11111100 from group (4 1 16'0010000000000010). |
| Merging pattern 24'------------------111001 and 24'------------------111011 from group (4 1 16'0010000000000010). |
| Merging pattern 24'------------------101101 and 24'------------------101111 from group (4 1 16'0010000000000010). |
| Merging pattern 24'------------------111101 and 24'------------------111111 from group (4 1 16'0010000000000010). |
| Merging pattern 24'------------------111011 and 24'------------------111001 from group (4 1 16'0010000000000010). |
| Merging pattern 24'------------------101111 and 24'------------------101101 from group (4 1 16'0010000000000010). |
| Merging pattern 24'------------------111111 and 24'------------------111101 from group (4 1 16'0010000000000010). |
| Merging pattern 24'----------------111110-0 and 24'----------------111111-0 from group (4 1 16'0010000000000010). |
| Merging pattern 24'----------------111111-0 and 24'----------------111110-0 from group (4 1 16'0010000000000010). |
| Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (4 1 16'0010000000000010). |
| Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (4 1 16'0010000000000010). |
| Merging pattern 24'----------------10111000 and 24'----------------10111010 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------0-111000 and 24'----------------0-111010 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------10101100 and 24'----------------10101110 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------0-101100 and 24'----------------0-101110 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------10111100 and 24'----------------10111110 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------0-111100 and 24'----------------0-111110 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------10111010 and 24'----------------10111000 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------0-111010 and 24'----------------0-111000 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------10101110 and 24'----------------10101100 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------0-101110 and 24'----------------0-101100 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------10111110 and 24'----------------10111100 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------0-111110 and 24'----------------0-111100 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------101110-0 and 24'----------------101111-0 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------0-1110-0 and 24'----------------0-1111-0 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------101111-0 and 24'----------------101110-0 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------0-1111-0 and 24'----------------0-1110-0 from group (4 4 16'0000000100000010). |
| Merging pattern 24'----------------11111000 and 24'----------------11111010 from group (5 1 16'0010000000000100). |
| Merging pattern 24'----------------11101100 and 24'----------------11101110 from group (5 1 16'0010000000000100). |
| Merging pattern 24'----------------11111100 and 24'----------------11111110 from group (5 1 16'0010000000000100). |
| Merging pattern 24'----------------11111010 and 24'----------------11111000 from group (5 1 16'0010000000000100). |
| Merging pattern 24'----------------11101110 and 24'----------------11101100 from group (5 1 16'0010000000000100). |
| Merging pattern 24'----------------11111110 and 24'----------------11111100 from group (5 1 16'0010000000000100). |
| Merging pattern 24'------------------111001 and 24'------------------111011 from group (5 1 16'0010000000000100). |
| Merging pattern 24'------------------101101 and 24'------------------101111 from group (5 1 16'0010000000000100). |
| Merging pattern 24'------------------111101 and 24'------------------111111 from group (5 1 16'0010000000000100). |
| Merging pattern 24'------------------111011 and 24'------------------111001 from group (5 1 16'0010000000000100). |
| Merging pattern 24'------------------101111 and 24'------------------101101 from group (5 1 16'0010000000000100). |
| Merging pattern 24'------------------111111 and 24'------------------111101 from group (5 1 16'0010000000000100). |
| Merging pattern 24'----------------111110-0 and 24'----------------111111-0 from group (5 1 16'0010000000000100). |
| Merging pattern 24'----------------111111-0 and 24'----------------111110-0 from group (5 1 16'0010000000000100). |
| Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (5 1 16'0010000000000100). |
| Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (5 1 16'0010000000000100). |
| Merging pattern 24'----------------10111000 and 24'----------------10111010 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------0-111000 and 24'----------------0-111010 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------10101100 and 24'----------------10101110 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------0-101100 and 24'----------------0-101110 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------10111100 and 24'----------------10111110 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------0-111100 and 24'----------------0-111110 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------10111010 and 24'----------------10111000 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------0-111010 and 24'----------------0-111000 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------10101110 and 24'----------------10101100 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------0-101110 and 24'----------------0-101100 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------10111110 and 24'----------------10111100 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------0-111110 and 24'----------------0-111100 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------101110-0 and 24'----------------101111-0 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------0-1110-0 and 24'----------------0-1111-0 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------101111-0 and 24'----------------101110-0 from group (5 5 16'0000000010000100). |
| Merging pattern 24'----------------0-1111-0 and 24'----------------0-1110-0 from group (5 5 16'0000000010000100). |
| Removing unused input signal $auto$opt_reduce.cc:134:opt_mux$16378. |
| Removing unused input signal $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1826$8665_Y. |
| Optimizing FSM `$fsm$\housekeeping.U1.state$16387' from module `\mgmt_core'. |
| |
| 12.8.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 117 unused cells and 117 unused wires. |
| <suppressed ~118 debug messages> |
| |
| 12.8.5. Executing FSM_OPT pass (simple optimizations of FSMs). |
| Optimizing FSM `$fsm$\housekeeping.U1.state$16387' from module `\mgmt_core'. |
| Removing unused output signal $flatten\housekeeping.\U1.$0\state[2:0] [0]. |
| Removing unused output signal $flatten\housekeeping.\U1.$0\state[2:0] [1]. |
| Removing unused output signal $flatten\housekeeping.\U1.$0\state[2:0] [2]. |
| Optimizing FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$16394' from module `\mgmt_core'. |
| Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [0]. |
| Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [1]. |
| Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [2]. |
| Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [3]. |
| Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [4]. |
| Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [5]. |
| Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [6]. |
| Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [7]. |
| Optimizing FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$16404' from module `\mgmt_core'. |
| Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0] [0]. |
| Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0] [1]. |
| Optimizing FSM `$fsm$\soc.cpu.state$16409' from module `\mgmt_core'. |
| Removing unused output signal $flatten\soc.\cpu.$0\state[1:0] [0]. |
| Removing unused output signal $flatten\soc.\cpu.$0\state[1:0] [1]. |
| Optimizing FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$16414' from module `\mgmt_core'. |
| Removing unused output signal $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0] [0]. |
| Removing unused output signal $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0] [1]. |
| Optimizing FSM `$fsm$\soc.spimemio.spimemio.state$16420' from module `\mgmt_core'. |
| Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [0]. |
| Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [1]. |
| Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [2]. |
| Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [3]. |
| |
| 12.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). |
| Recoding FSM `$fsm$\housekeeping.U1.state$16387' from module `\mgmt_core' using `auto' encoding: |
| mapping auto encoding to `one-hot` for this FSM. |
| 000 -> ----1 |
| 100 -> ---1- |
| 010 -> --1-- |
| 001 -> -1--- |
| 101 -> 1---- |
| Recoding FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$16394' from module `\mgmt_core' using `auto' encoding: |
| mapping auto encoding to `one-hot` for this FSM. |
| 10000000 -> -----1 |
| 01000000 -> ----1- |
| 00100000 -> ---1-- |
| 00001000 -> --1--- |
| 00000010 -> -1---- |
| 00000001 -> 1----- |
| Recoding FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$16404' from module `\mgmt_core' using `auto' encoding: |
| mapping auto encoding to `one-hot` for this FSM. |
| 00 -> --1 |
| 10 -> -1- |
| 01 -> 1-- |
| Recoding FSM `$fsm$\soc.cpu.state$16409' from module `\mgmt_core' using `auto' encoding: |
| mapping auto encoding to `one-hot` for this FSM. |
| 00 -> --1 |
| 10 -> -1- |
| 01 -> 1-- |
| Recoding FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$16414' from module `\mgmt_core' using `auto' encoding: |
| mapping auto encoding to `one-hot` for this FSM. |
| 00 -> ---1 |
| 10 -> --1- |
| 01 -> -1-- |
| 11 -> 1--- |
| Recoding FSM `$fsm$\soc.spimemio.spimemio.state$16420' from module `\mgmt_core' using `auto' encoding: |
| mapping auto encoding to `one-hot` for this FSM. |
| 0000 -> ------------1 |
| 1000 -> -----------1- |
| 0100 -> ----------1-- |
| 1100 -> ---------1--- |
| 0010 -> --------1---- |
| 1010 -> -------1----- |
| 0110 -> ------1------ |
| 0001 -> -----1------- |
| 1001 -> ----1-------- |
| 0101 -> ---1--------- |
| 0011 -> --1---------- |
| 1011 -> -1----------- |
| 0111 -> 1------------ |
| |
| 12.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). |
| |
| FSM `$fsm$\housekeeping.U1.state$16387' from module `mgmt_core': |
| ------------------------------------- |
| |
| Information on FSM $fsm$\housekeeping.U1.state$16387 (\housekeeping.U1.state): |
| |
| Number of input signals: 9 |
| Number of output signals: 5 |
| Number of state bits: 5 |
| |
| Input signals: |
| 0: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:428$3614_Y |
| 1: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:426$3613_Y |
| 2: $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:424$3612_Y |
| 3: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:422$3611_Y |
| 4: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:381$3601_Y |
| 5: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:368$3600_Y |
| 6: \housekeeping.U1.pre_pass_thru_user |
| 7: \housekeeping.U1.pre_pass_thru_mgmt |
| 8: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:458$3625_Y |
| |
| Output signals: |
| 0: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:417$3608_Y |
| 1: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:388$3604_Y |
| 2: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:388$3603_Y |
| 3: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:365$3598_Y |
| 4: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:349$3592_Y |
| |
| State encoding: |
| 0: 5'----1 <RESET STATE> |
| 1: 5'---1- |
| 2: 5'--1-- |
| 3: 5'-1--- |
| 4: 5'1---- |
| |
| Transition Table (state_in, ctrl_in, state_out, ctrl_out): |
| 0: 0 9'---000000 -> 0 5'00001 |
| 1: 0 9'---0-0001 -> 0 5'00001 |
| 2: 0 9'---0-001- -> 0 5'00001 |
| 3: 0 9'---0-01-- -> 0 5'00001 |
| 4: 0 9'---0-1--- -> 0 5'00001 |
| 5: 0 9'---1----- -> 0 5'00001 |
| 6: 0 9'-01010000 -> 1 5'00001 |
| 7: 0 9'-00010000 -> 3 5'00001 |
| 8: 0 9'-1-010000 -> 4 5'00001 |
| 9: 1 9'--------- -> 1 5'00010 |
| 10: 2 9'1---1---- -> 0 5'01000 |
| 11: 2 9'----0---- -> 2 5'01000 |
| 12: 2 9'0---1---- -> 2 5'01000 |
| 13: 3 9'----1---- -> 2 5'10000 |
| 14: 3 9'----0---- -> 3 5'10000 |
| 15: 4 9'--------- -> 4 5'00100 |
| |
| ------------------------------------- |
| |
| FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$16394' from module `mgmt_core': |
| ------------------------------------- |
| |
| Information on FSM $fsm$\soc.cpu.picorv32_core.cpu_state$16394 (\soc.cpu.picorv32_core.cpu_state): |
| |
| Number of input signals: 22 |
| Number of output signals: 8 |
| Number of state bits: 6 |
| |
| Input signals: |
| 0: \soc.cpu.wb_rst_i |
| 1: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1933$8719_Y |
| 2: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$8712_Y |
| 3: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1920$8709_Y |
| 4: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$8705_Y |
| 5: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1917$8702_Y |
| 6: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1867$8687_Y |
| 7: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$8683_Y |
| 8: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$8637_Y |
| 9: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1603$8623_Y |
| 10: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1600$8619_Y |
| 11: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1543$8606_Y |
| 12: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1533$8598_Y |
| 13: \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu |
| 14: \soc.cpu.picorv32_core.is_sb_sh_sw |
| 15: \soc.cpu.picorv32_core.decoder_trigger |
| 16: \soc.cpu.picorv32_core.instr_trap |
| 17: \soc.cpu.picorv32_core.instr_jal |
| 18: \soc.cpu.picorv32_core.mem_done |
| 19: \soc.cpu.picorv32_core.pcpi_int_ready |
| 20: $auto$opt_reduce.cc:134:opt_mux$16278 |
| 21: $auto$opt_reduce.cc:134:opt_mux$16276 |
| |
| Output signals: |
| 0: $flatten\soc.\cpu.\picorv32_core.$procmux$10243_CMP |
| 1: $flatten\soc.\cpu.\picorv32_core.$procmux$10104_CMP |
| 2: $flatten\soc.\cpu.\picorv32_core.$procmux$10093_CMP |
| 3: $flatten\soc.\cpu.\picorv32_core.$procmux$10029_CMP |
| 4: $flatten\soc.\cpu.\picorv32_core.$procmux$10005_CMP |
| 5: $flatten\soc.\cpu.\picorv32_core.$procmux$8806_CMP |
| 6: $flatten\soc.\cpu.\picorv32_core.$procmux$8802_CMP |
| 7: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y |
| |
| State encoding: |
| 0: 6'-----1 |
| 1: 6'----1- |
| 2: 6'---1-- |
| 3: 6'--1--- |
| 4: 6'-1---- |
| 5: 6'1----- |
| |
| Transition Table (state_in, ctrl_in, state_out, ctrl_out): |
| 0: 0 22'----------------10-000 -> 0 8'00100000 |
| 1: 0 22'----------------0---00 -> 0 8'00100000 |
| 2: 0 22'----------------101010 -> 0 8'00100000 |
| 3: 0 22'----------------0-1-10 -> 0 8'00100000 |
| 4: 0 22'----------------1011-0 -> 0 8'00100000 |
| 5: 0 22'----------------111--0 -> 0 8'00100000 |
| 6: 0 22'----------------11000- -> 0 8'00100000 |
| 7: 0 22'----------------1-010- -> 0 8'00100000 |
| 8: 0 22'------------------0-1- -> 0 8'00100000 |
| 9: 0 22'----------------10-001 -> 1 8'00100000 |
| 10: 0 22'----------------0---01 -> 1 8'00100000 |
| 11: 0 22'----------------101011 -> 1 8'00100000 |
| 12: 0 22'----------------0-1-11 -> 1 8'00100000 |
| 13: 0 22'----------------1011-1 -> 1 8'00100000 |
| 14: 0 22'----------------111--1 -> 1 8'00100000 |
| 15: 1 22'----------------11000- -> 0 8'10000000 |
| 16: 1 22'----------------1-010- -> 0 8'10000000 |
| 17: 1 22'------------------0-1- -> 0 8'10000000 |
| 18: 1 22'------0--00-----10-000 -> 1 8'10000000 |
| 19: 1 22'----1-1--00-----10-000 -> 1 8'10000000 |
| 20: 1 22'---------01-----10-000 -> 1 8'10000000 |
| 21: 1 22'---------1------10-000 -> 1 8'10000000 |
| 22: 1 22'------0--00-----0---00 -> 1 8'10000000 |
| 23: 1 22'----1-1--00-----0---00 -> 1 8'10000000 |
| 24: 1 22'---------01-----0---00 -> 1 8'10000000 |
| 25: 1 22'---------1------0---00 -> 1 8'10000000 |
| 26: 1 22'------0--00-----101010 -> 1 8'10000000 |
| 27: 1 22'----1-1--00-----101010 -> 1 8'10000000 |
| 28: 1 22'---------01-----101010 -> 1 8'10000000 |
| 29: 1 22'---------1------101010 -> 1 8'10000000 |
| 30: 1 22'------0--00-----0-1-10 -> 1 8'10000000 |
| 31: 1 22'----1-1--00-----0-1-10 -> 1 8'10000000 |
| 32: 1 22'---------01-----0-1-10 -> 1 8'10000000 |
| 33: 1 22'---------1------0-1-10 -> 1 8'10000000 |
| 34: 1 22'------0--00-----1011-0 -> 1 8'10000000 |
| 35: 1 22'----1-1--00-----1011-0 -> 1 8'10000000 |
| 36: 1 22'---------01-----1011-0 -> 1 8'10000000 |
| 37: 1 22'---------1------1011-0 -> 1 8'10000000 |
| 38: 1 22'------0--00-----111--0 -> 1 8'10000000 |
| 39: 1 22'----1-1--00-----111--0 -> 1 8'10000000 |
| 40: 1 22'---------01-----111--0 -> 1 8'10000000 |
| 41: 1 22'---------1------111--0 -> 1 8'10000000 |
| 42: 1 22'----------------10-001 -> 1 8'10000000 |
| 43: 1 22'----------------0---01 -> 1 8'10000000 |
| 44: 1 22'----------------101011 -> 1 8'10000000 |
| 45: 1 22'----------------0-1-11 -> 1 8'10000000 |
| 46: 1 22'----------------1011-1 -> 1 8'10000000 |
| 47: 1 22'----------------111--1 -> 1 8'10000000 |
| 48: 1 22'----0-1--00-----10-000 -> 2 8'10000000 |
| 49: 1 22'----0-1--00-----0---00 -> 2 8'10000000 |
| 50: 1 22'----0-1--00-----101010 -> 2 8'10000000 |
| 51: 1 22'----0-1--00-----0-1-10 -> 2 8'10000000 |
| 52: 1 22'----0-1--00-----1011-0 -> 2 8'10000000 |
| 53: 1 22'----0-1--00-----111--0 -> 2 8'10000000 |
| 54: 2 22'--0--1-----10---10-000 -> 0 8'00001000 |
| 55: 2 22'--0--1-----10---0---00 -> 0 8'00001000 |
| 56: 2 22'--0--1-----10---101010 -> 0 8'00001000 |
| 57: 2 22'--0--1-----10---0-1-10 -> 0 8'00001000 |
| 58: 2 22'--0--1-----10---1011-0 -> 0 8'00001000 |
| 59: 2 22'--0--1-----10---111--0 -> 0 8'00001000 |
| 60: 2 22'----------------11000- -> 0 8'00001000 |
| 61: 2 22'----------------1-010- -> 0 8'00001000 |
| 62: 2 22'------------------0-1- -> 0 8'00001000 |
| 63: 2 22'--0--1-----11---10-000 -> 1 8'00001000 |
| 64: 2 22'--1--1----------10-000 -> 1 8'00001000 |
| 65: 2 22'-1--------------10-000 -> 1 8'00001000 |
| 66: 2 22'--0--1-----11---0---00 -> 1 8'00001000 |
| 67: 2 22'--1--1----------0---00 -> 1 8'00001000 |
| 68: 2 22'-1--------------0---00 -> 1 8'00001000 |
| 69: 2 22'--0--1-----11---101010 -> 1 8'00001000 |
| 70: 2 22'--1--1----------101010 -> 1 8'00001000 |
| 71: 2 22'-1--------------101010 -> 1 8'00001000 |
| 72: 2 22'--0--1-----11---0-1-10 -> 1 8'00001000 |
| 73: 2 22'--1--1----------0-1-10 -> 1 8'00001000 |
| 74: 2 22'-1--------------0-1-10 -> 1 8'00001000 |
| 75: 2 22'--0--1-----11---1011-0 -> 1 8'00001000 |
| 76: 2 22'--1--1----------1011-0 -> 1 8'00001000 |
| 77: 2 22'-1--------------1011-0 -> 1 8'00001000 |
| 78: 2 22'--0--1-----11---111--0 -> 1 8'00001000 |
| 79: 2 22'--1--1----------111--0 -> 1 8'00001000 |
| 80: 2 22'-1--------------111--0 -> 1 8'00001000 |
| 81: 2 22'----------------10-001 -> 1 8'00001000 |
| 82: 2 22'----------------0---01 -> 1 8'00001000 |
| 83: 2 22'----------------101011 -> 1 8'00001000 |
| 84: 2 22'----------------0-1-11 -> 1 8'00001000 |
| 85: 2 22'----------------1011-1 -> 1 8'00001000 |
| 86: 2 22'----------------111--1 -> 1 8'00001000 |
| 87: 2 22'--0--1-----0----10-000 -> 2 8'00001000 |
| 88: 2 22'--0--1-----0----0---00 -> 2 8'00001000 |
| 89: 2 22'--0--1-----0----101010 -> 2 8'00001000 |
| 90: 2 22'--0--1-----0----0-1-10 -> 2 8'00001000 |
| 91: 2 22'--0--1-----0----1011-0 -> 2 8'00001000 |
| 92: 2 22'--0--1-----0----111--0 -> 2 8'00001000 |
| 93: 2 22'00---0-0-----0--10-000 -> 3 8'00001000 |
| 94: 2 22'1---------------10-000 -> 3 8'00001000 |
| 95: 2 22'00---0-0-----0--0---00 -> 3 8'00001000 |
| 96: 2 22'1---------------0---00 -> 3 8'00001000 |
| 97: 2 22'00---0-0-----0--101010 -> 3 8'00001000 |
| 98: 2 22'1---------------101010 -> 3 8'00001000 |
| 99: 2 22'00---0-0-----0--0-1-10 -> 3 8'00001000 |
| 100: 2 22'1---------------0-1-10 -> 3 8'00001000 |
| 101: 2 22'00---0-0-----0--1011-0 -> 3 8'00001000 |
| 102: 2 22'1---------------1011-0 -> 3 8'00001000 |
| 103: 2 22'00---0-0-----0--111--0 -> 3 8'00001000 |
| 104: 2 22'1---------------111--0 -> 3 8'00001000 |
| 105: 2 22'00-----1-----0--10-000 -> 4 8'00001000 |
| 106: 2 22'00-----1-----0--0---00 -> 4 8'00001000 |
| 107: 2 22'00-----1-----0--101010 -> 4 8'00001000 |
| 108: 2 22'00-----1-----0--0-1-10 -> 4 8'00001000 |
| 109: 2 22'00-----1-----0--1011-0 -> 4 8'00001000 |
| 110: 2 22'00-----1-----0--111--0 -> 4 8'00001000 |
| 111: 2 22'-------------1--10-000 -> 5 8'00001000 |
| 112: 2 22'-------------1--0---00 -> 5 8'00001000 |
| 113: 2 22'-------------1--101010 -> 5 8'00001000 |
| 114: 2 22'-------------1--0-1-10 -> 5 8'00001000 |
| 115: 2 22'-------------1--1011-0 -> 5 8'00001000 |
| 116: 2 22'-------------1--111--0 -> 5 8'00001000 |
| 117: 3 22'----------------11000- -> 0 8'01000000 |
| 118: 3 22'----------------1-010- -> 0 8'01000000 |
| 119: 3 22'------------------0-1- -> 0 8'01000000 |
| 120: 3 22'--------0-------10-000 -> 1 8'01000000 |
| 121: 3 22'---1----1-------10-000 -> 1 8'01000000 |
| 122: 3 22'--------0-------0---00 -> 1 8'01000000 |
| 123: 3 22'---1----1-------0---00 -> 1 8'01000000 |
| 124: 3 22'--------0-------101010 -> 1 8'01000000 |
| 125: 3 22'---1----1-------101010 -> 1 8'01000000 |
| 126: 3 22'--------0-------0-1-10 -> 1 8'01000000 |
| 127: 3 22'---1----1-------0-1-10 -> 1 8'01000000 |
| 128: 3 22'--------0-------1011-0 -> 1 8'01000000 |
| 129: 3 22'---1----1-------1011-0 -> 1 8'01000000 |
| 130: 3 22'--------0-------111--0 -> 1 8'01000000 |
| 131: 3 22'---1----1-------111--0 -> 1 8'01000000 |
| 132: 3 22'----------------10-001 -> 1 8'01000000 |
| 133: 3 22'----------------0---01 -> 1 8'01000000 |
| 134: 3 22'----------------101011 -> 1 8'01000000 |
| 135: 3 22'----------------0-1-11 -> 1 8'01000000 |
| 136: 3 22'----------------1011-1 -> 1 8'01000000 |
| 137: 3 22'----------------111--1 -> 1 8'01000000 |
| 138: 3 22'---0----1-------10-000 -> 3 8'01000000 |
| 139: 3 22'---0----1-------0---00 -> 3 8'01000000 |
| 140: 3 22'---0----1-------101010 -> 3 8'01000000 |
| 141: 3 22'---0----1-------0-1-10 -> 3 8'01000000 |
| 142: 3 22'---0----1-------1011-0 -> 3 8'01000000 |
| 143: 3 22'---0----1-------111--0 -> 3 8'01000000 |
| 144: 4 22'----------------11000- -> 0 8'00000010 |
| 145: 4 22'----------------1-010- -> 0 8'00000010 |
| 146: 4 22'------------------0-1- -> 0 8'00000010 |
| 147: 4 22'--------------1110-000 -> 1 8'00000010 |
| 148: 4 22'--------------110---00 -> 1 8'00000010 |
| 149: 4 22'--------------11101010 -> 1 8'00000010 |
| 150: 4 22'--------------110-1-10 -> 1 8'00000010 |
| 151: 4 22'--------------111011-0 -> 1 8'00000010 |
| 152: 4 22'--------------11111--0 -> 1 8'00000010 |
| 153: 4 22'----------------10-001 -> 1 8'00000010 |
| 154: 4 22'----------------0---01 -> 1 8'00000010 |
| 155: 4 22'----------------101011 -> 1 8'00000010 |
| 156: 4 22'----------------0-1-11 -> 1 8'00000010 |
| 157: 4 22'----------------1011-1 -> 1 8'00000010 |
| 158: 4 22'----------------111--1 -> 1 8'00000010 |
| 159: 4 22'--------------1010-000 -> 4 8'00000010 |
| 160: 4 22'--------------0-10-000 -> 4 8'00000010 |
| 161: 4 22'--------------100---00 -> 4 8'00000010 |
| 162: 4 22'--------------0-0---00 -> 4 8'00000010 |
| 163: 4 22'--------------10101010 -> 4 8'00000010 |
| 164: 4 22'--------------0-101010 -> 4 8'00000010 |
| 165: 4 22'--------------100-1-10 -> 4 8'00000010 |
| 166: 4 22'--------------0-0-1-10 -> 4 8'00000010 |
| 167: 4 22'--------------101011-0 -> 4 8'00000010 |
| 168: 4 22'--------------0-1011-0 -> 4 8'00000010 |
| 169: 4 22'--------------10111--0 -> 4 8'00000010 |
| 170: 4 22'--------------0-111--0 -> 4 8'00000010 |
| 171: 5 22'----------------11000- -> 0 8'00000100 |
| 172: 5 22'----------------1-010- -> 0 8'00000100 |
| 173: 5 22'------------------0-1- -> 0 8'00000100 |
| 174: 5 22'--------------1110-000 -> 1 8'00000100 |
| 175: 5 22'--------------110---00 -> 1 8'00000100 |
| 176: 5 22'--------------11101010 -> 1 8'00000100 |
| 177: 5 22'--------------110-1-10 -> 1 8'00000100 |
| 178: 5 22'--------------111011-0 -> 1 8'00000100 |
| 179: 5 22'--------------11111--0 -> 1 8'00000100 |
| 180: 5 22'----------------10-001 -> 1 8'00000100 |
| 181: 5 22'----------------0---01 -> 1 8'00000100 |
| 182: 5 22'----------------101011 -> 1 8'00000100 |
| 183: 5 22'----------------0-1-11 -> 1 8'00000100 |
| 184: 5 22'----------------1011-1 -> 1 8'00000100 |
| 185: 5 22'----------------111--1 -> 1 8'00000100 |
| 186: 5 22'--------------1010-000 -> 5 8'00000100 |
| 187: 5 22'--------------0-10-000 -> 5 8'00000100 |
| 188: 5 22'--------------100---00 -> 5 8'00000100 |
| 189: 5 22'--------------0-0---00 -> 5 8'00000100 |
| 190: 5 22'--------------10101010 -> 5 8'00000100 |
| 191: 5 22'--------------0-101010 -> 5 8'00000100 |
| 192: 5 22'--------------100-1-10 -> 5 8'00000100 |
| 193: 5 22'--------------0-0-1-10 -> 5 8'00000100 |
| 194: 5 22'--------------101011-0 -> 5 8'00000100 |
| 195: 5 22'--------------0-1011-0 -> 5 8'00000100 |
| 196: 5 22'--------------10111--0 -> 5 8'00000100 |
| 197: 5 22'--------------0-111--0 -> 5 8'00000100 |
| |
| ------------------------------------- |
| |
| FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$16404' from module `mgmt_core': |
| ------------------------------------- |
| |
| Information on FSM $fsm$\soc.cpu.picorv32_core.mem_wordsize$16404 (\soc.cpu.picorv32_core.mem_wordsize): |
| |
| Number of input signals: 13 |
| Number of output signals: 3 |
| Number of state bits: 3 |
| |
| Input signals: |
| 0: \soc.cpu.wb_rst_i |
| 1: $flatten\soc.\cpu.\picorv32_core.$procmux$10104_CMP |
| 2: $flatten\soc.\cpu.\picorv32_core.$procmux$10093_CMP |
| 3: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1882$8692_Y |
| 4: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1881$8691_Y |
| 5: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$8683_Y |
| 6: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$8524_Y |
| 7: \soc.cpu.picorv32_core.instr_sw |
| 8: \soc.cpu.picorv32_core.instr_sh |
| 9: \soc.cpu.picorv32_core.instr_sb |
| 10: \soc.cpu.picorv32_core.instr_lw |
| 11: \soc.cpu.picorv32_core.mem_do_wdata |
| 12: \soc.cpu.picorv32_core.mem_do_rdata |
| |
| Output signals: |
| 0: $flatten\soc.\cpu.\picorv32_core.$procmux$11545_CMP |
| 1: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$8710_Y |
| 2: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$8703_Y |
| |
| State encoding: |
| 0: 3'--1 |
| 1: 3'-1- |
| 2: 3'1-- |
| |
| Transition Table (state_in, ctrl_in, state_out, ctrl_out): |
| 0: 0 13'------0---000 -> 0 3'100 |
| 1: 0 13'-------0---10 -> 0 3'100 |
| 2: 0 13'-0---1-1---10 -> 0 3'100 |
| 3: 0 13'-1-----1---10 -> 0 3'100 |
| 4: 0 13'-------0--1-0 -> 0 3'100 |
| 5: 0 13'0-1----1--1-0 -> 0 3'100 |
| 6: 0 13'1------1--1-0 -> 0 3'100 |
| 7: 0 13'------1-----0 -> 0 3'100 |
| 8: 0 13'------------1 -> 0 3'100 |
| 9: 0 13'-0-1---1---10 -> 1 3'100 |
| 10: 0 13'0------11-1-0 -> 1 3'100 |
| 11: 0 13'-0--1--1---10 -> 2 3'100 |
| 12: 0 13'0------1-11-0 -> 2 3'100 |
| 13: 1 13'-0---1-1---10 -> 0 3'001 |
| 14: 1 13'0-1----1--1-0 -> 0 3'001 |
| 15: 1 13'------1-----0 -> 0 3'001 |
| 16: 1 13'------0---000 -> 1 3'001 |
| 17: 1 13'-------0---10 -> 1 3'001 |
| 18: 1 13'-0-1---1---10 -> 1 3'001 |
| 19: 1 13'-1-----1---10 -> 1 3'001 |
| 20: 1 13'0------11-1-0 -> 1 3'001 |
| 21: 1 13'-------0--1-0 -> 1 3'001 |
| 22: 1 13'1------1--1-0 -> 1 3'001 |
| 23: 1 13'------------1 -> 1 3'001 |
| 24: 1 13'-0--1--1---10 -> 2 3'001 |
| 25: 1 13'0------1-11-0 -> 2 3'001 |
| 26: 2 13'-0---1-1---10 -> 0 3'010 |
| 27: 2 13'0-1----1--1-0 -> 0 3'010 |
| 28: 2 13'------1-----0 -> 0 3'010 |
| 29: 2 13'-0-1---1---10 -> 1 3'010 |
| 30: 2 13'0------11-1-0 -> 1 3'010 |
| 31: 2 13'------0---000 -> 2 3'010 |
| 32: 2 13'-------0---10 -> 2 3'010 |
| 33: 2 13'-0--1--1---10 -> 2 3'010 |
| 34: 2 13'-1-----1---10 -> 2 3'010 |
| 35: 2 13'0------1-11-0 -> 2 3'010 |
| 36: 2 13'-------0--1-0 -> 2 3'010 |
| 37: 2 13'1------1--1-0 -> 2 3'010 |
| 38: 2 13'------------1 -> 2 3'010 |
| |
| ------------------------------------- |
| |
| FSM `$fsm$\soc.cpu.state$16409' from module `mgmt_core': |
| ------------------------------------- |
| |
| Information on FSM $fsm$\soc.cpu.state$16409 (\soc.cpu.state): |
| |
| Number of input signals: 3 |
| Number of output signals: 3 |
| Number of state bits: 3 |
| |
| Input signals: |
| 0: \soc.cpu.wb_rst_i |
| 1: \soc.cpu.wbm_ack_i |
| 2: \soc.cpu.picorv32_core.mem_valid |
| |
| Output signals: |
| 0: $flatten\soc.\cpu.$procmux$13540_CMP |
| 1: $flatten\soc.\cpu.$procmux$13544_CMP |
| 2: $flatten\soc.\cpu.$procmux$13631_CMP |
| |
| State encoding: |
| 0: 3'--1 <RESET STATE> |
| 1: 3'-1- |
| 2: 3'1-- |
| |
| Transition Table (state_in, ctrl_in, state_out, ctrl_out): |
| 0: 0 3'0-0 -> 0 3'010 |
| 1: 0 3'--1 -> 0 3'010 |
| 2: 0 3'1-0 -> 2 3'010 |
| 3: 1 3'--- -> 0 3'100 |
| 4: 2 3'--1 -> 0 3'001 |
| 5: 2 3'-10 -> 1 3'001 |
| 6: 2 3'-00 -> 2 3'001 |
| |
| ------------------------------------- |
| |
| FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$16414' from module `mgmt_core': |
| ------------------------------------- |
| |
| Information on FSM $fsm$\soc.simple_spi_master_inst.spi_master.state$16414 (\soc.simple_spi_master_inst.spi_master.state): |
| |
| Number of input signals: 2 |
| Number of output signals: 4 |
| Number of state bits: 4 |
| |
| Input signals: |
| 0: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:303$1993_Y |
| 1: \soc.simple_spi_master_inst.spi_master.w_latched |
| |
| Output signals: |
| 0: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:308$1994_Y |
| 1: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:290$1987_Y |
| 2: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:247$1971_Y |
| 3: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:247$1970_Y |
| |
| State encoding: |
| 0: 4'---1 <RESET STATE> |
| 1: 4'--1- |
| 2: 4'-1-- |
| 3: 4'1--- |
| |
| Transition Table (state_in, ctrl_in, state_out, ctrl_out): |
| 0: 0 2'0- -> 0 4'0010 |
| 1: 0 2'1- -> 2 4'0010 |
| 2: 1 2'-0 -> 2 4'0100 |
| 3: 1 2'-1 -> 3 4'0100 |
| 4: 2 2'-- -> 1 4'1000 |
| 5: 3 2'-- -> 0 4'0001 |
| |
| ------------------------------------- |
| |
| FSM `$fsm$\soc.spimemio.spimemio.state$16420' from module `mgmt_core': |
| ------------------------------------- |
| |
| Information on FSM $fsm$\soc.spimemio.spimemio.state$16420 (\soc.spimemio.spimemio.state): |
| |
| Number of input signals: 8 |
| Number of output signals: 13 |
| Number of state bits: 13 |
| |
| Input signals: |
| 0: \soc.spimemio.spimemio.xfer.din_ready |
| 1: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:511$1829_Y |
| 2: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:471$1825_Y |
| 3: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:372$1811_Y |
| 4: $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:215$1732_Y |
| 5: \soc.spimemio.spimemio.config_cont |
| 6: \soc.spimemio.spimemio.jump |
| 7: \soc.spimemio.spimemio.dout_valid |
| |
| Output signals: |
| 0: $flatten\soc.\spimemio.\spimemio.$procmux$14969_CMP |
| 1: $flatten\soc.\spimemio.\spimemio.$procmux$14966_CMP |
| 2: $flatten\soc.\spimemio.\spimemio.$procmux$14960_CMP |
| 3: $flatten\soc.\spimemio.\spimemio.$procmux$14955_CMP |
| 4: $flatten\soc.\spimemio.\spimemio.$procmux$14952_CMP |
| 5: $flatten\soc.\spimemio.\spimemio.$procmux$14949_CMP |
| 6: $flatten\soc.\spimemio.\spimemio.$procmux$14946_CMP |
| 7: $flatten\soc.\spimemio.\spimemio.$procmux$14943_CMP |
| 8: $flatten\soc.\spimemio.\spimemio.$procmux$14940_CMP |
| 9: $flatten\soc.\spimemio.\spimemio.$procmux$14937_CMP |
| 10: $flatten\soc.\spimemio.\spimemio.$procmux$14907_CMP |
| 11: $flatten\soc.\spimemio.\spimemio.$procmux$14890_CMP |
| 12: $flatten\soc.\spimemio.\spimemio.$procmux$14887_CMP |
| |
| State encoding: |
| 0: 13'------------1 <RESET STATE> |
| 1: 13'-----------1- |
| 2: 13'----------1-- |
| 3: 13'---------1--- |
| 4: 13'--------1---- |
| 5: 13'-------1----- |
| 6: 13'------1------ |
| 7: 13'-----1------- |
| 8: 13'----1-------- |
| 9: 13'---1--------- |
| 10: 13'--1---------- |
| 11: 13'-1----------- |
| 12: 13'1------------ |
| |
| Transition Table (state_in, ctrl_in, state_out, ctrl_out): |
| 0: 0 8'-0--0--0 -> 0 13'0000000000001 |
| 1: 0 8'----1--- -> 0 13'0000000000001 |
| 2: 0 8'-10-0--- -> 2 13'0000000000001 |
| 3: 0 8'-0--0--1 -> 7 13'0000000000001 |
| 4: 0 8'-11-0--- -> 9 13'0000000000001 |
| 5: 1 8'----1--- -> 0 13'0000000100000 |
| 6: 1 8'-0--0--0 -> 1 13'0000000100000 |
| 7: 1 8'-10-0--- -> 2 13'0000000100000 |
| 8: 1 8'-0--0--1 -> 8 13'0000000100000 |
| 9: 1 8'-11-0--- -> 9 13'0000000100000 |
| 10: 2 8'----1--- -> 0 13'0010000000000 |
| 11: 2 8'-0--0--0 -> 2 13'0010000000000 |
| 12: 2 8'-10-0--- -> 2 13'0010000000000 |
| 13: 2 8'-0--0--1 -> 9 13'0010000000000 |
| 14: 2 8'-11-0--- -> 9 13'0010000000000 |
| 15: 3 8'----1--- -> 0 13'0001000000000 |
| 16: 3 8'-10-0--- -> 2 13'0001000000000 |
| 17: 3 8'-0--0-10 -> 3 13'0001000000000 |
| 18: 3 8'-0--0-0- -> 3 13'0001000000000 |
| 19: 3 8'-0--0-11 -> 8 13'0001000000000 |
| 20: 3 8'-11-0--- -> 9 13'0001000000000 |
| 21: 4 8'----1--- -> 0 13'0000000000010 |
| 22: 4 8'-10-0--- -> 2 13'0000000000010 |
| 23: 4 8'-0--0--0 -> 4 13'0000000000010 |
| 24: 4 8'-11-0--- -> 9 13'0000000000010 |
| 25: 4 8'-0--0--1 -> 10 13'0000000000010 |
| 26: 5 8'----1--- -> 0 13'0000010000000 |
| 27: 5 8'-10-0--- -> 2 13'0000010000000 |
| 28: 5 8'-0--0--0 -> 5 13'0000010000000 |
| 29: 5 8'-11-0--- -> 9 13'0000010000000 |
| 30: 5 8'-0--0--1 -> 11 13'0000010000000 |
| 31: 6 8'----1--- -> 0 13'0000000001000 |
| 32: 6 8'-10-0--- -> 2 13'0000000001000 |
| 33: 6 8'-0--0--0 -> 6 13'0000000001000 |
| 34: 6 8'-11-0--- -> 9 13'0000000001000 |
| 35: 6 8'-0--0--1 -> 12 13'0000000001000 |
| 36: 7 8'----1--- -> 0 13'0100000000000 |
| 37: 7 8'-10-0--- -> 2 13'0100000000000 |
| 38: 7 8'10--0--- -> 4 13'0100000000000 |
| 39: 7 8'00--0--- -> 7 13'0100000000000 |
| 40: 7 8'-11-0--- -> 9 13'0100000000000 |
| 41: 8 8'----1--- -> 0 13'0000001000000 |
| 42: 8 8'-10-0--- -> 2 13'0000001000000 |
| 43: 8 8'-0--0--1 -> 5 13'0000001000000 |
| 44: 8 8'-0--0--0 -> 8 13'0000001000000 |
| 45: 8 8'-11-0--- -> 9 13'0000001000000 |
| 46: 9 8'----1--- -> 0 13'0000000000100 |
| 47: 9 8'-10-0--- -> 2 13'0000000000100 |
| 48: 9 8'-0-10--1 -> 6 13'0000000000100 |
| 49: 9 8'-0-10--0 -> 9 13'0000000000100 |
| 50: 9 8'-0-00--- -> 9 13'0000000000100 |
| 51: 9 8'-11-0--- -> 9 13'0000000000100 |
| 52: 10 8'----1--- -> 0 13'1000000000000 |
| 53: 10 8'-10-0--- -> 2 13'1000000000000 |
| 54: 10 8'10--0--- -> 2 13'1000000000000 |
| 55: 10 8'-11-0--- -> 9 13'1000000000000 |
| 56: 10 8'00--0--- -> 10 13'1000000000000 |
| 57: 11 8'----1--- -> 0 13'0000100000000 |
| 58: 11 8'-10-0--- -> 2 13'0000100000000 |
| 59: 11 8'-0--0--1 -> 3 13'0000100000000 |
| 60: 11 8'-11-0--- -> 9 13'0000100000000 |
| 61: 11 8'-0--0--0 -> 11 13'0000100000000 |
| 62: 12 8'----1--- -> 0 13'0000000010000 |
| 63: 12 8'-0--01-1 -> 1 13'0000000010000 |
| 64: 12 8'-10-0--- -> 2 13'0000000010000 |
| 65: 12 8'-0--00-1 -> 8 13'0000000010000 |
| 66: 12 8'-11-0--- -> 9 13'0000000010000 |
| 67: 12 8'-0--0--0 -> 12 13'0000000010000 |
| |
| ------------------------------------- |
| |
| 12.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). |
| Mapping FSM `$fsm$\housekeeping.U1.state$16387' from module `\mgmt_core'. |
| Mapping FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$16394' from module `\mgmt_core'. |
| Mapping FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$16404' from module `\mgmt_core'. |
| Mapping FSM `$fsm$\soc.cpu.state$16409' from module `\mgmt_core'. |
| Mapping FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$16414' from module `\mgmt_core'. |
| Mapping FSM `$fsm$\soc.spimemio.spimemio.state$16420' from module `\mgmt_core'. |
| |
| 12.9. Executing OPT pass (performing simple optimizations). |
| |
| 12.9.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~40 debug messages> |
| |
| 12.9.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| <suppressed ~138 debug messages> |
| Removed a total of 46 cells. |
| |
| 12.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10195. |
| dead port 3/5 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10220. |
| dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10229. |
| dead port 2/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10229. |
| dead port 3/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10229. |
| dead port 4/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10229. |
| dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10234. |
| dead port 2/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10234. |
| dead port 3/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10234. |
| dead port 4/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10234. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10238. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10238. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10241. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10241. |
| dead port 2/7 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9457. |
| dead port 4/7 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9457. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9460. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9460. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9470. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9470. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9511. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9511. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9514. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9514. |
| dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9516. |
| dead port 2/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9516. |
| dead port 3/6 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9704. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9720. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9720. |
| dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9986. |
| dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9986. |
| dead port 1/5 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9988. |
| dead port 2/5 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9988. |
| dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9998. |
| dead port 2/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9998. |
| dead port 3/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9998. |
| Removed 36 multiplexer ports. |
| <suppressed ~586 debug messages> |
| |
| 12.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16337: { \soc.cpu.picorv32_core.cpu_state [5:4] \soc.cpu.picorv32_core.cpu_state [2:0] } |
| New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16335: \soc.cpu.picorv32_core.cpu_state [4:0] |
| New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16333: { \soc.cpu.picorv32_core.cpu_state [5] \soc.cpu.picorv32_core.cpu_state [3:0] } |
| New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16331: { \soc.cpu.picorv32_core.cpu_state [5:2] \soc.cpu.picorv32_core.cpu_state [0] } |
| New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$16329: { \soc.cpu.picorv32_core.cpu_state [5:3] \soc.cpu.picorv32_core.cpu_state [0] } |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 5 changes. |
| |
| 12.9.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 12.9.6. Executing OPT_DFF pass (perform DFF optimizations). |
| Adding SRST signal on $flatten\soc.\wb_bridge.$procdff$16180 ($dff) from module mgmt_core (D = $flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:70$5307_Y, Q = \soc.wb_bridge.wb_ack_read, rval = 2'00). |
| Adding SRST signal on $flatten\soc.\wb_bridge.$procdff$16179 ($dff) from module mgmt_core (D = $flatten\soc.\wb_bridge.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:69$5303_Y, Q = \soc.wb_bridge.wb_ack_o, rval = 2'00). |
| Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$16009 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$12283_Y, Q = \soc.sysctrl.sysctrl.irq_8_inputsrc, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17372 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [1], Q = \soc.sysctrl.sysctrl.irq_8_inputsrc). |
| Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$16008 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$12301_Y, Q = \soc.sysctrl.sysctrl.irq_7_inputsrc, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17382 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.sysctrl.sysctrl.irq_7_inputsrc). |
| Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$16007 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$12317_Y, Q = \soc.sysctrl.sysctrl.trap_output_dest, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17392 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.sysctrl.sysctrl.trap_output_dest). |
| Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$16006 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$12330_Y, Q = \soc.sysctrl.sysctrl.clk2_output_dest, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17400 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [1], Q = \soc.sysctrl.sysctrl.clk2_output_dest). |
| Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$16005 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$12343_Y, Q = \soc.sysctrl.sysctrl.clk1_output_dest, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17406 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.sysctrl.sysctrl.clk1_output_dest). |
| Adding EN signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$16004 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$12348_Y, Q = \soc.sysctrl.sysctrl.iomem_ready). |
| Adding EN signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$16003 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$12362_Y, Q = \soc.sysctrl.sysctrl.iomem_rdata). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$17419 ($dffe) from module mgmt_core (D = 28'xxxxxxxxxxxxxxxxxxxxxxxxxxxx, Q = \soc.sysctrl.sysctrl.iomem_rdata [31:4], rval = 28'0000000000000000000000000000). |
| Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 24 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 25 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 26 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 27 on $auto$opt_dff.cc:702:run$17422 ($sdffce) from module mgmt_core. |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16147 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.fetch, Q = \soc.spimemio.spimemio.xfer.last_fetch, rval = 1'1). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16146 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.next_fetch, Q = \soc.spimemio.spimemio.xfer.fetch, rval = 1'1). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16145 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14523_Y, Q = \soc.spimemio.spimemio.xfer.xfer_tag, rval = 4'0000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17429 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.din_tag, Q = \soc.spimemio.spimemio.xfer.xfer_tag). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16144 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14528_Y, Q = \soc.spimemio.spimemio.xfer.xfer_rd, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17431 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.din_rd, Q = \soc.spimemio.spimemio.xfer.xfer_rd). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16143 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14533_Y, Q = \soc.spimemio.spimemio.xfer.xfer_qspi, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17433 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.din_qspi, Q = \soc.spimemio.spimemio.xfer.xfer_qspi). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16141 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14546_Y, Q = \soc.spimemio.spimemio.xfer.dummy_count, rval = 4'0000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17435 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14546_Y, Q = \soc.spimemio.spimemio.xfer.dummy_count). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16140 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14556_Y [3], Q = \soc.spimemio.spimemio.xfer.count [3], rval = 1'0). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16140 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14554_Y [2:0], Q = \soc.spimemio.spimemio.xfer.count [2:0], rval = 3'000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17442 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$2\next_count[3:0] [2:0], Q = \soc.spimemio.spimemio.xfer.count [2:0]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17439 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14556_Y [3], Q = \soc.spimemio.spimemio.xfer.count [3]). |
| Adding EN signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16139 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$2\next_ibuffer[7:0], Q = \soc.spimemio.spimemio.xfer.ibuffer). |
| Adding EN signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16138 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14574_Y, Q = \soc.spimemio.spimemio.xfer.obuffer). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16137 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14579_Y, Q = \soc.spimemio.spimemio.xfer.xfer_ddr, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17495 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.din_ddr, Q = \soc.spimemio.spimemio.xfer.xfer_ddr). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16136 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14584_Y, Q = \soc.spimemio.spimemio.xfer.xfer_dspi, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17497 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.din_dspi, Q = \soc.spimemio.spimemio.xfer.xfer_dspi). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16135 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14592_Y, Q = \soc.spimemio.spimemio.xfer.flash_clk, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17501 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14592_Y, Q = \soc.spimemio.spimemio.xfer.flash_clk). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16134 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14599_Y, Q = \soc.spimemio.spimemio.xfer.flash_csb, rval = 1'1). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17505 ($sdff) from module mgmt_core (D = 1'0, Q = \soc.spimemio.spimemio.xfer.flash_csb). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16178 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15131_Y, Q = \soc.spimemio.spimemio.config_do, rval = 4'0000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17507 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [3:0], Q = \soc.spimemio.spimemio.config_do). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16177 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15136_Y, Q = \soc.spimemio.spimemio.config_clk, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17509 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [4], Q = \soc.spimemio.spimemio.config_clk). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16176 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15141_Y, Q = \soc.spimemio.spimemio.config_csb, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17511 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [5], Q = \soc.spimemio.spimemio.config_csb). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16175 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15146_Y, Q = \soc.spimemio.spimemio.config_oe, rval = 4'0000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17513 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [11:8], Q = \soc.spimemio.spimemio.config_oe). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16174 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15151_Y, Q = \soc.spimemio.spimemio.config_dummy, rval = 4'1000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17515 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [19:16], Q = \soc.spimemio.spimemio.config_dummy). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16173 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15156_Y, Q = \soc.spimemio.spimemio.config_cont, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17517 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [20], Q = \soc.spimemio.spimemio.config_cont). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16172 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15161_Y, Q = \soc.spimemio.spimemio.config_qspi, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17519 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [21], Q = \soc.spimemio.spimemio.config_qspi). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16171 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15166_Y, Q = \soc.spimemio.spimemio.config_ddr, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17521 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [22], Q = \soc.spimemio.spimemio.config_ddr). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16170 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15171_Y, Q = \soc.spimemio.spimemio.config_en, rval = 1'1). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17523 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31], Q = \soc.spimemio.spimemio.config_en). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16169 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1743_Y, Q = \soc.spimemio.spimemio.softreset, rval = 1'1). |
| Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$16164 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$14908_Y, Q = \soc.spimemio.spimemio.rd_inc). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$17532 ($dffe) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$14896_Y, Q = \soc.spimemio.spimemio.rd_inc, rval = 1'0). |
| Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$16163 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$14915_Y, Q = \soc.spimemio.spimemio.rd_wait). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$17542 ($dffe) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$14913_Y, Q = \soc.spimemio.spimemio.rd_wait, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16162 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$14920_Y, Q = \soc.spimemio.spimemio.rd_valid, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17546 ($sdff) from module mgmt_core (D = 1'1, Q = \soc.spimemio.spimemio.rd_valid). |
| Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$16161 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:387$1822_Y [23:0], Q = \soc.spimemio.spimemio.rd_addr). |
| Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$16160 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.ibuffer, Q = \soc.spimemio.spimemio.buffer [23:16]). |
| Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$16160 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.ibuffer, Q = \soc.spimemio.spimemio.buffer [15:8]). |
| Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$16160 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.ibuffer, Q = \soc.spimemio.spimemio.buffer [7:0]). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16159 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$14979_Y, Q = \soc.spimemio.spimemio.din_rd, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17570 ($sdff) from module mgmt_core (D = 1'1, Q = \soc.spimemio.spimemio.din_rd). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16158 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15000_Y, Q = \soc.spimemio.spimemio.din_ddr, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16157 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15019_Y, Q = \soc.spimemio.spimemio.din_qspi, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16155 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15029_Y, Q = \soc.spimemio.spimemio.din_tag, rval = 4'0000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17576 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15029_Y, Q = \soc.spimemio.spimemio.din_tag). |
| Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$16154 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15048_Y, Q = \soc.spimemio.spimemio.din_data). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16153 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$14936_Y, Q = \soc.spimemio.spimemio.din_valid, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$16152 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$14886_Y, Q = \soc.spimemio.spimemio.xfer_resetn, rval = 1'0). |
| Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$16151 ($dff) from module mgmt_core (D = { \soc.spimemio.spimemio.xfer.ibuffer \soc.spimemio.spimemio.buffer }, Q = \soc.spimemio.spimemio.rdata). |
| Adding SRST signal on $flatten\soc.\soc_mem.$procdff$16078 ($dff) from module mgmt_core (D = $flatten\soc.\soc_mem.$and$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:48$2759_Y, Q = \soc.soc_mem.wb_ack_read, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\soc_mem.$procdff$16077 ($dff) from module mgmt_core (D = $flatten\soc.\soc_mem.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:47$2755_Y, Q = \soc.soc_mem.wb_ack_o, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$16133 ($dff) from module mgmt_core (D = { $flatten\soc.\simpleuart.\simpleuart.$procmux$14492_Y $flatten\soc.\simpleuart.\simpleuart.$procmux$14497_Y $flatten\soc.\simpleuart.\simpleuart.$procmux$14502_Y $flatten\soc.\simpleuart.\simpleuart.$procmux$14507_Y }, Q = \soc.simpleuart.simpleuart.cfg_divider, rval = 1). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17606 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.simpleuart.simpleuart.cfg_divider [7:0]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17606 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.simpleuart.simpleuart.cfg_divider [15:8]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17606 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.simpleuart.simpleuart.cfg_divider [23:16]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17606 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.simpleuart.simpleuart.cfg_divider [31:24]). |
| Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$16132 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$14512_Y, Q = \soc.simpleuart.simpleuart.enabled, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17611 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.simpleuart.simpleuart.enabled). |
| Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$16131 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$14453_Y, Q = \soc.simpleuart.simpleuart.recv_buf_valid, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$16130 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$14461_Y, Q = \soc.simpleuart.simpleuart.recv_buf_data, rval = 8'00000000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17614 ($sdff) from module mgmt_core (D = \soc.simpleuart.simpleuart.recv_pattern, Q = \soc.simpleuart.simpleuart.recv_buf_data). |
| Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$16129 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$14469_Y, Q = \soc.simpleuart.simpleuart.recv_pattern, rval = 8'00000000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17618 ($sdff) from module mgmt_core (D = { \mgmt_in_data [5] \soc.simpleuart.simpleuart.recv_pattern [7:1] }, Q = \soc.simpleuart.simpleuart.recv_pattern). |
| Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$16128 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$14439_Y, Q = \soc.simpleuart.simpleuart.recv_divcnt, rval = 0). |
| Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$16127 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$14481_Y, Q = \soc.simpleuart.simpleuart.recv_state, rval = 4'0000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17625 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$14481_Y, Q = \soc.simpleuart.simpleuart.recv_state). |
| Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$16126 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$14409_Y, Q = \soc.simpleuart.simpleuart.send_dummy, rval = 1'1). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17637 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$14409_Y, Q = \soc.simpleuart.simpleuart.send_dummy). |
| Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$16125 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:193$1923_Y, Q = \soc.simpleuart.simpleuart.send_divcnt, rval = 0). |
| Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$16124 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$14420_Y, Q = \soc.simpleuart.simpleuart.send_bitcnt, rval = 4'0000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17644 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$14420_Y, Q = \soc.simpleuart.simpleuart.send_bitcnt). |
| Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$16123 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$14425_Y [9], Q = \soc.simpleuart.simpleuart.send_pattern [9], rval = 1'1). |
| Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$16123 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$14428_Y [8:0], Q = \soc.simpleuart.simpleuart.send_pattern [8:0], rval = 9'111111111). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17653 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$14428_Y [8:0], Q = \soc.simpleuart.simpleuart.send_pattern [8:0]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17650 ($sdff) from module mgmt_core (D = 1'1, Q = \soc.simpleuart.simpleuart.send_pattern [9]). |
| Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$17657 ($sdffe) from module mgmt_core. |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16122 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15], Q = \soc.simple_spi_master_inst.spi_master.hkconn). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16121 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [11], Q = \soc.simple_spi_master_inst.spi_master.mode). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16120 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12], Q = \soc.simple_spi_master_inst.spi_master.stream). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16119 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [14], Q = \soc.simple_spi_master_inst.spi_master.irqena). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16118 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [8], Q = \soc.simple_spi_master_inst.spi_master.mlb). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16117 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [9], Q = \soc.simple_spi_master_inst.spi_master.invcsb). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16116 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [10], Q = \soc.simple_spi_master_inst.spi_master.invsck). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16115 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.simple_spi_master_inst.spi_master.prescaler). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16114 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [13], Q = \soc.simple_spi_master_inst.spi_master.enable). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16112 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\w_latched[0:0], Q = \soc.simple_spi_master_inst.spi_master.w_latched). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16111 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.simple_spi_master_inst.spi_master.d_latched). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16109 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\nbit[2:0], Q = \soc.simple_spi_master_inst.spi_master.nbit). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16108 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\icsb[0:0], Q = \soc.simple_spi_master_inst.spi_master.icsb). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16107 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\done[0:0], Q = \soc.simple_spi_master_inst.spi_master.done). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16105 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$not$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:329$2001_Y, Q = \soc.simple_spi_master_inst.spi_master.hsck). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16102 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14231_Y, Q = \soc.simple_spi_master_inst.spi_master.rreg). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16101 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\treg[7:0], Q = \soc.simple_spi_master_inst.spi_master.treg). |
| Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$16100 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\isdo[0:0], Q = \soc.simple_spi_master_inst.spi_master.isdo). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16067 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13007_Y, Q = \soc.mprj_ctrl.mprj_ctrl.iomem_ready, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16066 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13014_Y, Q = \soc.mprj_ctrl.mprj_ctrl.iomem_rdata, rval = 0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17723 ($sdff) from module mgmt_core (D = \soc.mprj_ctrl.mprj_ctrl.iomem_rdata_pre, Q = \soc.mprj_ctrl.mprj_ctrl.iomem_rdata). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16065 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12987_Y, Q = \soc.mprj_ctrl.mprj_ctrl.xfer_ctrl, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17731 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.mprj_ctrl.mprj_ctrl.xfer_ctrl). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16064 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13002_Y, Q = \soc.mprj_ctrl.mprj_ctrl.pwr_ctrl_out, rval = 4'0000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17735 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [3:0], Q = \soc.mprj_ctrl.mprj_ctrl.pwr_ctrl_out). |
| Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16061 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12878_Y, Q = \soc.mprj_ctrl.mprj_ctrl.serial_data_staging). |
| Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16060 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\xfer_state[1:0], Q = \soc.mprj_ctrl.mprj_ctrl.xfer_state). |
| Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16059 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\pad_count[5:0], Q = \soc.mprj_ctrl.mprj_ctrl.pad_count). |
| Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16058 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12934_Y, Q = \soc.mprj_ctrl.mprj_ctrl.xfer_count). |
| Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16057 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\serial_resetn[0:0], Q = \soc.mprj_ctrl.mprj_ctrl.serial_resetn). |
| Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16056 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\serial_clock[0:0], Q = \soc.mprj_ctrl.mprj_ctrl.serial_clock). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16055 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12802_Y, Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [31:0], rval = 0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17797 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o, Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [31:0]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16054 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12793_Y, Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [37:32], rval = 6'000000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17801 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [5:0], Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [37:32]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16053 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12784_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[0], rval = 13'1100000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17805 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[0]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16052 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12775_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[1], rval = 13'1100000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17809 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[1]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16051 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12766_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[2], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17813 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[2]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16050 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12757_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[3], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17817 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[3]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16049 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12748_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[4], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17821 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[4]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16048 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12739_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[5], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17825 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[5]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16047 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12730_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[6], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17829 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[6]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16046 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12721_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[7], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17833 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[7]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16045 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12712_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[8], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17837 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[8]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16044 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12703_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[9], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17841 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[9]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16043 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12694_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[10], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17845 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[10]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16042 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12685_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[11], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17849 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[11]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16041 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12676_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[12], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17853 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[12]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16040 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12667_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[13], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17857 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[13]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16039 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12658_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[14], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17861 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[14]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16038 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12649_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[15], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17865 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[15]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16037 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12640_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[16], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17869 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[16]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16036 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12631_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[17], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17873 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[17]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16035 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12622_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[18], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17877 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[18]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16034 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12613_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[19], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17881 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[19]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16033 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12604_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[20], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17885 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[20]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16032 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12595_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[21], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17889 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[21]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16031 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12586_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[22], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17893 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[22]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16030 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12577_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[23], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17897 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[23]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16029 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12568_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[24], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17901 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[24]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16028 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12559_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[25], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17905 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[25]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16027 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12550_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[26], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17909 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[26]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16026 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12541_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[27], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17913 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[27]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16025 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12532_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[28], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17917 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[28]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16024 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12523_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[29], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17921 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[29]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16023 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12514_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[30], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17925 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[30]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16022 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12505_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[31], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17929 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[31]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16021 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12496_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[32], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17933 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[32]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16020 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12487_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[33], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17937 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[33]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16019 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12478_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[34], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17941 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[34]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16018 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12469_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[35], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17945 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[35]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16017 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12460_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[36], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17949 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[36]). |
| Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$16016 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12451_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[37], rval = 13'0010000000011). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17953 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[37]). |
| Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$16002 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$11610_Y $flatten\soc.\la.\la_ctrl.$procmux$11640_Y $flatten\soc.\la.\la_ctrl.$procmux$11670_Y $flatten\soc.\la.\la_ctrl.$procmux$11700_Y }, Q = \soc.la.la_ctrl.la_ena_3, rval = 32'11111111111111111111111111111111). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17957 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_3 [7:0]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17957 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_3 [15:8]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17957 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_3 [23:16]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$17957 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_3 [31:24]). |
| Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$16001 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$12232_Y $flatten\soc.\la.\la_ctrl.$procmux$11728_Y $flatten\soc.\la.\la_ctrl.$procmux$11756_Y $flatten\soc.\la.\la_ctrl.$procmux$11784_Y }, Q = \soc.la.la_ctrl.la_ena_2, rval = 32'11111111111111111111111111111111). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18026 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_2 [7:0]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18026 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_2 [15:8]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18026 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_2 [23:16]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18026 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_2 [31:24]). |
| Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$16000 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$12124_Y $flatten\soc.\la.\la_ctrl.$procmux$11809_Y $flatten\soc.\la.\la_ctrl.$procmux$11834_Y $flatten\soc.\la.\la_ctrl.$procmux$11859_Y }, Q = \soc.la.la_ctrl.la_ena_1, rval = 32'11111111111111111111111111111111). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18087 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_1 [7:0]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18087 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_1 [15:8]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18087 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_1 [23:16]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18087 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_1 [31:24]). |
| Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$15999 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$12146_Y $flatten\soc.\la.\la_ctrl.$procmux$11881_Y $flatten\soc.\la.\la_ctrl.$procmux$11903_Y $flatten\soc.\la.\la_ctrl.$procmux$11925_Y }, Q = \soc.la.la_ctrl.la_ena_0, rval = 32'11111111111111111111111111111111). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18140 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_0 [7:0]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18140 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_0 [15:8]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18140 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_0 [23:16]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18140 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_0 [31:24]). |
| Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$15998 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$12165_Y $flatten\soc.\la.\la_ctrl.$procmux$11944_Y $flatten\soc.\la.\la_ctrl.$procmux$11963_Y $flatten\soc.\la.\la_ctrl.$procmux$11982_Y }, Q = \soc.la.la_ctrl.la_data_3, rval = 0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18185 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_3 [7:0]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18185 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_3 [15:8]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18185 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_3 [23:16]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18185 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_3 [31:24]). |
| Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$15997 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$12181_Y $flatten\soc.\la.\la_ctrl.$procmux$11998_Y $flatten\soc.\la.\la_ctrl.$procmux$12014_Y $flatten\soc.\la.\la_ctrl.$procmux$12030_Y }, Q = \soc.la.la_ctrl.la_data_2, rval = 0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18222 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_2 [7:0]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18222 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_2 [15:8]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18222 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_2 [23:16]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18222 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_2 [31:24]). |
| Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$15996 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$12194_Y $flatten\soc.\la.\la_ctrl.$procmux$12043_Y $flatten\soc.\la.\la_ctrl.$procmux$12056_Y $flatten\soc.\la.\la_ctrl.$procmux$12069_Y }, Q = \soc.la.la_ctrl.la_data_1, rval = 0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18251 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_1 [7:0]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18251 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_1 [15:8]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18251 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_1 [23:16]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18251 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_1 [31:24]). |
| Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$15995 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$12204_Y $flatten\soc.\la.\la_ctrl.$procmux$12079_Y $flatten\soc.\la.\la_ctrl.$procmux$12089_Y $flatten\soc.\la.\la_ctrl.$procmux$12099_Y }, Q = \soc.la.la_ctrl.la_data_0, rval = 0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18272 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_0 [7:0]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18272 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_0 [15:8]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18272 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_0 [23:16]). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18272 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_0 [31:24]). |
| Adding EN signal on $flatten\soc.\la.\la_ctrl.$procdff$15994 ($dff) from module mgmt_core (D = $flatten\soc.\la.\la_ctrl.$procmux$12237_Y, Q = \soc.la.la_ctrl.iomem_ready). |
| Adding EN signal on $flatten\soc.\la.\la_ctrl.$procdff$15993 ($dff) from module mgmt_core (D = $flatten\soc.\la.\la_ctrl.$procmux$12263_Y, Q = \soc.la.la_ctrl.iomem_rdata). |
| Adding EN signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$16015 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12369_Y, Q = \soc.gpio_wb.gpio_ctrl.iomem_ready). |
| Adding EN signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$16014 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12383_Y, Q = \soc.gpio_wb.gpio_ctrl.iomem_rdata). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$18300 ($dffe) from module mgmt_core (D = 30'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, Q = \soc.gpio_wb.gpio_ctrl.iomem_rdata [31:2], rval = 30'000000000000000000000000000000). |
| Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 24 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 25 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 26 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 27 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 28 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Setting constant 0-bit at position 29 on $auto$opt_dff.cc:702:run$18303 ($sdffce) from module mgmt_core. |
| Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$16013 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12403_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio_pd, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18304 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio_pd). |
| Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$16012 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12419_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio_pu, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18314 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio_pu). |
| Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$16011 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12432_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio_oeb, rval = 1'1). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18322 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio_oeb). |
| Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$16010 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12442_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18328 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$16212 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15347_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mulhu, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$16211 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15352_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mulhsu, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$16210 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15358_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mulh, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$16209 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15365_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mul, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$16207 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15295_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.mul_finish, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$16206 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15306_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.mul_waiting, rval = 1'1). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$16205 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15312_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.mul_counter). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$16204 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15318_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rdx). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$18341 ($dffe) from module mgmt_core (D = { \soc.cpu.picorv32_core.pcpi_mul.next_rdx [60] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [56] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [52] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [48] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [44] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [40] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [36] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [32] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [28] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [24] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [20] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [16] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [12] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [8] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [4] }, Q = { \soc.cpu.picorv32_core.pcpi_mul.rdx [60] \soc.cpu.picorv32_core.pcpi_mul.rdx [56] \soc.cpu.picorv32_core.pcpi_mul.rdx [52] \soc.cpu.picorv32_core.pcpi_mul.rdx [48] \soc.cpu.picorv32_core.pcpi_mul.rdx [44] \soc.cpu.picorv32_core.pcpi_mul.rdx [40] \soc.cpu.picorv32_core.pcpi_mul.rdx [36] \soc.cpu.picorv32_core.pcpi_mul.rdx [32] \soc.cpu.picorv32_core.pcpi_mul.rdx [28] \soc.cpu.picorv32_core.pcpi_mul.rdx [24] \soc.cpu.picorv32_core.pcpi_mul.rdx [20] \soc.cpu.picorv32_core.pcpi_mul.rdx [16] \soc.cpu.picorv32_core.pcpi_mul.rdx [12] \soc.cpu.picorv32_core.pcpi_mul.rdx [8] \soc.cpu.picorv32_core.pcpi_mul.rdx [4] }, rval = 15'000000000000000). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$16203 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15324_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rd). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$18343 ($dffe) from module mgmt_core (D = \soc.cpu.picorv32_core.pcpi_mul.next_rd, Q = \soc.cpu.picorv32_core.pcpi_mul.rd, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$16202 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15333_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rs2). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$18345 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [0], Q = \soc.cpu.picorv32_core.pcpi_mul.rs2 [0], rval = 1'0). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$16201 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15342_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rs1). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$18347 ($dffe) from module mgmt_core (D = \soc.cpu.picorv32_core.reg_op1 [31], Q = \soc.cpu.picorv32_core.pcpi_mul.rs1 [63], rval = 1'0). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$16199 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2308$1626_Y [31:0], Q = \soc.cpu.picorv32_core.pcpi_mul.pcpi_rd). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$16195 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15267_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_remu, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$16194 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15272_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_rem, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$16193 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15278_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_divu, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$16192 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15285_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_div, rval = 1'0). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$16189 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2471$1679_Y, Q = \soc.cpu.picorv32_core.pcpi_div.outsign). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$16188 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15222_Y, Q = \soc.cpu.picorv32_core.pcpi_div.running, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18361 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15222_Y, Q = \soc.cpu.picorv32_core.pcpi_div.running). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$16187 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15231_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient_msk). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$18371 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15228_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient_msk, rval = 32'10000000000000000000000000000000). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$16186 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15242_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$18381 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15239_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient, rval = 0). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$16185 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15251_Y, Q = \soc.cpu.picorv32_core.pcpi_div.divisor). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$18389 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15248_Y [30:0], Q = \soc.cpu.picorv32_core.pcpi_div.divisor [30:0], rval = 31'0000000000000000000000000000000). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$16184 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15262_Y, Q = \soc.cpu.picorv32_core.pcpi_div.dividend). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$16181 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15195_Y, Q = \soc.cpu.picorv32_core.pcpi_div.pcpi_wr, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15992 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:397$8150_Y, Q = \soc.cpu.picorv32_core.last_mem_valid, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15991 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$11571_Y, Q = \soc.cpu.picorv32_core.mem_la_firstword_reg, rval = 1'0). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15990 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_rdata_latched [6:0], Q = \soc.cpu.picorv32_core.mem_rdata_q [6:0]). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15988 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$11203_Y, Q = \soc.cpu.picorv32_core.mem_16bit_buffer). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15987 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$11224_Y, Q = \soc.cpu.picorv32_core.prefetched_high_word, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18419 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$11215_Y, Q = \soc.cpu.picorv32_core.prefetched_high_word). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15986 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$11238_Y, Q = \soc.cpu.picorv32_core.mem_la_secondword, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18427 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$11234_Y, Q = \soc.cpu.picorv32_core.mem_la_secondword). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15985 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$0\mem_state[1:0], Q = \soc.cpu.picorv32_core.mem_state). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15984 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$11273_Y, Q = \soc.cpu.picorv32_core.mem_wstrb). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15983 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_la_wdata, Q = \soc.cpu.picorv32_core.mem_wdata). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15982 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_la_addr, Q = \soc.cpu.picorv32_core.mem_addr). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15980 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$0\mem_valid[0:0], Q = \soc.cpu.picorv32_core.mem_valid). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15964 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:862$8229_Y, Q = \soc.cpu.picorv32_core.is_compare, rval = 1'0). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15963 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10606_Y, Q = \soc.cpu.picorv32_core.is_alu_reg_reg). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15962 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10642_Y, Q = \soc.cpu.picorv32_core.is_alu_reg_imm). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15960 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10654_Y, Q = \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18477 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10652_Y, Q = \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15957 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:858$8225_Y, Q = \soc.cpu.picorv32_core.is_lui_auipc_jal_jalr_addi_add_sub, rval = 1'0). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15955 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10667_Y, Q = \soc.cpu.picorv32_core.is_sb_sh_sw). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15954 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1098$8467_Y, Q = \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15953 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1092$8458_Y, Q = \soc.cpu.picorv32_core.is_slli_srli_srai). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15952 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10687_Y, Q = \soc.cpu.picorv32_core.is_lb_lh_lw_lbu_lhu). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15950 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10691_Y, Q = \soc.cpu.picorv32_core.compressed_instr). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15949 ($dff) from module mgmt_core (D = { $flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10737_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10532_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10500_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10520_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10504_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10508_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10516_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10528_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10512_Y 1'0 }, Q = \soc.cpu.picorv32_core.decoded_imm_j). |
| Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$18485 ($dffe) from module mgmt_core. |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15948 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700_Y, Q = \soc.cpu.picorv32_core.decoded_imm). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15947 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10733_Y, Q = \soc.cpu.picorv32_core.decoded_rs2). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15946 ($dff) from module mgmt_core (D = { $flatten\soc.\cpu.\picorv32_core.$procmux$10496_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10583_Y }, Q = \soc.cpu.picorv32_core.decoded_rs1). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15945 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10784_Y, Q = \soc.cpu.picorv32_core.decoded_rd). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15944 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1090$8445_Y, Q = \soc.cpu.picorv32_core.instr_timer). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15943 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:870$8243_Y, Q = \soc.cpu.picorv32_core.instr_waitirq). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15942 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1089$8441_Y, Q = \soc.cpu.picorv32_core.instr_maskirq). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15941 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:869$8239_Y, Q = \soc.cpu.picorv32_core.instr_retirq). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15940 ($dff) from module mgmt_core (D = 1'0, Q = \soc.cpu.picorv32_core.instr_setq). |
| Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$18494 ($dffe) from module mgmt_core. |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15939 ($dff) from module mgmt_core (D = 1'0, Q = \soc.cpu.picorv32_core.instr_getq). |
| Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$18495 ($dffe) from module mgmt_core. |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15938 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1084$8428_Y, Q = \soc.cpu.picorv32_core.instr_ecall_ebreak). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15937 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1082$8418_Y, Q = \soc.cpu.picorv32_core.instr_rdinstrh). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15936 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1081$8414_Y, Q = \soc.cpu.picorv32_core.instr_rdinstr). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15935 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1079$8410_Y, Q = \soc.cpu.picorv32_core.instr_rdcycleh). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15934 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1077$8402_Y, Q = \soc.cpu.picorv32_core.instr_rdcycle). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15933 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10810_Y, Q = \soc.cpu.picorv32_core.instr_and, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18501 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1075$8394_Y, Q = \soc.cpu.picorv32_core.instr_and). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15932 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10814_Y, Q = \soc.cpu.picorv32_core.instr_or, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18503 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1074$8390_Y, Q = \soc.cpu.picorv32_core.instr_or). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15931 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10818_Y, Q = \soc.cpu.picorv32_core.instr_sra, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18505 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1073$8386_Y, Q = \soc.cpu.picorv32_core.instr_sra). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15930 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10822_Y, Q = \soc.cpu.picorv32_core.instr_srl, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18507 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1072$8382_Y, Q = \soc.cpu.picorv32_core.instr_srl). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15929 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10826_Y, Q = \soc.cpu.picorv32_core.instr_xor, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18509 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1071$8378_Y, Q = \soc.cpu.picorv32_core.instr_xor). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15928 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10830_Y, Q = \soc.cpu.picorv32_core.instr_sltu, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18511 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1070$8374_Y, Q = \soc.cpu.picorv32_core.instr_sltu). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15927 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10834_Y, Q = \soc.cpu.picorv32_core.instr_slt, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18513 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1069$8370_Y, Q = \soc.cpu.picorv32_core.instr_slt). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15926 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10838_Y, Q = \soc.cpu.picorv32_core.instr_sll, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18515 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1068$8366_Y, Q = \soc.cpu.picorv32_core.instr_sll). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15925 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10842_Y, Q = \soc.cpu.picorv32_core.instr_sub, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18517 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1067$8362_Y, Q = \soc.cpu.picorv32_core.instr_sub). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15924 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10846_Y, Q = \soc.cpu.picorv32_core.instr_add, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18519 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1066$8358_Y, Q = \soc.cpu.picorv32_core.instr_add). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15923 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1064$8354_Y, Q = \soc.cpu.picorv32_core.instr_srai). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15922 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1063$8350_Y, Q = \soc.cpu.picorv32_core.instr_srli). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15921 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1062$8346_Y, Q = \soc.cpu.picorv32_core.instr_slli). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15920 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10856_Y, Q = \soc.cpu.picorv32_core.instr_andi, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18524 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1060$8342_Y, Q = \soc.cpu.picorv32_core.instr_andi). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15919 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10860_Y, Q = \soc.cpu.picorv32_core.instr_ori, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18526 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1059$8340_Y, Q = \soc.cpu.picorv32_core.instr_ori). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15918 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10864_Y, Q = \soc.cpu.picorv32_core.instr_xori, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18528 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1058$8338_Y, Q = \soc.cpu.picorv32_core.instr_xori). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15917 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10868_Y, Q = \soc.cpu.picorv32_core.instr_sltiu, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18530 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1057$8336_Y, Q = \soc.cpu.picorv32_core.instr_sltiu). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15916 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10872_Y, Q = \soc.cpu.picorv32_core.instr_slti, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18532 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1056$8334_Y, Q = \soc.cpu.picorv32_core.instr_slti). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15915 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10876_Y, Q = \soc.cpu.picorv32_core.instr_addi, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18534 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1055$8332_Y, Q = \soc.cpu.picorv32_core.instr_addi). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15914 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1053$8330_Y, Q = \soc.cpu.picorv32_core.instr_sw). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15913 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1052$8328_Y, Q = \soc.cpu.picorv32_core.instr_sh). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15912 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1051$8326_Y, Q = \soc.cpu.picorv32_core.instr_sb). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15911 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1049$8324_Y, Q = \soc.cpu.picorv32_core.instr_lhu). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15910 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1048$8322_Y, Q = \soc.cpu.picorv32_core.instr_lbu). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15909 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1047$8320_Y, Q = \soc.cpu.picorv32_core.instr_lw). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15908 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1046$8318_Y, Q = \soc.cpu.picorv32_core.instr_lh). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15907 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1045$8316_Y, Q = \soc.cpu.picorv32_core.instr_lb). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15906 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10896_Y, Q = \soc.cpu.picorv32_core.instr_bgeu, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18544 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1043$8314_Y, Q = \soc.cpu.picorv32_core.instr_bgeu). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15905 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10900_Y, Q = \soc.cpu.picorv32_core.instr_bltu, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18546 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1042$8312_Y, Q = \soc.cpu.picorv32_core.instr_bltu). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15904 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10904_Y, Q = \soc.cpu.picorv32_core.instr_bge, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18548 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1041$8310_Y, Q = \soc.cpu.picorv32_core.instr_bge). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15903 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10908_Y, Q = \soc.cpu.picorv32_core.instr_blt, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18550 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1040$8308_Y, Q = \soc.cpu.picorv32_core.instr_blt). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15902 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10912_Y, Q = \soc.cpu.picorv32_core.instr_bne, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18552 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1039$8306_Y, Q = \soc.cpu.picorv32_core.instr_bne). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15901 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10916_Y, Q = \soc.cpu.picorv32_core.instr_beq, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18554 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1038$8304_Y, Q = \soc.cpu.picorv32_core.instr_beq). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15900 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10929_Y, Q = \soc.cpu.picorv32_core.instr_jalr). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15899 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10941_Y, Q = \soc.cpu.picorv32_core.instr_jal). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15898 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:866$8232_Y, Q = \soc.cpu.picorv32_core.instr_auipc). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15897 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10961_Y, Q = \soc.cpu.picorv32_core.instr_lui). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15896 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_rdata_q, Q = \soc.cpu.picorv32_core.pcpi_insn). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15890 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9310_Y, Q = \soc.cpu.picorv32_core.do_waitirq, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15888 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_not$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1424$8557_Y, Q = \soc.cpu.picorv32_core.pcpi_timeout, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15887 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9549_Y, Q = \soc.cpu.picorv32_core.pcpi_timeout_counter, rval = 4'1111). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18569 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$8556_Y [3:0], Q = \soc.cpu.picorv32_core.pcpi_timeout_counter). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15885 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9564_Y, Q = \soc.cpu.picorv32_core.latched_rd, rval = 5'00010). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18571 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9564_Y, Q = \soc.cpu.picorv32_core.latched_rd). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15884 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9590_Y, Q = \soc.cpu.picorv32_core.latched_is_lb, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18579 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9590_Y, Q = \soc.cpu.picorv32_core.latched_is_lb). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15883 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9603_Y, Q = \soc.cpu.picorv32_core.latched_is_lh, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18589 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9603_Y, Q = \soc.cpu.picorv32_core.latched_is_lh). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15882 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9616_Y, Q = \soc.cpu.picorv32_core.latched_is_lu, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18599 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9616_Y, Q = \soc.cpu.picorv32_core.latched_is_lu). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15880 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.compressed_instr, Q = \soc.cpu.picorv32_core.latched_compr). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15879 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9661_Y, Q = \soc.cpu.picorv32_core.latched_branch, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18616 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9661_Y, Q = \soc.cpu.picorv32_core.latched_branch). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15878 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9697_Y, Q = \soc.cpu.picorv32_core.latched_stalu, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18624 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9697_Y, Q = \soc.cpu.picorv32_core.latched_stalu). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15877 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9704_Y, Q = \soc.cpu.picorv32_core.latched_store, rval = 1'1). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18632 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9704_Y, Q = \soc.cpu.picorv32_core.latched_store). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15873 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9762_Y, Q = \soc.cpu.picorv32_core.irq_state, rval = 2'00). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18642 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1535$8602_Y, Q = \soc.cpu.picorv32_core.irq_state). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15866 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9324_Y, Q = \soc.cpu.picorv32_core.decoder_pseudo_trigger, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15863 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9974_Y, Q = \soc.cpu.picorv32_core.mem_do_wdata, rval = 1'1). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18653 ($sdff) from module mgmt_core (D = 1'0, Q = \soc.cpu.picorv32_core.mem_do_wdata). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15862 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9978_Y, Q = \soc.cpu.picorv32_core.mem_do_rdata, rval = 1'1). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18655 ($sdff) from module mgmt_core (D = 1'0, Q = \soc.cpu.picorv32_core.mem_do_rdata). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15861 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10052_Y, Q = \soc.cpu.picorv32_core.mem_do_rinst, rval = 1'1). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18657 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10052_Y, Q = \soc.cpu.picorv32_core.mem_do_rinst). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15860 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10077_Y, Q = \soc.cpu.picorv32_core.mem_do_prefetch, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18669 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1568$8616_Y, Q = \soc.cpu.picorv32_core.mem_do_prefetch). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15858 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10123_Y, Q = \soc.cpu.picorv32_core.timer, rval = 0). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15856 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10141_Y, Q = \soc.cpu.picorv32_core.irq_mask, rval = 32'11111111111111111111111111111111). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18682 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs_rs1, Q = \soc.cpu.picorv32_core.irq_mask). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15855 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10160_Y, Q = \soc.cpu.picorv32_core.irq_active, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18686 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10160_Y, Q = \soc.cpu.picorv32_core.irq_active). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15854 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10185_Y, Q = \soc.cpu.picorv32_core.irq_delay, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18696 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.irq_active, Q = \soc.cpu.picorv32_core.irq_delay). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15852 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9457_Y, Q = \soc.cpu.picorv32_core.reg_out, rval = 1024). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15851 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10198_Y, Q = \soc.cpu.picorv32_core.reg_op2). |
| Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15850 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10220_Y, Q = \soc.cpu.picorv32_core.reg_op1). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15849 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10281_Y, Q = \soc.cpu.picorv32_core.reg_next_pc, rval = 268435456). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18725 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10279_Y, Q = \soc.cpu.picorv32_core.reg_next_pc). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15848 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10293_Y, Q = \soc.cpu.picorv32_core.reg_pc, rval = 268435456). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18727 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0], Q = \soc.cpu.picorv32_core.reg_pc). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15847 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10313_Y, Q = \soc.cpu.picorv32_core.count_instr, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18729 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$8612_Y, Q = \soc.cpu.picorv32_core.count_instr). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15846 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$8558_Y, Q = \soc.cpu.picorv32_core.count_cycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15842 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10357_Y, Q = \soc.cpu.picorv32_core.pcpi_valid, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18738 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10353_Y, Q = \soc.cpu.picorv32_core.pcpi_valid). |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15841 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9543_Y, Q = \soc.cpu.picorv32_core.trap, rval = 1'0). |
| Adding SRST signal on $flatten\soc.\cpu.$procdff$16075 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$13552_Y, Q = \soc.cpu.wbm_cyc_o, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18743 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$13552_Y, Q = \soc.cpu.wbm_cyc_o). |
| Adding SRST signal on $flatten\soc.\cpu.$procdff$16074 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$13565_Y, Q = \soc.cpu.wbm_stb_o, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18751 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$13565_Y, Q = \soc.cpu.wbm_stb_o). |
| Adding SRST signal on $flatten\soc.\cpu.$procdff$16073 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$13580_Y, Q = \soc.cpu.wbm_sel_o, rval = 4'0000). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18759 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_wstrb, Q = \soc.cpu.wbm_sel_o). |
| Adding SRST signal on $flatten\soc.\cpu.$procdff$16072 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$13589_Y, Q = \soc.cpu.wbm_we_o, rval = 1'0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18763 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$13589_Y, Q = \soc.cpu.wbm_we_o). |
| Adding SRST signal on $flatten\soc.\cpu.$procdff$16071 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$13604_Y, Q = \soc.cpu.wbm_dat_o, rval = 0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18771 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_wdata, Q = \soc.cpu.wbm_dat_o). |
| Adding SRST signal on $flatten\soc.\cpu.$procdff$16070 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$13615_Y, Q = \soc.cpu.wbm_adr_o, rval = 0). |
| Adding EN signal on $auto$opt_dff.cc:702:run$18775 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_addr, Q = \soc.cpu.wbm_adr_o). |
| Adding EN signal on $flatten\soc.\cpu.$procdff$16069 ($dff) from module mgmt_core (D = \soc.cpu.wbm_dat_i, Q = \soc.cpu.mem_rdata). |
| Adding EN signal on $flatten\soc.\cpu.$procdff$16068 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$13630_Y, Q = \soc.cpu.mem_ready). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16099 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [3], Q = \soc.counter_timer_1.counter_timer_high_inst.chain). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16098 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [4], Q = \soc.counter_timer_1.counter_timer_high_inst.irq_ena). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16097 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [2], Q = \soc.counter_timer_1.counter_timer_high_inst.updown). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16096 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [1], Q = \soc.counter_timer_1.counter_timer_high_inst.oneshot). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16095 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.counter_timer_1.counter_timer_high_inst.enable). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16094 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.counter_timer_1.counter_timer_high_inst.value_reset [7:0]). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16094 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.counter_timer_1.counter_timer_high_inst.value_reset [15:8]). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16094 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.counter_timer_1.counter_timer_high_inst.value_reset [23:16]). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16094 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.counter_timer_1.counter_timer_high_inst.value_reset [31:24]). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16092 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$0\value_cur[31:0] [7:0], Q = \soc.counter_timer_1.counter_timer_high_inst.value_cur [7:0]). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16092 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$0\value_cur[31:0] [15:8], Q = \soc.counter_timer_1.counter_timer_high_inst.value_cur [15:8]). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16092 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$0\value_cur[31:0] [23:16], Q = \soc.counter_timer_1.counter_timer_high_inst.value_cur [23:16]). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16092 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$0\value_cur[31:0] [31:24], Q = \soc.counter_timer_1.counter_timer_high_inst.value_cur [31:24]). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16091 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$14201_Y, Q = \soc.counter_timer_1.counter_timer_high_inst.stop_out). |
| Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$16090 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:196$2061_Y, Q = \soc.counter_timer_1.counter_timer_high_inst.irq_out). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16089 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [3], Q = \soc.counter_timer_0.counter_timer_low_inst.chain). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16088 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [4], Q = \soc.counter_timer_0.counter_timer_low_inst.irq_ena). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16087 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [2], Q = \soc.counter_timer_0.counter_timer_low_inst.updown). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16086 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [1], Q = \soc.counter_timer_0.counter_timer_low_inst.oneshot). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16085 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.counter_timer_0.counter_timer_low_inst.enable). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16084 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.counter_timer_0.counter_timer_low_inst.value_reset [7:0]). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16084 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.counter_timer_0.counter_timer_low_inst.value_reset [15:8]). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16084 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.counter_timer_0.counter_timer_low_inst.value_reset [23:16]). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16084 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.counter_timer_0.counter_timer_low_inst.value_reset [31:24]). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16082 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$0\value_cur[31:0] [7:0], Q = \soc.counter_timer_0.counter_timer_low_inst.value_cur [7:0]). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16082 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$0\value_cur[31:0] [15:8], Q = \soc.counter_timer_0.counter_timer_low_inst.value_cur [15:8]). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16082 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$0\value_cur[31:0] [23:16], Q = \soc.counter_timer_0.counter_timer_low_inst.value_cur [23:16]). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16082 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$0\value_cur[31:0] [31:24], Q = \soc.counter_timer_0.counter_timer_low_inst.value_cur [31:24]). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16081 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13886_Y, Q = \soc.counter_timer_0.counter_timer_low_inst.stop_out). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16080 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13915_Y, Q = \soc.counter_timer_0.counter_timer_low_inst.strobe). |
| Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$16079 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:203$2122_Y, Q = \soc.counter_timer_0.counter_timer_low_inst.irq_out). |
| Adding EN signal on $flatten\housekeeping.\U1.$procdff$16230 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$procmux$15630_Y, Q = \housekeeping.U1.ldata). |
| Adding EN signal on $flatten\housekeeping.\U1.$procdff$16229 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$0\wrstb[0:0], Q = \housekeeping.U1.wrstb). |
| Adding EN signal on $flatten\housekeeping.\U1.$procdff$16227 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$procmux$15393_Y, Q = \housekeeping.U1.pre_pass_thru_user). |
| Adding EN signal on $flatten\housekeeping.\U1.$procdff$16226 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$procmux$15419_Y, Q = \housekeeping.U1.pre_pass_thru_mgmt). |
| Adding EN signal on $flatten\housekeeping.\U1.$procdff$16225 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata [5:0] \housekeeping.SDI }, Q = \housekeeping.U1.predata). |
| Adding EN signal on $flatten\housekeeping.\U1.$procdff$16224 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$0\fixed[2:0], Q = \housekeeping.U1.fixed). |
| Adding EN signal on $flatten\housekeeping.\U1.$procdff$16223 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.U1.readmode). |
| Adding EN signal on $flatten\housekeeping.\U1.$procdff$16222 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.U1.writemode). |
| Adding EN signal on $flatten\housekeeping.\U1.$procdff$16221 ($adff) from module mgmt_core (D = \housekeeping.U1.pre_pass_thru_user, Q = \housekeeping.U1.pass_thru_user_delay). |
| Adding EN signal on $flatten\housekeeping.\U1.$procdff$16220 ($adff) from module mgmt_core (D = 1'1, Q = \housekeeping.U1.pass_thru_user). |
| Adding EN signal on $flatten\housekeeping.\U1.$procdff$16219 ($adff) from module mgmt_core (D = \housekeeping.U1.pre_pass_thru_mgmt, Q = \housekeeping.U1.pass_thru_mgmt_delay). |
| Adding EN signal on $flatten\housekeeping.\U1.$procdff$16217 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$0\count[2:0], Q = \housekeeping.U1.count). |
| Adding EN signal on $flatten\housekeeping.\U1.$procdff$16216 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$procmux$15560_Y, Q = \housekeeping.U1.addr). |
| Adding EN signal on $flatten\housekeeping.\U1.$procdff$16214 ($adff) from module mgmt_core (D = 1'1, Q = \housekeeping.U1.pass_thru_mgmt). |
| Adding EN signal on $flatten\housekeeping.$procdff$16239 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.reset_reg). |
| Adding EN signal on $flatten\housekeeping.$procdff$16238 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.irq). |
| Adding EN signal on $flatten\housekeeping.$procdff$16237 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.pll_bypass). |
| Adding EN signal on $flatten\housekeeping.$procdff$16236 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata [0] \housekeeping.SDI }, Q = \housekeeping.pll_trim [25:24]). |
| Adding EN signal on $flatten\housekeeping.$procdff$16236 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata \housekeeping.SDI }, Q = \housekeeping.pll_trim [23:16]). |
| Adding EN signal on $flatten\housekeeping.$procdff$16236 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata \housekeeping.SDI }, Q = \housekeeping.pll_trim [15:8]). |
| Adding EN signal on $flatten\housekeeping.$procdff$16236 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata \housekeeping.SDI }, Q = \housekeeping.pll_trim [7:0]). |
| Adding EN signal on $flatten\housekeeping.$procdff$16235 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.pll_ena). |
| Adding EN signal on $flatten\housekeeping.$procdff$16234 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata [3:0] \housekeeping.SDI }, Q = \housekeeping.pll_div). |
| Adding EN signal on $flatten\housekeeping.$procdff$16233 ($adff) from module mgmt_core (D = \housekeeping.U1.predata [4:2], Q = \housekeeping.pll90_sel). |
| Adding EN signal on $flatten\housekeeping.$procdff$16232 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata [1:0] \housekeeping.SDI }, Q = \housekeeping.pll_sel). |
| Adding EN signal on $flatten\housekeeping.$procdff$16231 ($adff) from module mgmt_core (D = \housekeeping.U1.predata [0], Q = \housekeeping.pll_dco_ena). |
| Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$16271 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\out_counter[0:0], Q = \clocking.divider2.odd_0.out_counter). |
| Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$16264 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\counter[2:0], Q = \clocking.divider2.odd_0.counter). |
| Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$16257 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\initial_begin[2:0], Q = \clocking.divider2.odd_0.initial_begin). |
| Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$16256 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\out_counter2[0:0], Q = \clocking.divider2.odd_0.out_counter2). |
| Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$16249 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\counter2[2:0], Q = \clocking.divider2.odd_0.counter2). |
| Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$16248 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$procmux$15760_Y, Q = \clocking.divider2.odd_0.rst_pulse). |
| Adding EN signal on $flatten\clocking.\divider2.\even_0.$procdff$16246 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\even_0.$not$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:187$850_Y, Q = \clocking.divider2.even_0.out_counter). |
| Adding EN signal on $flatten\clocking.\divider2.\even_0.$procdff$16245 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\even_0.$procmux$15755_Y, Q = \clocking.divider2.even_0.counter). |
| Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$16271 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\out_counter[0:0], Q = \clocking.divider.odd_0.out_counter). |
| Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$16264 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\counter[2:0], Q = \clocking.divider.odd_0.counter). |
| Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$16257 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\initial_begin[2:0], Q = \clocking.divider.odd_0.initial_begin). |
| Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$16256 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\out_counter2[0:0], Q = \clocking.divider.odd_0.out_counter2). |
| Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$16249 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\counter2[2:0], Q = \clocking.divider.odd_0.counter2). |
| Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$16248 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$procmux$15760_Y, Q = \clocking.divider.odd_0.rst_pulse). |
| Adding EN signal on $flatten\clocking.\divider.\even_0.$procdff$16246 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\even_0.$not$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:187$850_Y, Q = \clocking.divider.even_0.out_counter). |
| Adding EN signal on $flatten\clocking.\divider.\even_0.$procdff$16245 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\even_0.$procmux$15755_Y, Q = \clocking.divider.even_0.counter). |
| |
| 12.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 933 unused cells and 1005 unused wires. |
| <suppressed ~936 debug messages> |
| |
| 12.9.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~188 debug messages> |
| |
| 12.9.9. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 12.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~344 debug messages> |
| |
| 12.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 0 changes. |
| |
| 12.9.12. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| <suppressed ~771 debug messages> |
| Removed a total of 257 cells. |
| |
| 12.9.13. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 12.9.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 0 unused cells and 372 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 12.9.15. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| |
| 12.9.16. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 12.9.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~345 debug messages> |
| |
| 12.9.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 0 changes. |
| |
| 12.9.19. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 12.9.20. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 12.9.21. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| |
| 12.9.22. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| |
| 12.9.23. Finished OPT passes. (There is nothing left to do.) |
| |
| 12.10. Executing WREDUCE pass (reducing word size of cells). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:190$851 ($sub). |
| Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:190$851 ($sub). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider2.\even_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:183$849 ($eq). |
| Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$15801 ($mux). |
| Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$15793 ($mux). |
| Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$15791 ($mux). |
| Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$15785 ($mux). |
| Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$15776 ($mux). |
| Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$15774 ($mux). |
| Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$15767 ($mux). |
| Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$15764 ($mux). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:109$835 ($eq). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:105$833 ($le). |
| Removed top 1 bits (of 4) from port A of cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:90$830 ($add). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:79$827 ($eq). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:190$851 ($sub). |
| Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:190$851 ($sub). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider.\even_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:183$849 ($eq). |
| Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$15801 ($mux). |
| Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$15793 ($mux). |
| Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$15791 ($mux). |
| Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$15785 ($mux). |
| Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$15776 ($mux). |
| Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$15774 ($mux). |
| Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$15767 ($mux). |
| Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$15764 ($mux). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider.\odd_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:109$835 ($eq). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\clocking.\divider.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:105$833 ($le). |
| Removed top 1 bits (of 4) from port A of cell mgmt_core.$flatten\clocking.\divider.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:90$830 ($add). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider.\odd_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:79$827 ($eq). |
| Removed top 2 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17263 ($eq). |
| Removed top 3 bits (of 7) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17753 ($ne). |
| Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17751 ($ne). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17744 ($ne). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17695 ($ne). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17670 ($ne). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17633 ($ne). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17631 ($ne). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17629 ($ne). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17582 ($ne). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17580 ($ne). |
| Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17451 ($ne). |
| Removed top 3 bits (of 9) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17477 ($ne). |
| Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17298 ($eq). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17344 ($eq). |
| Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17329 ($eq). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17320 ($eq). |
| Removed top 2 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17316 ($eq). |
| Removed top 3 bits (of 6) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17755 ($ne). |
| Removed top 4 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16696 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16704 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16692 ($eq). |
| Removed top 3 bits (of 5) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17761 ($ne). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17765 ($ne). |
| Removed top 3 bits (of 5) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17757 ($ne). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16452 ($eq). |
| Removed top 2 bits (of 4) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17775 ($ne). |
| Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16537 ($eq). |
| Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16533 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16529 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16545 ($eq). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16456 ($eq). |
| Removed top 2 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16712 ($eq). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17048 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17024 ($eq). |
| Removed top 2 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17015 ($eq). |
| Removed top 2 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17003 ($eq). |
| Removed top 2 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16991 ($eq). |
| Removed top 2 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16979 ($eq). |
| Removed top 2 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16967 ($eq). |
| Removed top 2 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16955 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16938 ($eq). |
| Removed top 5 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16934 ($eq). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16926 ($eq). |
| Removed top 5 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16922 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16914 ($eq). |
| Removed top 6 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16910 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16902 ($eq). |
| Removed top 5 bits (of 11) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16898 ($eq). |
| Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16890 ($eq). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16878 ($eq). |
| Removed top 5 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16874 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16869 ($eq). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16865 ($eq). |
| Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16861 ($eq). |
| Removed top 1 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16521 ($eq). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16513 ($eq). |
| Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16505 ($eq). |
| Removed top 3 bits (of 5) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17462 ($ne). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17173 ($eq). |
| Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17171 ($eq). |
| Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17165 ($eq). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17161 ($eq). |
| Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17142 ($eq). |
| Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17136 ($eq). |
| Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17115 ($eq). |
| Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17105 ($eq). |
| Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17084 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17072 ($eq). |
| Removed top 2 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17060 ($eq). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16837 ($eq). |
| Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16818 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16833 ($eq). |
| Removed top 1 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16845 ($eq). |
| Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16841 ($eq). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16814 ($eq). |
| Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16796 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16788 ($eq). |
| Removed top 3 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16780 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16776 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16754 ($eq). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16746 ($eq). |
| Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16738 ($eq). |
| Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16734 ($eq). |
| Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16829 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16853 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16825 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16857 ($eq). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16849 ($eq). |
| Removed top 2 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$17247 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16469 ($eq). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18822 ($ne). |
| Removed top 7 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:42$5007 ($eq). |
| Removed top 6 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:42$5009 ($eq). |
| Removed top 3 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:42$5011 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:42$5013 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:42$5015 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:42$5017 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:42$5019 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:42$5021 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:42$5023 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:42$5025 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:42$5027 ($eq). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18811 ($ne). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:42$5029 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:42$5031 ($eq). |
| Removed top 4 bits (of 8) from port Y of cell mgmt_core.$flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:59$5298 ($and). |
| Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:59$5298 ($and). |
| Removed top 3 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\wb_bridge.$eq$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$5832 ($eq). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18411 ($ne). |
| Removed top 2 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\wb_bridge.$eq$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:88$5838 ($eq). |
| Removed top 2 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\wb_bridge.$eq$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:88$5840 ($eq). |
| Removed top 1 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\wb_bridge.$eq$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:88$5842 ($eq). |
| Removed top 1 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\wb_bridge.$eq$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:88$5844 ($eq). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13464 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13452 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13440 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13428 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13416 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13404 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13392 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13380 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13368 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13356 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13344 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13332 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13320 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13308 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13296 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13284 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13272 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13260 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13248 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13236 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13224 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13212 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13200 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13188 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13176 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13164 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13152 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13140 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13128 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13116 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13104 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13092 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13080 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13068 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13056 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13044 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13032 ($mux). |
| Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$13020 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12972 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12961 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12950 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12939 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12929 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12927 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12922 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12917 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12912 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12904 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12902 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12894 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12892 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12889 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12886 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12883 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12875 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12873 ($mux). |
| Removed top 5 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12846_CMP0 ($eq). |
| Removed top 4 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12845_CMP0 ($eq). |
| Removed top 4 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12844_CMP0 ($eq). |
| Removed top 3 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12843_CMP0 ($eq). |
| Removed top 3 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12842_CMP0 ($eq). |
| Removed top 3 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12841_CMP0 ($eq). |
| Removed top 3 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12840_CMP0 ($eq). |
| Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12839_CMP0 ($eq). |
| Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12838_CMP0 ($eq). |
| Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12837_CMP0 ($eq). |
| Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12836_CMP0 ($eq). |
| Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12835_CMP0 ($eq). |
| Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12834_CMP0 ($eq). |
| Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12833_CMP0 ($eq). |
| Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12832_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12831_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12830_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12829_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12828_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12827_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12826_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12825_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12824_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12823_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12822_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12821_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12820_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12819_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12818_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12817_CMP0 ($eq). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12816_CMP0 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7721 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7716 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7711 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7706 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7701 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7696 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7691 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7686 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7681 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7676 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7671 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7666 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7661 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7656 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7651 ($eq). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7646 ($eq). |
| Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7641 ($eq). |
| Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7636 ($eq). |
| Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7631 ($eq). |
| Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7626 ($eq). |
| Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7621 ($eq). |
| Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7616 ($eq). |
| Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7611 ($eq). |
| Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:158$7606 ($eq). |
| Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:357$7599 ($eq). |
| Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:354$7598 ($eq). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:351$7597 ($eq). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:335$7593 ($add). |
| Removed top 28 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:335$7593 ($add). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:321$7585 ($sub). |
| Removed top 26 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:321$7585 ($sub). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:317$7582 ($eq). |
| Removed top 2 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:211$7563 ($eq). |
| Removed cell mgmt_core.$flatten\soc.\la.\la_ctrl.$procmux$12242 ($mux). |
| Removed top 2 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:137$8049 ($eq). |
| Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:118$8044 ($eq). |
| Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:119$8043 ($eq). |
| Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:120$8042 ($eq). |
| Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:121$8041 ($eq). |
| Removed top 2 bits (of 7) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18807 ($ne). |
| Removed top 28 bits (of 32) from mux cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$12362 ($mux). |
| Removed top 28 bits (of 32) from mux cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$12359 ($mux). |
| Removed top 28 bits (of 32) from mux cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$12356 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$12353 ($mux). |
| Removed top 2 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:127$6637 ($eq). |
| Removed top 30 bits (of 32) from mux cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12383 ($mux). |
| Removed top 30 bits (of 32) from mux cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12380 ($mux). |
| Removed top 30 bits (of 32) from mux cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12377 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12374 ($mux). |
| Removed top 2 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:114$6627 ($eq). |
| Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:104$6622 ($eq). |
| Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:103$6621 ($eq). |
| Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:102$6620 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:38$5859 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:39$5861 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:40$5863 ($eq). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$14148 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$14145 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$14108 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$14096 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$14093 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$14056 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$14044 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$14041 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$14004 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$13992 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$13989 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$13967 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$13952 ($mux). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:167$2048 ($sub). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:166$2047 ($add). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:39$5881 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:40$5883 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:41$5885 ($eq). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13908 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13898 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13832 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13829 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13785 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13782 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13738 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13735 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13691 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13688 ($mux). |
| Removed top 30 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:260$2139 ($eq). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:169$2107 ($sub). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:168$2106 ($add). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:98$5903 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:99$5905 ($eq). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14346 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14343 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14341 ($mux). |
| Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16662 ($eq). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14306 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14302 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14299 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14296 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14288 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14285 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14282 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14278 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14274 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14271 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14249 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$14238 ($mux). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18665 ($ne). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:327$1999 ($add). |
| Removed top 24 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:327$1999 ($add). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:302$1992 ($add). |
| Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:302$1992 ($add). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:50$5921 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:51$5923 ($eq). |
| Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:52$5925 ($eq). |
| Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$14486 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$14483 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$14479 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$14476 ($mux). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$14443_CMP0 ($eq). |
| Removed top 1 bits (of 10) from mux cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$14428 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$14425 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$14414 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$14406 ($mux). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:213$1931 ($sub). |
| Removed top 28 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:213$1931 ($sub). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:193$1923 ($add). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:180$1920 ($add). |
| Removed top 28 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:180$1920 ($add). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:155$1913 ($add). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:632$1842 ($sub). |
| Removed top 1 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:652$1849 ($sub). |
| Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:685$1861 ($sub). |
| Removed top 28 bits (of 32) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:728$1880 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14544 ($mux). |
| Removed top 1 bits (of 4) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14551 ($mux). |
| Removed top 1 bits (of 4) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14554 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14569 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14572 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14589 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14592 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14609 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14611 ($mux). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14613_CMP0 ($eq). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14615 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14620 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14633 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14650 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14652 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14659 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14670 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14684 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14686 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14694 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14706 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14724 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14734 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14744 ($mux). |
| Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18444 ($ne). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18440 ($ne). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18438 ($ne). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18436 ($ne). |
| Removed top 1 bits (of 4) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14828 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14834 ($mux). |
| Removed top 2 bits (of 4) from FF cell mgmt_core.$auto$opt_dff.cc:764:run$17508 ($sdffe). |
| Removed top 3 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16654 ($eq). |
| Removed top 1 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16650 ($eq). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$15063_CMP0 ($eq). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$15057 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$15037 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$15027 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$14913 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$14896 ($mux). |
| Removed top 1 bits (of 8) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:477$1827 ($mux). |
| Removed top 8 bits (of 32) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:387$1822 ($mux). |
| Removed top 1 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$eq$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:385$1818 ($eq). |
| Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$eq$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:384$1816 ($eq). |
| Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$eq$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:383$1814 ($eq). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$eq$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:382$1812 ($eq). |
| Removed top 29 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:215$1733 ($add). |
| Removed top 7 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:215$1733 ($add). |
| Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16620 ($eq). |
| Removed cell mgmt_core.$flatten\soc.\cpu.$procmux$13550 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.$procmux$13632 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.$procmux$13636 ($mux). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2439$1655 ($eq). |
| Removed top 6 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2439$1657 ($eq). |
| Removed top 31 bits (of 63) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1670 ($neg). |
| Removed top 31 bits (of 63) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1672 ($mux). |
| Removed top 31 bits (of 63) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1688 ($sub). |
| Removed top 31 bits (of 63) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1688 ($sub). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15186 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15189 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15192 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15219 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15228 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15236 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15239 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15248 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15256 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15259 ($mux). |
| Removed top 1 bits (of 5) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1614 ($add). |
| Removed top 1 bits (of 5) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1614 ($add). |
| Removed top 26 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2286$1620 ($mux). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1622 ($sub). |
| Removed top 25 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1622 ($sub). |
| Removed top 32 bits (of 64) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2308$1626 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15318 ($mux). |
| Removed top 1 bits (of 64) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15342 ($mux). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15348_CMP0 ($eq). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15353_CMP0 ($eq). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15359_CMP0 ($eq). |
| Removed cell mgmt_core.$auto$opt_dff.cc:764:run$18341 ($dffe). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\cpuregs.$procmux$15808 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\cpuregs.$procmux$15810 ($mux). |
| Removed top 31 bits (of 32) from FF cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\cpuregs.$procdff$16274 ($dff). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18964 ($ne). |
| Removed top 16 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11548 ($pmux). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11542_CMP0 ($eq). |
| Removed top 24 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11539 ($pmux). |
| Removed top 2 bits (of 6) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11523 ($mux). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$19019 ($ne). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11317 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11311 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11308 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11301 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11262 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11256 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11253 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11251 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11247 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11243 ($mux). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11208_CMP0 ($eq). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11201 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11198 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$11196 ($mux). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$19085 ($ne). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10776_CMP0 ($eq). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$19090 ($ne). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$19119 ($ne). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$19124 ($ne). |
| Removed top 2 bits (of 4) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10552 ($mux). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10494_CMP0 ($eq). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10491_CMP0 ($eq). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10489_CMP0 ($eq). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10401 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10226 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10224 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10218 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10216 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10164 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10158 ($mux). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16608 ($eq). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10050 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10002 ($mux). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18833 ($ne). |
| Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16586 ($eq). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16578 ($eq). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18844 ($ne). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9727 ($pmux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9692 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9669 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9614 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9612 ($mux). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18866 ($ne). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9601 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9599 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9588 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9586 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9559 ($mux). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18873 ($ne). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9501 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9498 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9496 ($mux). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18880 ($ne). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9468 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9455 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9453 ($mux). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18887 ($ne). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18914 ($ne). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9195 ($mux). |
| Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9192 ($mux). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18934 ($ne). |
| Removed top 2 bits (of 4) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18954 ($ne). |
| Removed top 2 bits (of 6) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18956 ($ne). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$18962 ($ne). |
| Removed top 1 bits (of 33) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sshr$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1240$8741 ($sshr). |
| Removed top 20 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1911$8696 ($or). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$8612 ($add). |
| Removed top 29 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$8608 ($mux). |
| Removed top 29 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1541$8603 ($mux). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$8600 ($eq). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1438$8563 ($sub). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$8558 ($add). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$8556 ($sub). |
| Removed top 28 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$8556 ($sub). |
| Removed top 29 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$8525 ($mux). |
| Removed top 4 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1090$8444 ($eq). |
| Removed top 5 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1089$8440 ($eq). |
| Removed top 3 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1089$8439 ($eq). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1064$8353 ($eq). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1057$8335 ($eq). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1047$8319 ($eq). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1039$8305 ($eq). |
| Removed top 28 bits (of 32) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$8263 ($add). |
| Removed top 27 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$8263 ($add). |
| Removed top 28 bits (of 32) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$8262 ($add). |
| Removed top 27 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$8262 ($add). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:876$8249 ($eq). |
| Removed top 2 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:875$8248 ($eq). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:874$8247 ($eq). |
| Removed top 5 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:873$8246 ($eq). |
| Removed top 4 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:870$8242 ($eq). |
| Removed top 5 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:869$8238 ($eq). |
| Removed top 3 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:869$8237 ($eq). |
| Removed top 2 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:866$8232 ($eq). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:865$8231 ($eq). |
| Removed top 30 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:617$8212 ($mux). |
| Removed top 1 bits (of 7) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:491$8168 ($mux). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:488$8164 ($eq). |
| Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:486$8162 ($eq). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:478$8160 ($eq). |
| Removed top 3 bits (of 5) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:465$8158 ($eq). |
| Removed top 3 bits (of 4) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$shl$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:419$8153 ($shl). |
| Removed top 16 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:386$8145 ($mux). |
| Removed top 16 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:388$8143 ($mux). |
| Removed top 31 bits (of 32) from mux cell mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:24$3506 ($mux). |
| Removed top 31 bits (of 32) from mux cell mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:23$3508 ($mux). |
| Removed top 31 bits (of 32) from mux cell mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:27$3513 ($mux). |
| Removed top 31 bits (of 32) from mux cell mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:26$3514 ($mux). |
| Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16670 ($eq). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16478 ($eq). |
| Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16487 ($eq). |
| Removed top 4 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16444 ($eq). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16448 ($eq). |
| Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16570 ($eq). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:419$3609 ($add). |
| Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:419$3609 ($add). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:422$3611 ($eq). |
| Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:458$3625 ($eq). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:461$3627 ($sub). |
| Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:461$3627 ($sub). |
| Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3628 ($add). |
| Removed top 24 bits (of 32) from port Y of cell mgmt_core.$flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3628 ($add). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15388 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15390 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15413 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15416 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15444 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15447 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15449 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15451 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15454 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15458 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15461 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15464 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15539 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15542 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15545 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15553 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15555 ($mux). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15557 ($mux). |
| Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16566 ($eq). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16557 ($eq). |
| Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$15640 ($mux). |
| Removed top 3 bits (of 8) from mux cell mgmt_core.$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$3570 ($mux). |
| Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$3569 ($eq). |
| Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$3568 ($eq). |
| Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:190$3567 ($eq). |
| Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:189$3566 ($eq). |
| Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:188$3565 ($eq). |
| Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:187$3564 ($eq). |
| Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:186$3563 ($eq). |
| Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:185$3562 ($eq). |
| Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:184$3561 ($eq). |
| Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:183$3560 ($eq). |
| Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:182$3559 ($eq). |
| Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:180$3558 ($eq). |
| Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:179$3557 ($eq). |
| Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:178$3556 ($eq). |
| Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:177$3555 ($eq). |
| Removed top 6 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:176$3554 ($eq). |
| Removed top 6 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:175$3553 ($eq). |
| Removed top 7 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:174$3552 ($eq). |
| Removed top 1 bits (of 2) from port Y of cell mgmt_core.$flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:58$5297 ($and). |
| Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:58$5297 ($and). |
| Removed top 7 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$ne$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:215$1734 ($ne). |
| Removed top 31 bits (of 63) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1670 ($neg). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1599 ($add). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1601 ($add). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1603 ($add). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1605 ($add). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1607 ($add). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1609 ($add). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1611 ($add). |
| Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1613 ($add). |
| Removed top 1 bits (of 5) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1613 ($add). |
| Removed top 1 bits (of 64) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15340 ($mux). |
| Removed top 29 bits (of 32) from wire mgmt_core.$flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:190$851_Y. |
| Removed top 29 bits (of 32) from wire mgmt_core.$flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:190$851_Y. |
| Removed top 3 bits (of 8) from wire mgmt_core.$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$3570_Y. |
| Removed top 31 bits (of 32) from wire mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:24$3506_Y. |
| Removed top 31 bits (of 32) from wire mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:27$3513_Y. |
| Removed top 16 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$2\mem_rdata_word[31:0]. |
| Removed top 24 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$3\mem_rdata_word[31:0]. |
| Removed top 27 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$8262_Y. |
| Removed top 27 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$8263_Y. |
| Removed top 2 bits (of 4) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10552_Y. |
| Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$8556_Y. |
| Removed top 29 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$8525_Y. |
| Removed top 29 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1541$8603_Y. |
| Removed top 29 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$8608_Y. |
| Removed top 1 bits (of 7) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:491$8168_Y. |
| Removed top 31 bits (of 63) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1670_Y. |
| Removed top 1 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15228_Y. |
| Removed top 1 bits (of 63) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$15248_Y. |
| Removed top 1 bits (of 5) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1613_Y. |
| Removed top 1 bits (of 64) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15340_Y. |
| Removed top 1 bits (of 64) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15342_Y. |
| Removed top 25 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1622_Y. |
| Removed top 26 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2286$1620_Y. |
| Removed top 32 bits (of 64) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2308$1626_Y. |
| Removed top 30 bits (of 32) from wire mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12377_Y. |
| Removed top 30 bits (of 32) from wire mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12380_Y. |
| Removed top 30 bits (of 32) from wire mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12383_Y. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$10\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$11\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$12\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$13\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$14\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$15\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$16\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$17\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$18\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$19\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$20\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$21\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$22\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$23\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$24\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$25\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$26\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$27\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$28\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$29\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$30\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$31\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$32\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$33\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$34\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$35\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$36\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$37\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$38\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$39\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$40\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$41\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$42\iomem_rdata_pre[31:0]. |
| Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$43\iomem_rdata_pre[31:0]. |
| Removed top 24 bits (of 32) from wire mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:327$1999_Y. |
| Removed top 2 bits (of 10) from wire mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$14425_Y. |
| Removed top 1 bits (of 10) from wire mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$14428_Y. |
| Removed top 7 bits (of 32) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:215$1733_Y. |
| Removed top 8 bits (of 32) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:387$1822_Y. |
| Removed top 1 bits (of 8) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:477$1827_Y. |
| Removed top 3 bits (of 4) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:632$1841_Y. |
| Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:728$1880_Y. |
| Removed top 30 bits (of 32) from wire mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$12353_Y. |
| Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$12356_Y. |
| Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$12359_Y. |
| Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$12362_Y. |
| |
| 12.11. Executing PEEPOPT pass (run peephole optimizers). |
| |
| 12.12. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 1 unused cells and 262 unused wires. |
| <suppressed ~2 debug messages> |
| |
| 12.13. Executing ALUMACC pass (create $alu and $macc cells). |
| Extracting $alu and $macc cells in module mgmt_core: |
| creating $macc model for $flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:190$851 ($sub). |
| creating $macc model for $flatten\clocking.\divider.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:90$830 ($add). |
| creating $macc model for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:113$837 ($sub). |
| creating $macc model for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:116$838 ($sub). |
| creating $macc model for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:83$829 ($sub). |
| creating $macc model for $flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:190$851 ($sub). |
| creating $macc model for $flatten\clocking.\divider2.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:90$830 ($add). |
| creating $macc model for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:113$837 ($sub). |
| creating $macc model for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:116$838 ($sub). |
| creating $macc model for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:83$829 ($sub). |
| creating $macc model for $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:419$3609 ($add). |
| creating $macc model for $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3628 ($add). |
| creating $macc model for $flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:461$3627 ($sub). |
| creating $macc model for $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:168$2106 ($add). |
| creating $macc model for $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:169$2107 ($sub). |
| creating $macc model for $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:166$2047 ($add). |
| creating $macc model for $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:167$2048 ($sub). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$8733 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$8526 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$8558 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$8609 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$8612 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$8613 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1801$8660 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1864$8685 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$8136 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$8262 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$8263 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$8732 ($sub). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$8556 ($sub). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1438$8563 ($sub). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2469$1665 ($neg). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1670 ($neg). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2488$1683 ($neg). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2490$1685 ($neg). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1688 ($sub). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1583 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1584 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1585 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1586 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1587 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1588 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1589 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1590 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1591 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1592 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1593 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1594 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1595 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1596 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1597 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1598 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1599 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1600 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1601 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1602 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1603 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1604 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1605 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1606 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1607 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1608 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1609 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1610 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1611 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1612 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1613 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1614 ($add). |
| creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1622 ($sub). |
| creating $macc model for $flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:335$7593 ($add). |
| creating $macc model for $flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:321$7585 ($sub). |
| creating $macc model for $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:302$1992 ($add). |
| creating $macc model for $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:327$1999 ($add). |
| creating $macc model for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:155$1913 ($add). |
| creating $macc model for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:180$1920 ($add). |
| creating $macc model for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:193$1923 ($add). |
| creating $macc model for $flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:213$1931 ($sub). |
| creating $macc model for $flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:215$1733 ($add). |
| creating $macc model for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:632$1842 ($sub). |
| creating $macc model for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:652$1849 ($sub). |
| creating $macc model for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:685$1861 ($sub). |
| creating $macc model for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:715$1873 ($sub). |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1613 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1614. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1611 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1612. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1609 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1610. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1607 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1608. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1605 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1606. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1603 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1604. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1601 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1602. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1599 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1600. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1597 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1598. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1595 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1596. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1593 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1594. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1591 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1592. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1589 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1590. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1587 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1588. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1585 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1586. |
| merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1583 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1584. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1612. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1614. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1610. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1622. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1608. |
| creating $alu model for $macc $flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:335$7593. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1606. |
| creating $alu model for $macc $flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:321$7585. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1604. |
| creating $alu model for $macc $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:302$1992. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1602. |
| creating $alu model for $macc $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:327$1999. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1600. |
| creating $alu model for $macc $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:155$1913. |
| creating $alu model for $macc $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:180$1920. |
| creating $alu model for $macc $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:193$1923. |
| creating $alu model for $macc $flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:213$1931. |
| creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:215$1733. |
| creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:632$1842. |
| creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:652$1849. |
| creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:685$1861. |
| creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:715$1873. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1688. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2490$1685. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2488$1683. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1670. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2469$1665. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1438$8563. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$8556. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$8732. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$8263. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$8262. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$8136. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1864$8685. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1801$8660. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$8613. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$8612. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$8609. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$8558. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$8526. |
| creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$8733. |
| creating $alu model for $macc $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:167$2048. |
| creating $alu model for $macc $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:166$2047. |
| creating $alu model for $macc $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:169$2107. |
| creating $alu model for $macc $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:168$2106. |
| creating $alu model for $macc $flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:461$3627. |
| creating $alu model for $macc $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3628. |
| creating $alu model for $macc $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:419$3609. |
| creating $alu model for $macc $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:83$829. |
| creating $alu model for $macc $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:116$838. |
| creating $alu model for $macc $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:113$837. |
| creating $alu model for $macc $flatten\clocking.\divider2.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:90$830. |
| creating $alu model for $macc $flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:190$851. |
| creating $alu model for $macc $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:83$829. |
| creating $alu model for $macc $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:116$838. |
| creating $alu model for $macc $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:113$837. |
| creating $alu model for $macc $flatten\clocking.\divider.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:90$830. |
| creating $alu model for $macc $flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:190$851. |
| creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1590: $auto$alumacc.cc:365:replace_macc$19213 |
| creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1598: $auto$alumacc.cc:365:replace_macc$19214 |
| creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1584: $auto$alumacc.cc:365:replace_macc$19215 |
| creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1592: $auto$alumacc.cc:365:replace_macc$19216 |
| creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1588: $auto$alumacc.cc:365:replace_macc$19217 |
| creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1594: $auto$alumacc.cc:365:replace_macc$19218 |
| creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1586: $auto$alumacc.cc:365:replace_macc$19219 |
| creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1596: $auto$alumacc.cc:365:replace_macc$19220 |
| creating $alu model for $flatten\clocking.\divider.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:105$833 ($le): new $alu |
| creating $alu model for $flatten\clocking.\divider2.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:105$833 ($le): new $alu |
| creating $alu model for $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:424$3612 ($lt): new $alu |
| creating $alu model for $flatten\soc.\cpu.\picorv32_core.$lt$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1237$8736 ($lt): new $alu |
| creating $alu model for $flatten\soc.\cpu.\picorv32_core.$lt$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1238$8737 ($lt): new $alu |
| creating $alu model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$le$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2493$1687 ($le): new $alu |
| creating $alu model for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:165$1917 ($gt): new $alu |
| creating $alu model for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:171$1918 ($gt): new $alu |
| creating $alu model for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:211$1929 ($gt): new $alu |
| creating $alu model for $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:426$3613 ($eq): merged with $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:424$3612. |
| creating $alu model for $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1236$8735 ($eq): merged with $flatten\soc.\cpu.\picorv32_core.$lt$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1238$8737. |
| creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:211$1929: $auto$alumacc.cc:485:replace_alu$19230 |
| creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:171$1918: $auto$alumacc.cc:485:replace_alu$19241 |
| creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:165$1917: $auto$alumacc.cc:485:replace_alu$19252 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$le$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2493$1687: $auto$alumacc.cc:485:replace_alu$19257 |
| creating $alu cell for $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:424$3612, $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:426$3613: $auto$alumacc.cc:485:replace_alu$19270 |
| creating $alu cell for $flatten\clocking.\divider2.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:105$833: $auto$alumacc.cc:485:replace_alu$19277 |
| creating $alu cell for $flatten\clocking.\divider.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:105$833: $auto$alumacc.cc:485:replace_alu$19290 |
| creating $alu cell for $flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:190$851: $auto$alumacc.cc:485:replace_alu$19303 |
| creating $alu cell for $flatten\clocking.\divider.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:90$830: $auto$alumacc.cc:485:replace_alu$19306 |
| creating $alu cell for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:113$837: $auto$alumacc.cc:485:replace_alu$19309 |
| creating $alu cell for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:116$838: $auto$alumacc.cc:485:replace_alu$19312 |
| creating $alu cell for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:83$829: $auto$alumacc.cc:485:replace_alu$19315 |
| creating $alu cell for $flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:190$851: $auto$alumacc.cc:485:replace_alu$19318 |
| creating $alu cell for $flatten\clocking.\divider2.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:90$830: $auto$alumacc.cc:485:replace_alu$19321 |
| creating $alu cell for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:113$837: $auto$alumacc.cc:485:replace_alu$19324 |
| creating $alu cell for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:116$838: $auto$alumacc.cc:485:replace_alu$19327 |
| creating $alu cell for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:83$829: $auto$alumacc.cc:485:replace_alu$19330 |
| creating $alu cell for $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:419$3609: $auto$alumacc.cc:485:replace_alu$19333 |
| creating $alu cell for $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3628: $auto$alumacc.cc:485:replace_alu$19336 |
| creating $alu cell for $flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:461$3627: $auto$alumacc.cc:485:replace_alu$19339 |
| creating $alu cell for $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:168$2106: $auto$alumacc.cc:485:replace_alu$19342 |
| creating $alu cell for $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:169$2107: $auto$alumacc.cc:485:replace_alu$19345 |
| creating $alu cell for $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:166$2047: $auto$alumacc.cc:485:replace_alu$19348 |
| creating $alu cell for $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:167$2048: $auto$alumacc.cc:485:replace_alu$19351 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$lt$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1238$8737, $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1236$8735: $auto$alumacc.cc:485:replace_alu$19354 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$lt$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1237$8736: $auto$alumacc.cc:485:replace_alu$19365 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$8733: $auto$alumacc.cc:485:replace_alu$19378 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$8526: $auto$alumacc.cc:485:replace_alu$19381 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$8558: $auto$alumacc.cc:485:replace_alu$19384 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$8609: $auto$alumacc.cc:485:replace_alu$19387 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$8612: $auto$alumacc.cc:485:replace_alu$19390 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$8613: $auto$alumacc.cc:485:replace_alu$19393 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1801$8660: $auto$alumacc.cc:485:replace_alu$19396 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1864$8685: $auto$alumacc.cc:485:replace_alu$19399 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$8136: $auto$alumacc.cc:485:replace_alu$19402 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$8262: $auto$alumacc.cc:485:replace_alu$19405 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$8263: $auto$alumacc.cc:485:replace_alu$19408 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$8732: $auto$alumacc.cc:485:replace_alu$19411 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$8556: $auto$alumacc.cc:485:replace_alu$19414 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1438$8563: $auto$alumacc.cc:485:replace_alu$19417 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2469$1665: $auto$alumacc.cc:485:replace_alu$19420 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1670: $auto$alumacc.cc:485:replace_alu$19423 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2488$1683: $auto$alumacc.cc:485:replace_alu$19426 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2490$1685: $auto$alumacc.cc:485:replace_alu$19429 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1688: $auto$alumacc.cc:485:replace_alu$19432 |
| creating $alu cell for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:715$1873: $auto$alumacc.cc:485:replace_alu$19435 |
| creating $alu cell for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:685$1861: $auto$alumacc.cc:485:replace_alu$19438 |
| creating $alu cell for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:652$1849: $auto$alumacc.cc:485:replace_alu$19441 |
| creating $alu cell for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:632$1842: $auto$alumacc.cc:485:replace_alu$19444 |
| creating $alu cell for $flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:215$1733: $auto$alumacc.cc:485:replace_alu$19447 |
| creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:213$1931: $auto$alumacc.cc:485:replace_alu$19450 |
| creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:193$1923: $auto$alumacc.cc:485:replace_alu$19453 |
| creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:180$1920: $auto$alumacc.cc:485:replace_alu$19456 |
| creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:155$1913: $auto$alumacc.cc:485:replace_alu$19459 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1600: $auto$alumacc.cc:485:replace_alu$19462 |
| creating $alu cell for $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:327$1999: $auto$alumacc.cc:485:replace_alu$19465 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1602: $auto$alumacc.cc:485:replace_alu$19468 |
| creating $alu cell for $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:302$1992: $auto$alumacc.cc:485:replace_alu$19471 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1604: $auto$alumacc.cc:485:replace_alu$19474 |
| creating $alu cell for $flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:321$7585: $auto$alumacc.cc:485:replace_alu$19477 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1606: $auto$alumacc.cc:485:replace_alu$19480 |
| creating $alu cell for $flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:335$7593: $auto$alumacc.cc:485:replace_alu$19483 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1608: $auto$alumacc.cc:485:replace_alu$19486 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1622: $auto$alumacc.cc:485:replace_alu$19489 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1610: $auto$alumacc.cc:485:replace_alu$19492 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1614: $auto$alumacc.cc:485:replace_alu$19495 |
| creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1612: $auto$alumacc.cc:485:replace_alu$19498 |
| created 67 $alu and 8 $macc cells. |
| |
| 12.14. Executing SHARE pass (SAT-based resource sharing). |
| Found 4 cells in module mgmt_core that may be considered for resource sharing. |
| Analyzing resource sharing options for $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:858$3533 ($memrd): |
| Found 1 activation_patterns using ctrl signal { $auto$opt_reduce.cc:134:opt_mux$16280 \soc.cpu.picorv32_core.is_lui_auipc_jal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1386$8540_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10015_CTRL }. |
| Found 1 candidates: $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:857$3532 |
| Analyzing resource sharing with $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:857$3532 ($memrd): |
| Found 1 activation_patterns using ctrl signal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1385$8538_Y. |
| Activation pattern for cell $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:858$3533: { $auto$opt_reduce.cc:134:opt_mux$16280 \soc.cpu.picorv32_core.is_lui_auipc_jal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1386$8540_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10015_CTRL } = 4'0010 |
| Activation pattern for cell $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:857$3532: $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1385$8538_Y = 1'1 |
| Adding exclusive control bits: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$8637_Y vs. \soc.cpu.picorv32_core.instr_trap |
| Adding exclusive control bits: $flatten\soc.\cpu.\picorv32_core.$procmux$10015_CTRL vs. $auto$opt_reduce.cc:134:opt_mux$16280 |
| Adding exclusive control bits: $flatten\soc.\cpu.\picorv32_core.$procmux$10015_CTRL vs. \soc.cpu.picorv32_core.is_lui_auipc_jal |
| Adding exclusive control bits: \soc.cpu.picorv32_core.is_lui_auipc_jal vs. $auto$opt_reduce.cc:134:opt_mux$16280 |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bgeu vs. \soc.cpu.picorv32_core.instr_bge |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bgeu vs. \soc.cpu.picorv32_core.instr_bne |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bgeu vs. \soc.cpu.picorv32_core.instr_beq |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bge vs. \soc.cpu.picorv32_core.instr_bne |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bge vs. \soc.cpu.picorv32_core.instr_beq |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bne vs. \soc.cpu.picorv32_core.instr_beq |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_timer vs. \soc.cpu.picorv32_core.instr_maskirq |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_timer vs. \soc.cpu.picorv32_core.instr_retirq |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_maskirq vs. \soc.cpu.picorv32_core.instr_retirq |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_trap vs. \soc.cpu.picorv32_core.instr_timer |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_trap vs. \soc.cpu.picorv32_core.instr_maskirq |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_trap vs. \soc.cpu.picorv32_core.instr_retirq |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstrh vs. \soc.cpu.picorv32_core.instr_rdinstr |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstrh vs. \soc.cpu.picorv32_core.instr_rdcycleh |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstrh vs. \soc.cpu.picorv32_core.instr_rdcycle |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstr vs. \soc.cpu.picorv32_core.instr_rdcycleh |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstr vs. \soc.cpu.picorv32_core.instr_rdcycle |
| Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdcycleh vs. \soc.cpu.picorv32_core.instr_rdcycle |
| Size of SAT problem: 7 cells, 133 variables, 287 clauses |
| According to the SAT solver this pair of cells can not be shared. |
| Model from SAT solver: { $auto$opt_reduce.cc:134:opt_mux$16280 \soc.cpu.picorv32_core.is_lui_auipc_jal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1385$8538_Y $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1386$8540_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10015_CTRL } = 5'00110 |
| Analyzing resource sharing options for $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:857$3532 ($memrd): |
| Found 1 activation_patterns using ctrl signal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1385$8538_Y. |
| No candidates found. |
| Analyzing resource sharing options for $flatten\soc.\cpu.\picorv32_core.$sshr$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1240$8741 ($sshr): |
| Found 1 activation_patterns using ctrl signal $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1277$8516_Y. |
| No candidates found. |
| Analyzing resource sharing options for $flatten\soc.\cpu.\picorv32_core.$shl$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1239$8738 ($shl): |
| Found 1 activation_patterns using ctrl signal $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1275$8512_Y. |
| No candidates found. |
| |
| 12.15. Executing OPT pass (performing simple optimizations). |
| |
| 12.15.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~10 debug messages> |
| |
| 12.15.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| <suppressed ~3 debug messages> |
| Removed a total of 1 cells. |
| |
| 12.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~332 debug messages> |
| |
| 12.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.$procmux$13630: { \soc.cpu.state [2] $auto$opt_reduce.cc:134:opt_mux$19502 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10014: { $auto$opt_reduce.cc:134:opt_mux$16278 $auto$opt_reduce.cc:134:opt_mux$19504 $auto$opt_reduce.cc:134:opt_mux$16276 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10220: { \soc.cpu.picorv32_core.cpu_state [2] $auto$opt_reduce.cc:134:opt_mux$19506 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11245: { $flatten\soc.\cpu.\picorv32_core.$logic_not$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:379$8116_Y $flatten\soc.\cpu.\picorv32_core.$procmux$11208_CMP $auto$opt_reduce.cc:134:opt_mux$19508 } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9704: { \soc.cpu.picorv32_core.cpu_state [1] \soc.cpu.picorv32_core.cpu_state [3] $auto$opt_reduce.cc:134:opt_mux$19510 } |
| New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$15029: { $auto$opt_reduce.cc:134:opt_mux$19512 \soc.spimemio.spimemio.state [8] \soc.spimemio.spimemio.state [5] \soc.spimemio.spimemio.state [11] \soc.spimemio.spimemio.state [3] } |
| New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14736: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14614_CMP $auto$opt_reduce.cc:134:opt_mux$19514 } |
| New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14746: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14614_CMP $auto$opt_reduce.cc:134:opt_mux$19516 } |
| New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$19511: { \soc.spimemio.spimemio.state [12] \soc.spimemio.spimemio.state [9] \soc.spimemio.spimemio.state [6] \soc.spimemio.spimemio.state [4] \soc.spimemio.spimemio.state [2:0] } |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 9 changes. |
| |
| 12.15.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| <suppressed ~9 debug messages> |
| Removed a total of 3 cells. |
| |
| 12.15.6. Executing OPT_DFF pass (perform DFF optimizations). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$18471 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$11303_Y, Q = \soc.cpu.picorv32_core.mem_valid, rval = 1'0). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$18447 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$11245_Y, Q = \soc.cpu.picorv32_core.mem_state, rval = 2'00). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$18389 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$shl$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1673_Y [62], Q = \soc.cpu.picorv32_core.pcpi_div.divisor [62], rval = 1'0). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$18340 ($dffe) from module mgmt_core (D = $auto$wreduce.cc:454:run$19161 [6], Q = \soc.cpu.picorv32_core.pcpi_mul.mul_counter [6], rval = 1'0). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$17749 ($dffe) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$4$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$7549_DATA[12:0]$7587 [0], Q = \soc.mprj_ctrl.mprj_ctrl.serial_data_staging [0], rval = 1'0). |
| |
| 12.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 17 unused cells and 39 unused wires. |
| <suppressed ~19 debug messages> |
| |
| 12.15.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| |
| 12.15.9. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 12.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~334 debug messages> |
| |
| 12.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 0 changes. |
| |
| 12.15.12. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 12.15.13. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 12.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| |
| 12.15.15. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| |
| 12.15.16. Finished OPT passes. (There is nothing left to do.) |
| |
| 12.16. Executing MEMORY pass. |
| |
| 12.16.1. Executing OPT_MEM pass (optimize memories). |
| Performed a total of 0 transformations. |
| |
| 12.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). |
| Checking cell `$flatten\soc.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:0$3534' in module `\mgmt_core': merged $dff to cell. |
| Checking cell `$flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:857$3532' in module `\mgmt_core': merged address $dff to cell. |
| Checking cell `$flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:858$3533' in module `\mgmt_core': merged address $dff to cell. |
| |
| 12.16.3. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 3 unused cells and 3 unused wires. |
| <suppressed ~4 debug messages> |
| |
| 12.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). |
| |
| 12.16.5. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| |
| 12.16.6. Executing MEMORY_COLLECT pass (generating $mem cells). |
| Collecting $memrd, $memwr and $meminit for memory `\soc.cpu.picorv32_core.cpuregs.regs' in module `\mgmt_core': |
| $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:0$3534 ($memwr) |
| $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:858$3533 ($memrd) |
| $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:857$3532 ($memrd) |
| |
| 12.17. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| |
| 12.18. Executing OPT pass (performing simple optimizations). |
| |
| 12.18.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~382 debug messages> |
| |
| 12.18.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| <suppressed ~9 debug messages> |
| Removed a total of 3 cells. |
| |
| 12.18.3. Executing OPT_DFF pass (perform DFF optimizations). |
| Adding EN signal on $auto$opt_dff.cc:764:run$17552 ($dffe) from module mgmt_core (D = $auto$wreduce.cc:454:run$19205 [1:0], Q = \soc.spimemio.spimemio.rd_addr [1:0]). |
| |
| 12.18.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 18 unused cells and 109 unused wires. |
| <suppressed ~22 debug messages> |
| |
| 12.18.5. Rerunning OPT passes. (Removed registers in this run.) |
| |
| 12.18.6. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~2 debug messages> |
| |
| 12.18.7. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 12.18.8. Executing OPT_DFF pass (perform DFF optimizations). |
| Setting constant 1-bit at position 4 on $flatten\soc.\cpu.\picorv32_core.$procdff$15857 ($dff) from module mgmt_core. |
| Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$15857 ($dff) from module mgmt_core (D = { $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [31:12] $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [8] $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [5] $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [3] $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [1] }, Q = { \soc.cpu.picorv32_core.irq_pending [31:12] \soc.cpu.picorv32_core.irq_pending [8] \soc.cpu.picorv32_core.irq_pending [5] \soc.cpu.picorv32_core.irq_pending [3] \soc.cpu.picorv32_core.irq_pending [1] }, rval = 24'000000000000000000000000). |
| |
| 12.18.9. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 0 unused cells and 1 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 12.18.10. Rerunning OPT passes. (Removed registers in this run.) |
| |
| 12.18.11. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~21 debug messages> |
| |
| 12.18.12. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 12.18.13. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 12.18.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 0 unused cells and 11 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 12.18.15. Finished fast OPT passes. |
| |
| 12.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). |
| Mapping memory cell \soc.cpu.picorv32_core.cpuregs.regs in module \mgmt_core: |
| created 32 $dff cells and 0 static cells of width 32. |
| read interface: 2 $dff and 62 $mux cells. |
| write interface: 32 write mux blocks. |
| |
| 12.20. Executing OPT pass (performing simple optimizations). |
| |
| 12.20.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~11 debug messages> |
| |
| 12.20.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 12.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~282 debug messages> |
| |
| 12.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| New input vector for $reduce_and cell $auto$opt_dff.cc:243:make_patterns_logic$19584: { $auto$opt_dff.cc:217:make_patterns_logic$19581 $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:385$1819_Y $auto$rtlil.cc:2121:Not$17529 } |
| Consolidated identical input bits for $mux cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$3571: |
| Old ports: A={ 3'000 $auto$wreduce.cc:454:run$19142 [4:0] }, B={ 2'00 \housekeeping.pll90_sel \housekeeping.pll_sel }, Y=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$3571_Y |
| New ports: A={ 1'0 $auto$wreduce.cc:454:run$19142 [4:0] }, B={ \housekeeping.pll90_sel \housekeeping.pll_sel }, Y=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$3571_Y [5:0] |
| New connections: $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$3571_Y [7:6] = 2'00 |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10472: { $flatten\soc.\cpu.\picorv32_core.$procmux$10491_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10473_CMP } |
| New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10474: { $flatten\soc.\cpu.\picorv32_core.$procmux$10471_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10489_CMP } |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10524: |
| Old ports: A={ \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] }, B={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y |
| New ports: A=\soc.cpu.picorv32_core.mem_rdata_latched [31], B=\soc.cpu.picorv32_core.mem_rdata_latched [12], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y [0] |
| New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y [11:1] = { $flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$10524_Y [0] } |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10552: |
| Old ports: A=2'00, B=2'10, Y=$auto$wreduce.cc:454:run$19149 [1:0] |
| New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$19149 [1] |
| New connections: $auto$wreduce.cc:454:run$19149 [0] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10730: |
| Old ports: A=5'00000, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10730_Y |
| New ports: A=4'0000, B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10730_Y [3:0] |
| New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10730_Y [4] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10737: |
| Old ports: A=\soc.cpu.picorv32_core.mem_rdata_latched [19:12], B={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10737_Y |
| New ports: A=\soc.cpu.picorv32_core.mem_rdata_latched [19:13], B={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10737_Y [7:1] |
| New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10737_Y [0] = \soc.cpu.picorv32_core.mem_rdata_latched [12] |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10762: |
| Old ports: A=5'00000, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10762_Y |
| New ports: A=4'0000, B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10762_Y [3:0] |
| New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10762_Y [4] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10780: |
| Old ports: A=5'00000, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10780_Y |
| New ports: A=4'0000, B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10780_Y [3:0] |
| New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10780_Y [4] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11397: |
| Old ports: A={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, B={ \soc.cpu.picorv32_core.mem_rdata_latched [6] 4'0000 }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$11397_Y |
| New ports: A={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, B={ \soc.cpu.picorv32_core.mem_rdata_latched [6] 1'0 }, Y={ $flatten\soc.\cpu.\picorv32_core.$procmux$11397_Y [4] $flatten\soc.\cpu.\picorv32_core.$procmux$11397_Y [0] } |
| New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$11397_Y [3:1] = { $flatten\soc.\cpu.\picorv32_core.$procmux$11397_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$11397_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$11397_Y [0] } |
| Consolidated identical input bits for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$11564: |
| Old ports: A=\soc.cpu.picorv32_core.reg_op2, B={ \soc.cpu.picorv32_core.reg_op2 [15:0] \soc.cpu.picorv32_core.reg_op2 [15:0] \soc.cpu.picorv32_core.reg_op2 [7:0] \soc.cpu.picorv32_core.reg_op2 [7:0] \soc.cpu.picorv32_core.reg_op2 [7:0] \soc.cpu.picorv32_core.reg_op2 [7:0] }, Y=\soc.cpu.picorv32_core.mem_la_wdata |
| New ports: A=\soc.cpu.picorv32_core.reg_op2 [31:8], B={ \soc.cpu.picorv32_core.reg_op2 [15:0] \soc.cpu.picorv32_core.reg_op2 [15:0] \soc.cpu.picorv32_core.reg_op2 [7:0] \soc.cpu.picorv32_core.reg_op2 [7:0] }, Y=\soc.cpu.picorv32_core.mem_la_wdata [31:8] |
| New connections: \soc.cpu.picorv32_core.mem_la_wdata [7:0] = \soc.cpu.picorv32_core.reg_op2 [7:0] |
| Consolidated identical input bits for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9449: |
| Old ports: A=\soc.cpu.picorv32_core.mem_rdata_word, B={ \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15:0] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7:0] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9449_Y |
| New ports: A=\soc.cpu.picorv32_core.mem_rdata_word [31:8], B={ \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15:7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9449_Y [31:8] |
| New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9449_Y [7:0] = \soc.cpu.picorv32_core.mem_rdata_word [7:0] |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$8525: |
| Old ports: A=3'100, B=3'010, Y=$auto$wreduce.cc:454:run$19151 [2:0] |
| New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:454:run$19151 [2:1] |
| New connections: $auto$wreduce.cc:454:run$19151 [0] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$8601: |
| Old ports: A=2'00, B=2'10, Y=$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$8601_Y |
| New ports: A=1'0, B=1'1, Y=$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$8601_Y [1] |
| New connections: $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$8601_Y [0] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1541$8603: |
| Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:454:run$19152 [2:0] |
| New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:454:run$19152 [2] $auto$wreduce.cc:454:run$19152 [0] } |
| New connections: $auto$wreduce.cc:454:run$19152 [1] = $auto$wreduce.cc:454:run$19152 [0] |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$8608: |
| Old ports: A=3'100, B=3'010, Y=$auto$wreduce.cc:454:run$19153 [2:0] |
| New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:454:run$19153 [2:1] |
| New connections: $auto$wreduce.cc:454:run$19153 [0] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$8137: |
| Old ports: A={ \soc.cpu.picorv32_core.reg_op1 [31:2] 2'00 }, B={ $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$8136_Y 2'00 }, Y=\soc.cpu.picorv32_core.mem_la_addr |
| New ports: A=\soc.cpu.picorv32_core.reg_op1 [31:2], B=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$8136_Y, Y=\soc.cpu.picorv32_core.mem_la_addr [31:2] |
| New connections: \soc.cpu.picorv32_core.mem_la_addr [1:0] = 2'00 |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$8152: |
| Old ports: A=4'0011, B=4'1100, Y=$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$8152_Y |
| New ports: A=2'01, B=2'10, Y={ $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$8152_Y [2] $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$8152_Y [0] } |
| New connections: { $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$8152_Y [3] $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$8152_Y [1] } = { $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$8152_Y [2] $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$8152_Y [0] } |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:491$8168: |
| Old ports: A=6'000000, B=6'100000, Y=$auto$wreduce.cc:454:run$19154 [5:0] |
| New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$19154 [5] |
| New connections: $auto$wreduce.cc:454:run$19154 [4:0] = 5'00000 |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:617$8212: |
| Old ports: A=2'11, B=2'00, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$11251_Y |
| New ports: A=1'1, B=1'0, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$11251_Y [0] |
| New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$11251_Y [1] = $flatten\soc.\cpu.\picorv32_core.$procmux$11251_Y [0] |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331: |
| Old ports: A={ 32'00000000000000000000000000000000 \soc.cpu.picorv32_core.reg_op2 }, B={ \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 }, Y=$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y |
| New ports: A=1'0, B=\soc.cpu.picorv32_core.reg_op2 [31], Y=$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] |
| New connections: { $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [63:33] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [31:0] } = { $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15331_Y [32] \soc.cpu.picorv32_core.reg_op2 } |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$15340: |
| Old ports: A={ 31'0000000000000000000000000000000 \soc.cpu.picorv32_core.reg_op1 }, B={ \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 }, Y=$auto$wreduce.cc:454:run$19159 [62:0] |
| New ports: A=1'0, B=\soc.cpu.picorv32_core.reg_op1 [31], Y=$auto$wreduce.cc:454:run$19159 [32] |
| New connections: { $auto$wreduce.cc:454:run$19159 [62:33] $auto$wreduce.cc:454:run$19159 [31:0] } = { $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] $auto$wreduce.cc:454:run$19159 [32] \soc.cpu.picorv32_core.reg_op1 } |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2286$1620: |
| Old ports: A=6'011110, B=6'111110, Y=$auto$wreduce.cc:454:run$19162 [5:0] |
| New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$19162 [5] |
| New connections: $auto$wreduce.cc:454:run$19162 [4:0] = 5'11110 |
| Consolidated identical input bits for $mux cell $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12377: |
| Old ports: A={ 1'0 \soc.gpio_wb.gpio_ctrl.gpio_pd }, B={ 1'0 \soc.gpio_wb.gpio_ctrl.gpio_pu }, Y=$auto$wreduce.cc:454:run$19164 [1:0] |
| New ports: A=\soc.gpio_wb.gpio_ctrl.gpio_pd, B=\soc.gpio_wb.gpio_ctrl.gpio_pu, Y=$auto$wreduce.cc:454:run$19164 [0] |
| New connections: $auto$wreduce.cc:454:run$19164 [1] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12900: |
| Old ports: A=2'01, B=2'11, Y=$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12900_Y |
| New ports: A=1'0, B=1'1, Y=$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12900_Y [1] |
| New connections: $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12900_Y [0] = 1'1 |
| Consolidated identical input bits for $mux cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:205$1965: |
| Old ports: A=32'11111111111111111111111111111111, B={ 24'000000000000000000000000 \soc.simple_spi_master_inst.spi_master.rreg }, Y=\soc.simple_spi_master_inst.simple_spi_master_reg_dat_do |
| New ports: A=9'111111111, B={ 1'0 \soc.simple_spi_master_inst.spi_master.rreg }, Y=\soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8:0] |
| New connections: \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [31:9] = { \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] } |
| Consolidated identical input bits for $mux cell $flatten\soc.\simpleuart.\simpleuart.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:132$1908: |
| Old ports: A=32'11111111111111111111111111111111, B={ 24'000000000000000000000000 \soc.simpleuart.simpleuart.recv_buf_data }, Y=\soc.simpleuart.simpleuart_reg_dat_do |
| New ports: A=9'111111111, B={ 1'0 \soc.simpleuart.simpleuart.recv_buf_data }, Y=\soc.simpleuart.simpleuart_reg_dat_do [8:0] |
| New connections: \soc.simpleuart.simpleuart_reg_dat_do [31:9] = { \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] } |
| Consolidated identical input bits for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$15029: |
| Old ports: A=4'0000, B=16'0001001000110100, Y=$flatten\soc.\spimemio.\spimemio.$procmux$15029_Y |
| New ports: A=3'000, B=12'001010011100, Y=$flatten\soc.\spimemio.\spimemio.$procmux$15029_Y [2:0] |
| New connections: $flatten\soc.\spimemio.\spimemio.$procmux$15029_Y [3] = 1'0 |
| Consolidated identical input bits for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$15060: |
| Old ports: A=8'11101101, B=24'111010111011101100000011, Y=$flatten\soc.\spimemio.\spimemio.$procmux$15060_Y |
| New ports: A=5'10110, B=15'101010110100001, Y={ $flatten\soc.\spimemio.\spimemio.$procmux$15060_Y [6] $flatten\soc.\spimemio.\spimemio.$procmux$15060_Y [4:1] } |
| New connections: { $flatten\soc.\spimemio.\spimemio.$procmux$15060_Y [7] $flatten\soc.\spimemio.\spimemio.$procmux$15060_Y [5] $flatten\soc.\spimemio.\spimemio.$procmux$15060_Y [0] } = { $flatten\soc.\spimemio.\spimemio.$procmux$15060_Y [3] $flatten\soc.\spimemio.\spimemio.$procmux$15060_Y [3] 1'1 } |
| Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:477$1827: |
| Old ports: A=7'1111111, B=7'0100101, Y=$auto$wreduce.cc:454:run$19206 [6:0] |
| New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$19206 [1] |
| New connections: { $auto$wreduce.cc:454:run$19206 [6:2] $auto$wreduce.cc:454:run$19206 [0] } = { $auto$wreduce.cc:454:run$19206 [1] 1'1 $auto$wreduce.cc:454:run$19206 [1] $auto$wreduce.cc:454:run$19206 [1] 2'11 } |
| Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14607: |
| Old ports: A=\soc.spimemio.spimemio.xfer.count, B={ $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:685$1861_Y [3:1] \soc.spimemio.spimemio.xfer.count [0] }, Y=$flatten\soc.\spimemio.\spimemio.\xfer.$5\next_count[3:0] |
| New ports: A=\soc.spimemio.spimemio.xfer.count [3:1], B=$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:685$1861_Y [3:1], Y=$flatten\soc.\spimemio.\spimemio.\xfer.$5\next_count[3:0] [3:1] |
| New connections: $flatten\soc.\spimemio.\spimemio.\xfer.$5\next_count[3:0] [0] = \soc.spimemio.spimemio.xfer.count [0] |
| Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14648: |
| Old ports: A=\soc.spimemio.spimemio.xfer.count, B={ $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:652$1849_Y [3:2] \soc.spimemio.spimemio.xfer.count [1:0] }, Y=$flatten\soc.\spimemio.\spimemio.\xfer.$4\next_count[3:0] |
| New ports: A=\soc.spimemio.spimemio.xfer.count [3:2], B=$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:652$1849_Y [3:2], Y=$flatten\soc.\spimemio.\spimemio.\xfer.$4\next_count[3:0] [3:2] |
| New connections: $flatten\soc.\spimemio.\spimemio.\xfer.$4\next_count[3:0] [1:0] = \soc.spimemio.spimemio.xfer.count [1:0] |
| Consolidated identical input bits for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14746: |
| Old ports: A={ \soc.spimemio.spimemio.xfer.obuffer [5:0] 2'00 }, B={ \soc.spimemio.spimemio.xfer.obuffer [6:0] 1'0 \soc.spimemio.spimemio.xfer.obuffer [3:0] 4'0000 }, Y=\soc.spimemio.spimemio.xfer.next_obuffer |
| New ports: A={ \soc.spimemio.spimemio.xfer.obuffer [5:0] 1'0 }, B={ \soc.spimemio.spimemio.xfer.obuffer [6:0] \soc.spimemio.spimemio.xfer.obuffer [3:0] 3'000 }, Y=\soc.spimemio.spimemio.xfer.next_obuffer [7:1] |
| New connections: \soc.spimemio.spimemio.xfer.next_obuffer [0] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\soc.\sysctrl.\sysctrl.$procmux$12356: |
| Old ports: A={ 2'00 \soc.sysctrl.sysctrl.irq_8_inputsrc \soc.sysctrl.sysctrl.irq_7_inputsrc }, B={ 3'000 \soc.sysctrl.sysctrl.trap_output_dest }, Y=$auto$wreduce.cc:454:run$19210 [3:0] |
| New ports: A={ \soc.sysctrl.sysctrl.irq_8_inputsrc \soc.sysctrl.sysctrl.irq_7_inputsrc }, B={ 1'0 \soc.sysctrl.sysctrl.trap_output_dest }, Y=$auto$wreduce.cc:454:run$19210 [1:0] |
| New connections: $auto$wreduce.cc:454:run$19210 [3:2] = 2'00 |
| Optimizing cells in module \mgmt_core. |
| Consolidated identical input bits for $mux cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:190$3572: |
| Old ports: A=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$3571_Y, B={ 6'000000 \housekeeping.pll_trim [25:24] }, Y=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:190$3572_Y |
| New ports: A=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$3571_Y [5:0], B={ 4'0000 \housekeeping.pll_trim [25:24] }, Y=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:190$3572_Y [5:0] |
| New connections: $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:190$3572_Y [7:6] = 2'00 |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10764: |
| Old ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$10762_Y, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10764_Y |
| New ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$10762_Y [3:0], B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10764_Y [3:0] |
| New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10764_Y [4] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$12380: |
| Old ports: A=$auto$wreduce.cc:454:run$19164 [1:0], B={ 1'0 \soc.gpio_wb.gpio_ctrl.gpio_oeb }, Y=$auto$wreduce.cc:454:run$19165 [1:0] |
| New ports: A=$auto$wreduce.cc:454:run$19164 [0], B=\soc.gpio_wb.gpio_ctrl.gpio_oeb, Y=$auto$wreduce.cc:454:run$19165 [0] |
| New connections: $auto$wreduce.cc:454:run$19165 [1] = 1'0 |
| Consolidated identical input bits for $mux cell $flatten\soc.\simple_spi_master_inst.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:108$5915: |
| Old ports: A=\soc.simple_spi_master_inst.simple_spi_master_reg_dat_do, B={ 16'0000000000000000 \soc.simple_spi_master_inst.spi_master.hkconn \soc.simple_spi_master_inst.spi_master.irqena \soc.simple_spi_master_inst.spi_master.enable \soc.simple_spi_master_inst.spi_master.stream \soc.simple_spi_master_inst.spi_master.mode \soc.simple_spi_master_inst.spi_master.invsck \soc.simple_spi_master_inst.spi_master.invcsb \soc.simple_spi_master_inst.spi_master.mlb \soc.simple_spi_master_inst.spi_master.prescaler }, Y=\soc.simple_spi_master_inst.wb_dat_o |
| New ports: A={ \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8:0] }, B={ 1'0 \soc.simple_spi_master_inst.spi_master.hkconn \soc.simple_spi_master_inst.spi_master.irqena \soc.simple_spi_master_inst.spi_master.enable \soc.simple_spi_master_inst.spi_master.stream \soc.simple_spi_master_inst.spi_master.mode \soc.simple_spi_master_inst.spi_master.invsck \soc.simple_spi_master_inst.spi_master.invcsb \soc.simple_spi_master_inst.spi_master.mlb \soc.simple_spi_master_inst.spi_master.prescaler }, Y=\soc.simple_spi_master_inst.wb_dat_o [16:0] |
| New connections: \soc.simple_spi_master_inst.wb_dat_o [31:17] = { \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] } |
| Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.$procmux$15050: |
| Old ports: A={ 1'1 $auto$wreduce.cc:454:run$19206 [6:0] }, B={ 4'0000 \soc.spimemio.spimemio.config_dummy }, Y=$flatten\soc.\spimemio.\spimemio.$procmux$15050_Y |
| New ports: A={ 1'1 $auto$wreduce.cc:454:run$19206 [1] $auto$wreduce.cc:454:run$19206 [1] 1'1 $auto$wreduce.cc:454:run$19206 [1] 1'1 }, B={ 2'00 \soc.spimemio.spimemio.config_dummy }, Y=$flatten\soc.\spimemio.\spimemio.$procmux$15050_Y [5:0] |
| New connections: $flatten\soc.\spimemio.\spimemio.$procmux$15050_Y [7:6] = $flatten\soc.\spimemio.\spimemio.$procmux$15050_Y [5:4] |
| Consolidated identical input bits for $mux cell $flatten\soc.\sysctrl.\sysctrl.$procmux$12359: |
| Old ports: A=$auto$wreduce.cc:454:run$19210 [3:0], B={ 2'00 \soc.sysctrl.sysctrl.clk2_output_dest \soc.sysctrl.sysctrl.clk1_output_dest }, Y=$auto$wreduce.cc:454:run$19211 [3:0] |
| New ports: A=$auto$wreduce.cc:454:run$19210 [1:0], B={ \soc.sysctrl.sysctrl.clk2_output_dest \soc.sysctrl.sysctrl.clk1_output_dest }, Y=$auto$wreduce.cc:454:run$19211 [1:0] |
| New connections: $auto$wreduce.cc:454:run$19211 [3:2] = 2'00 |
| Optimizing cells in module \mgmt_core. |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10766: |
| Old ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$10764_Y, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10766_Y |
| New ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$10764_Y [3:0], B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10766_Y [3:0] |
| New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10766_Y [4] = 1'0 |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 42 changes. |
| |
| 12.20.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| <suppressed ~54 debug messages> |
| Removed a total of 18 cells. |
| |
| 12.20.6. Executing OPT_SHARE pass. |
| Found cells that share an operand and can be merged by moving the $mux $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13886 in front of them: |
| $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13884 |
| $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13859 |
| |
| Found cells that share an operand and can be merged by moving the $mux $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13913 in front of them: |
| $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13911 |
| $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$13901 |
| |
| Found cells that share an operand and can be merged by moving the $mux $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$14199 in front of them: |
| $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$14197 |
| $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$14173 |
| |
| Found cells that share an operand and can be merged by moving the $mux $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$8734 in front of them: |
| $auto$alumacc.cc:485:replace_alu$19411 |
| $auto$alumacc.cc:485:replace_alu$19378 |
| |
| Found cells that share an operand and can be merged by moving the $pmux $flatten\soc.\spimemio.\spimemio.$procmux$14936 in front of them: |
| $flatten\soc.\spimemio.\spimemio.$procmux$14934 |
| $flatten\soc.\spimemio.\spimemio.$procmux$14958 |
| |
| 12.20.7. Executing OPT_DFF pass (perform DFF optimizations). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$18340 ($dffe) from module mgmt_core (D = $auto$wreduce.cc:454:run$19161 [4:0], Q = \soc.cpu.picorv32_core.pcpi_mul.mul_counter [4:0], rval = 5'11110). |
| Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$18567 ($sdff) from module mgmt_core. |
| |
| 12.20.8. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 2 unused cells and 135 unused wires. |
| <suppressed ~3 debug messages> |
| |
| 12.20.9. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~19 debug messages> |
| |
| 12.20.10. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 12.20.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~281 debug messages> |
| |
| 12.20.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10268: |
| Old ports: A=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$8609_Y, B={ $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$8613_Y [31:1] $auto$alumacc.cc:501:replace_alu$19394 [0] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10268_Y |
| New ports: A=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$8609_Y [31:1], B=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$8613_Y [31:1], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10268_Y [31:1] |
| New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10268_Y [0] = $auto$alumacc.cc:501:replace_alu$19394 [0] |
| New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$14936: { $auto$opt_reduce.cc:134:opt_mux$16386 $auto$opt_reduce.cc:134:opt_mux$20115 } |
| Optimizing cells in module \mgmt_core. |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10270: |
| Old ports: A={ $flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$19394 [0] }, B=$flatten\soc.\cpu.\picorv32_core.$procmux$10268_Y, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10270_Y |
| New ports: A=$flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], B=$flatten\soc.\cpu.\picorv32_core.$procmux$10268_Y [31:1], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10270_Y [31:1] |
| New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10270_Y [0] = $auto$alumacc.cc:501:replace_alu$19394 [0] |
| Optimizing cells in module \mgmt_core. |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10276: |
| Old ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$10270_Y, B={ $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$8609_Y [31:1] $auto$alumacc.cc:501:replace_alu$19394 [0] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10276_Y |
| New ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$10270_Y [31:1], B=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$8609_Y [31:1], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10276_Y [31:1] |
| New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10276_Y [0] = $auto$alumacc.cc:501:replace_alu$19394 [0] |
| Optimizing cells in module \mgmt_core. |
| Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10279: |
| Old ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$10276_Y, B={ $flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$19394 [0] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10279_Y |
| New ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$10276_Y [31:1], B=$flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10279_Y [31:1] |
| New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10279_Y [0] = $auto$alumacc.cc:501:replace_alu$19394 [0] |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 5 changes. |
| |
| 12.20.13. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 12.20.14. Executing OPT_SHARE pass. |
| Found cells that share an operand and can be merged by moving the $mux $auto$opt_share.cc:241:merge_operators$20098 in front of them: |
| $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:212$2126 |
| $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:260$2139 |
| |
| 12.20.15. Executing OPT_DFF pass (perform DFF optimizations). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[9]$19614 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[9]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[8]$19612 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[8]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[7]$19610 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[7]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[6]$19608 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[6]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[5]$19606 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[5]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[4]$19604 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[4]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[3]$19602 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[3]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[31]$19658 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[31]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[30]$19656 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[30]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[2]$19600 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[2]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[29]$19654 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[29]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[28]$19652 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[28]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[27]$19650 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[27]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[26]$19648 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[26]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[25]$19646 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[25]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[24]$19644 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[24]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[23]$19642 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[23]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[22]$19640 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[22]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[21]$19638 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[21]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[20]$19636 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[20]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[1]$19598 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[1]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[19]$19634 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[19]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[18]$19632 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[18]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[17]$19630 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[17]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[16]$19628 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[16]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[15]$19626 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[15]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[14]$19624 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[14]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[13]$19622 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[13]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[12]$19620 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[12]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[11]$19618 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[11]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[10]$19616 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[10]). |
| Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[0]$19596 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[0]). |
| Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$18458 ($dffe) from module mgmt_core. |
| Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$18458 ($dffe) from module mgmt_core. |
| Adding SRST signal on $auto$opt_dff.cc:764:run$18300 ($dffe) from module mgmt_core (D = \soc.gpio_wb.gpio_ctrl.gpio, Q = \soc.gpio_wb.gpio_ctrl.iomem_rdata [1], rval = 1'0). |
| Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$17585 ($sdffe) from module mgmt_core. |
| Adding SRST signal on $auto$opt_dff.cc:764:run$17494 ($dffe) from module mgmt_core (D = \soc.spimemio.spimemio.din_data [0], Q = \soc.spimemio.spimemio.xfer.obuffer [0], rval = 1'0). |
| Adding SRST signal on $auto$opt_dff.cc:764:run$17419 ($dffe) from module mgmt_core (D = { \mprj2_vdd_pwrgood \mprj_vdd_pwrgood }, Q = \soc.sysctrl.sysctrl.iomem_rdata [3:2], rval = 2'00). |
| |
| 12.20.16. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 32 unused cells and 46 unused wires. |
| <suppressed ~33 debug messages> |
| |
| 12.20.17. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~1 debug messages> |
| |
| 12.20.18. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 12.20.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~249 debug messages> |
| |
| 12.20.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| Consolidated identical input bits for $mux cell $auto$opt_share.cc:241:merge_operators$20117: |
| Old ports: A=2, B=32'11111111111111111111111111111111, Y=$auto$rtlil.cc:2218:Mux$20118 |
| New ports: A=1'0, B=1'1, Y=$auto$rtlil.cc:2218:Mux$20118 [0] |
| New connections: $auto$rtlil.cc:2218:Mux$20118 [31:1] = { $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] $auto$rtlil.cc:2218:Mux$20118 [0] 1'1 } |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 1 changes. |
| |
| 12.20.21. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 12.20.22. Executing OPT_SHARE pass. |
| |
| 12.20.23. Executing OPT_DFF pass (perform DFF optimizations). |
| Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$18778 ($sdffe) from module mgmt_core. |
| Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$18778 ($sdffe) from module mgmt_core. |
| Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$17430 ($sdffe) from module mgmt_core. |
| |
| 12.20.24. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 0 unused cells and 1 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 12.20.25. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~2 debug messages> |
| |
| 12.20.26. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 12.20.27. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~248 debug messages> |
| |
| 12.20.28. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.$procmux$15053: |
| Old ports: A={ \soc.cpu.wbm_adr_o [7:2] 2'00 }, B=8'00000000, Y=$flatten\soc.\spimemio.\spimemio.$procmux$15053_Y |
| New ports: A=\soc.cpu.wbm_adr_o [7:2], B=6'000000, Y=$flatten\soc.\spimemio.\spimemio.$procmux$15053_Y [7:2] |
| New connections: $flatten\soc.\spimemio.\spimemio.$procmux$15053_Y [1:0] = 2'00 |
| Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:387$1822: |
| Old ports: A={ \soc.cpu.wbm_adr_o [23:2] 2'00 }, B={ $auto$wreduce.cc:454:run$19204 [23:2] 2'xx }, Y=$auto$wreduce.cc:454:run$19205 [23:0] |
| New ports: A={ \soc.cpu.wbm_adr_o [23:2] 1'0 }, B={ $auto$wreduce.cc:454:run$19204 [23:2] 1'x }, Y={ $auto$wreduce.cc:454:run$19205 [23:2] $auto$wreduce.cc:454:run$19205 [0] } |
| New connections: $auto$wreduce.cc:454:run$19205 [1] = $auto$wreduce.cc:454:run$19205 [0] |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 2 changes. |
| |
| 12.20.29. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 12.20.30. Executing OPT_SHARE pass. |
| |
| 12.20.31. Executing OPT_DFF pass (perform DFF optimizations). |
| Setting constant 0-bit at position 3 on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$16149 ($dff) from module mgmt_core. |
| |
| 12.20.32. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 0 unused cells and 1 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 12.20.33. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| |
| 12.20.34. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 12.20.35. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~248 debug messages> |
| |
| 12.20.36. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 0 changes. |
| |
| 12.20.37. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 12.20.38. Executing OPT_SHARE pass. |
| |
| 12.20.39. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 12.20.40. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| |
| 12.20.41. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| |
| 12.20.42. Finished OPT passes. (There is nothing left to do.) |
| |
| 12.21. Executing TECHMAP pass (map to technology primitives). |
| |
| 12.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v |
| Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation. |
| Generating RTLIL representation for module `\_90_simplemap_bool_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_logic_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_compare_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_various'. |
| Generating RTLIL representation for module `\_90_simplemap_registers'. |
| Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. |
| Generating RTLIL representation for module `\_90_shift_shiftx'. |
| Generating RTLIL representation for module `\_90_fa'. |
| Generating RTLIL representation for module `\_90_lcu'. |
| Generating RTLIL representation for module `\_90_alu'. |
| Generating RTLIL representation for module `\_90_macc'. |
| Generating RTLIL representation for module `\_90_alumacc'. |
| Generating RTLIL representation for module `\$__div_mod_u'. |
| Generating RTLIL representation for module `\$__div_mod_trunc'. |
| Generating RTLIL representation for module `\_90_div'. |
| Generating RTLIL representation for module `\_90_mod'. |
| Generating RTLIL representation for module `\$__div_mod_floor'. |
| Generating RTLIL representation for module `\_90_divfloor'. |
| Generating RTLIL representation for module `\_90_modfloor'. |
| Generating RTLIL representation for module `\_90_pow'. |
| Generating RTLIL representation for module `\_90_pmux'. |
| Generating RTLIL representation for module `\_90_lut'. |
| Successfully finished Verilog frontend. |
| |
| 12.21.2. Continuing TECHMAP pass. |
| Using extmapper simplemap for cells of type $mux. |
| Using extmapper simplemap for cells of type $and. |
| Using extmapper simplemap for cells of type $not. |
| Using extmapper simplemap for cells of type $or. |
| Using extmapper simplemap for cells of type $reduce_and. |
| Using extmapper simplemap for cells of type $eq. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. |
| Using extmapper simplemap for cells of type $logic_not. |
| Using extmapper simplemap for cells of type $xor. |
| Using extmapper simplemap for cells of type $adff. |
| Using extmapper simplemap for cells of type $adffe. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=3\Y_WIDTH=4 for cells of type $alu. |
| Using extmapper simplemap for cells of type $dff. |
| Using extmapper simplemap for cells of type $ne. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu. |
| Using extmapper simplemap for cells of type $logic_and. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=0\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu. |
| Using extmapper simplemap for cells of type $reduce_or. |
| Using extmapper simplemap for cells of type $reduce_bool. |
| Using extmapper simplemap for cells of type $sdffe. |
| Using extmapper simplemap for cells of type $dffe. |
| Using extmapper simplemap for cells of type $sdff. |
| Using extmapper simplemap for cells of type $sdffce. |
| Using extmapper maccmap for cells of type $macc. |
| add \soc.cpu.picorv32_core.pcpi_mul.rd [15:12] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [15:12] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.rdx [12] (1 bits, unsigned) |
| packed 1 (1) bits / 1 words into adder tree |
| Running "alumacc" on wrapper $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47. |
| Using template $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47. |
| Using template $paramod\_90_pmux\WIDTH=13\S_WIDTH=37 for cells of type $pmux. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=5 for cells of type $alu. |
| Using extmapper simplemap for cells of type $logic_or. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=1\Y_WIDTH=32 for cells of type $alu. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. |
| Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=3 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=3 for cells of type $pmux. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=31\B_WIDTH=31\Y_WIDTH=31 for cells of type $alu. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=63\Y_WIDTH=63 for cells of type $alu. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=22\Y_WIDTH=23 for cells of type $alu. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu. |
| Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=3 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=2 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=7\S_WIDTH=2 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=5\S_WIDTH=3 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=7 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=4 for cells of type $pmux. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=0\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu. |
| add \soc.cpu.picorv32_core.pcpi_mul.rd [19:16] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [19:16] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.rdx [16] (1 bits, unsigned) |
| packed 1 (1) bits / 1 words into adder tree |
| add \soc.cpu.picorv32_core.pcpi_mul.rd [27:24] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [27:24] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.rdx [24] (1 bits, unsigned) |
| packed 1 (1) bits / 1 words into adder tree |
| add \soc.cpu.picorv32_core.pcpi_mul.rd [23:20] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [23:20] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.rdx [20] (1 bits, unsigned) |
| packed 1 (1) bits / 1 words into adder tree |
| add \soc.cpu.picorv32_core.pcpi_mul.rd [31:28] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [31:28] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.rdx [28] (1 bits, unsigned) |
| packed 1 (1) bits / 1 words into adder tree |
| add \soc.cpu.picorv32_core.pcpi_mul.rd [11:8] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [11:8] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.rdx [8] (1 bits, unsigned) |
| packed 1 (1) bits / 1 words into adder tree |
| add \soc.cpu.picorv32_core.pcpi_mul.rd [7:4] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [7:4] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.rdx [4] (1 bits, unsigned) |
| packed 1 (1) bits / 1 words into adder tree |
| add \soc.cpu.picorv32_core.pcpi_mul.rd [3:0] (4 bits, unsigned) |
| add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [3:0] (4 bits, unsigned) |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=1\Y_WIDTH=6 for cells of type $alu. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=1\Y_WIDTH=7 for cells of type $alu. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. |
| Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux. |
| Using template $paramod$constmap:66d421c313e4e958be776b99540ac2de3b59fdbc$paramod$9b74a473ccd678a23e1df4cc12019cbbece20051\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. |
| Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=2 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=6\S_WIDTH=2 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=6\S_WIDTH=4 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=6\S_WIDTH=3 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=2 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=3 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=5\S_WIDTH=2 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux. |
| Using extmapper simplemap for cells of type $dffsre. |
| Using template $paramod\_90_pmux\WIDTH=5\S_WIDTH=4 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=5 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=4 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=5 for cells of type $pmux. |
| Using template $paramod$constmap:87f69c0bea22f84de4bcd0314b57cb19e61b5eb7$paramod$88abf4b792300efa328894e6936be740fdc22f6d\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr. |
| Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$887c9fe2c55be14c90171bd2ff359c086a0858d7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. |
| Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=6 for cells of type $pmux. |
| Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=4 for cells of type $pmux. |
| Using template $paramod\_90_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=64\Y_WIDTH=64 for cells of type $alu. |
| Using extmapper simplemap for cells of type $pos. |
| Using template $paramod\_90_lcu\WIDTH=5 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=4 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=7 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=6 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=3 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=8 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=32 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=64 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=31 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=30 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=23 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=63 for cells of type $lcu. |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. |
| No more expansions possible. |
| <suppressed ~13750 debug messages> |
| |
| 12.22. Executing OPT pass (performing simple optimizations). |
| |
| 12.22.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~9701 debug messages> |
| |
| 12.22.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| <suppressed ~11859 debug messages> |
| Removed a total of 3953 cells. |
| |
| 12.22.3. Executing OPT_DFF pass (perform DFF optimizations). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$41072 ($_DFFE_PP_) from module mgmt_core (D = 1'x, Q = \soc.spimemio.spimemio.rd_addr [0], rval = 1'0). |
| Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$68086 ($_SDFFCE_PN0P_) from module mgmt_core. |
| |
| 12.22.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 1049 unused cells and 9593 unused wires. |
| <suppressed ~1050 debug messages> |
| |
| 12.22.5. Rerunning OPT passes. (Removed registers in this run.) |
| |
| 12.22.6. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~4 debug messages> |
| |
| 12.22.7. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 12.22.8. Executing OPT_DFF pass (perform DFF optimizations). |
| Adding EN signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$39870 ($_SDFFE_PP0P_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9189.B_AND_S [32], Q = \soc.cpu.picorv32_core.reg_pc [0]). |
| Adding EN signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$21296 ($_SDFFE_PP0P_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$14726.Y_B [0], Q = \soc.spimemio.spimemio.xfer.count [0]). |
| Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$37355 ($_SDFF_PP0_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$14936.Y_B, Q = \soc.spimemio.spimemio.din_valid, rval = 1'0). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36512 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [30], Q = \soc.cpu.picorv32_core.irq_pending [31]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36511 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [29], Q = \soc.cpu.picorv32_core.irq_pending [30]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36510 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [28], Q = \soc.cpu.picorv32_core.irq_pending [29]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36509 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [27], Q = \soc.cpu.picorv32_core.irq_pending [28]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36508 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [26], Q = \soc.cpu.picorv32_core.irq_pending [27]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36507 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [25], Q = \soc.cpu.picorv32_core.irq_pending [26]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36506 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [24], Q = \soc.cpu.picorv32_core.irq_pending [25]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36505 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [23], Q = \soc.cpu.picorv32_core.irq_pending [24]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36504 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [22], Q = \soc.cpu.picorv32_core.irq_pending [23]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36503 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [21], Q = \soc.cpu.picorv32_core.irq_pending [22]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36502 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [20], Q = \soc.cpu.picorv32_core.irq_pending [21]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36501 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [19], Q = \soc.cpu.picorv32_core.irq_pending [20]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36500 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [18], Q = \soc.cpu.picorv32_core.irq_pending [19]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36499 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [17], Q = \soc.cpu.picorv32_core.irq_pending [18]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36498 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [16], Q = \soc.cpu.picorv32_core.irq_pending [17]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36497 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [15], Q = \soc.cpu.picorv32_core.irq_pending [16]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36496 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [14], Q = \soc.cpu.picorv32_core.irq_pending [15]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36495 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [13], Q = \soc.cpu.picorv32_core.irq_pending [14]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36494 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [12], Q = \soc.cpu.picorv32_core.irq_pending [13]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36493 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [11], Q = \soc.cpu.picorv32_core.irq_pending [12]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36492 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [7], Q = \soc.cpu.picorv32_core.irq_pending [8]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36491 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [4], Q = \soc.cpu.picorv32_core.irq_pending [5]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36490 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$19593 [3], Q = \soc.cpu.picorv32_core.irq_pending [3]). |
| Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$36489 ($_SDFF_PP0_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8820.Y, Q = \soc.cpu.picorv32_core.irq_pending [1]). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39565 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [31], Q = \soc.cpu.picorv32_core.decoded_imm [31], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39564 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [30], Q = \soc.cpu.picorv32_core.decoded_imm [30], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39563 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [29], Q = \soc.cpu.picorv32_core.decoded_imm [29], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39562 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [28], Q = \soc.cpu.picorv32_core.decoded_imm [28], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39561 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [27], Q = \soc.cpu.picorv32_core.decoded_imm [27], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39560 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [26], Q = \soc.cpu.picorv32_core.decoded_imm [26], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39559 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [25], Q = \soc.cpu.picorv32_core.decoded_imm [25], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39558 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [24], Q = \soc.cpu.picorv32_core.decoded_imm [24], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39557 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [23], Q = \soc.cpu.picorv32_core.decoded_imm [23], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39556 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [22], Q = \soc.cpu.picorv32_core.decoded_imm [22], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39555 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [21], Q = \soc.cpu.picorv32_core.decoded_imm [21], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39554 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [20], Q = \soc.cpu.picorv32_core.decoded_imm [20], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39553 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [19], Q = \soc.cpu.picorv32_core.decoded_imm [19], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39552 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [18], Q = \soc.cpu.picorv32_core.decoded_imm [18], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39551 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [17], Q = \soc.cpu.picorv32_core.decoded_imm [17], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39550 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [16], Q = \soc.cpu.picorv32_core.decoded_imm [16], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39549 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [15], Q = \soc.cpu.picorv32_core.decoded_imm [15], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39548 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [14], Q = \soc.cpu.picorv32_core.decoded_imm [14], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39547 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [13], Q = \soc.cpu.picorv32_core.decoded_imm [13], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39546 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [12], Q = \soc.cpu.picorv32_core.decoded_imm [12], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39545 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [11], Q = \soc.cpu.picorv32_core.decoded_imm [11], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39544 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [10], Q = \soc.cpu.picorv32_core.decoded_imm [10], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39543 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [9], Q = \soc.cpu.picorv32_core.decoded_imm [9], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39542 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [8], Q = \soc.cpu.picorv32_core.decoded_imm [8], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39541 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [7], Q = \soc.cpu.picorv32_core.decoded_imm [7], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39540 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [6], Q = \soc.cpu.picorv32_core.decoded_imm [6], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39539 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [5], Q = \soc.cpu.picorv32_core.decoded_imm [5], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39538 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [4], Q = \soc.cpu.picorv32_core.decoded_imm [4], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39537 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [3], Q = \soc.cpu.picorv32_core.decoded_imm [3], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39536 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [2], Q = \soc.cpu.picorv32_core.decoded_imm [2], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39535 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10700.Y_B [1], Q = \soc.cpu.picorv32_core.decoded_imm [1], rval = 1'0). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$21056 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15048.Y_B [7], Q = \soc.spimemio.spimemio.din_data [7], rval = 1'1). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$21055 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15048.Y_B [6], Q = \soc.spimemio.spimemio.din_data [6], rval = 1'1). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$21054 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15048.Y_B [5], Q = \soc.spimemio.spimemio.din_data [5], rval = 1'1). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$21053 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15048.Y_B [4], Q = \soc.spimemio.spimemio.din_data [4], rval = 1'1). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$21052 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15048.Y_B [3], Q = \soc.spimemio.spimemio.din_data [3], rval = 1'1). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$21051 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15048.Y_B [2], Q = \soc.spimemio.spimemio.din_data [2], rval = 1'1). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$21050 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15048.Y_B [1], Q = \soc.spimemio.spimemio.din_data [1], rval = 1'1). |
| Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$21049 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$15048.Y_B [0], Q = \soc.spimemio.spimemio.din_data [0], rval = 1'1). |
| |
| 12.22.9. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 88 unused cells and 30 unused wires. |
| <suppressed ~89 debug messages> |
| |
| 12.22.10. Rerunning OPT passes. (Removed registers in this run.) |
| |
| 12.22.11. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~2 debug messages> |
| |
| 12.22.12. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| <suppressed ~132 debug messages> |
| Removed a total of 44 cells. |
| |
| 12.22.13. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 12.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 0 unused cells and 45 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 12.22.15. Finished fast OPT passes. |
| |
| 12.23. Executing ABC pass (technology mapping using ABC). |
| |
| 12.23.1. Extracting gate netlist of module `\mgmt_core' to `<abc-temp-dir>/input.blif'.. |
| Extracted 20482 gates and 24728 wires to a netlist network with 4243 inputs and 1941 outputs. |
| |
| 12.23.1.1. Executing ABC. |
| Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". |
| ABC: |
| ABC: + read_blif <abc-temp-dir>/input.blif |
| ABC: + read_library <abc-temp-dir>/stdcells.genlib |
| ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib". |
| ABC: + strash |
| ABC: + dretime |
| ABC: + map |
| ABC: + write_blif <abc-temp-dir>/output.blif |
| |
| 12.23.1.2. Re-integrating ABC results. |
| ABC RESULTS: AND cells: 962 |
| ABC RESULTS: ANDNOT cells: 4589 |
| ABC RESULTS: MUX cells: 5749 |
| ABC RESULTS: NAND cells: 764 |
| ABC RESULTS: NOR cells: 774 |
| ABC RESULTS: NOT cells: 1139 |
| ABC RESULTS: OR cells: 4025 |
| ABC RESULTS: ORNOT cells: 610 |
| ABC RESULTS: XNOR cells: 247 |
| ABC RESULTS: XOR cells: 1196 |
| ABC RESULTS: internal signals: 18544 |
| ABC RESULTS: input signals: 4243 |
| ABC RESULTS: output signals: 1941 |
| Removing temp directory. |
| |
| 12.24. Executing OPT pass (performing simple optimizations). |
| |
| 12.24.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| <suppressed ~3888 debug messages> |
| |
| 12.24.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| <suppressed ~225 debug messages> |
| Removed a total of 75 cells. |
| |
| 12.24.3. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 12.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 26 unused cells and 12023 unused wires. |
| <suppressed ~221 debug messages> |
| |
| 12.24.5. Finished fast OPT passes. |
| |
| 12.25. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 12.25.1. Analyzing design hierarchy.. |
| Top module: \mgmt_core |
| |
| 12.25.2. Analyzing design hierarchy.. |
| Top module: \mgmt_core |
| Removed 0 unused modules. |
| |
| 12.26. Printing statistics. |
| |
| === mgmt_core === |
| |
| Number of wires: 20400 |
| Number of wire bits: 34246 |
| Number of public wires: 1161 |
| Number of public wire bits: 14394 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 23822 |
| $_ANDNOT_ 4581 |
| $_AND_ 962 |
| $_DFFE_NN0P_ 12 |
| $_DFFE_NN1P_ 32 |
| $_DFFE_NP0N_ 3 |
| $_DFFE_NP0P_ 26 |
| $_DFFE_PN0N_ 7 |
| $_DFFE_PN0P_ 182 |
| $_DFFE_PN1N_ 5 |
| $_DFFE_PN1P_ 23 |
| $_DFFE_PN_ 7 |
| $_DFFE_PP0P_ 9 |
| $_DFFE_PP_ 1654 |
| $_DFFSRE_NPPP_ 12 |
| $_DFFSRE_PPPP_ 6 |
| $_DFF_NP0_ 4 |
| $_DFF_NP1_ 1 |
| $_DFF_N_ 2 |
| $_DFF_PN0_ 25 |
| $_DFF_PN1_ 8 |
| $_DFF_PP1_ 1 |
| $_DFF_P_ 152 |
| $_MUX_ 5743 |
| $_NAND_ 761 |
| $_NOR_ 724 |
| $_NOT_ 1113 |
| $_ORNOT_ 608 |
| $_OR_ 4021 |
| $_SDFFCE_PN0P_ 42 |
| $_SDFFCE_PN1P_ 8 |
| $_SDFFCE_PP0P_ 177 |
| $_SDFFCE_PP1P_ 5 |
| $_SDFFE_PN0N_ 1 |
| $_SDFFE_PN0P_ 916 |
| $_SDFFE_PN1N_ 4 |
| $_SDFFE_PN1P_ 285 |
| $_SDFFE_PP0P_ 20 |
| $_SDFFE_PP1N_ 2 |
| $_SDFFE_PP1P_ 11 |
| $_SDFF_PN0_ 181 |
| $_SDFF_PN1_ 3 |
| $_SDFF_PP0_ 38 |
| $_SDFF_PP1_ 2 |
| $_XNOR_ 246 |
| $_XOR_ 1195 |
| DFFRAM 1 |
| digital_pll 1 |
| |
| 12.27. Executing CHECK pass (checking for obvious problems). |
| checking module mgmt_core.. |
| Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.spi_master.isdo: |
| port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$20770 ($_DFFE_PN0P_) |
| port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$23282 ($_SDFFE_PN0P_) |
| Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [9]: |
| port Y[0] of cell $abc$68314$auto$blifparse.cc:377:parse_blif$87475 ($_ANDNOT_) |
| port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$23289 ($_SDFFE_PN0P_) |
| Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [10]: |
| port Y[0] of cell $abc$68314$auto$blifparse.cc:377:parse_blif$87474 ($_AND_) |
| port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$23290 ($_SDFFE_PN0P_) |
| Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [8]: |
| port Y[0] of cell $abc$68314$auto$blifparse.cc:377:parse_blif$85457 ($_NOT_) |
| port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$23288 ($_SDFFE_PN0P_) |
| Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [3]: |
| port Y[0] of cell $abc$68314$auto$blifparse.cc:377:parse_blif$72106 ($_XOR_) |
| port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$23283 ($_SDFFE_PN0P_) |
| Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [4]: |
| port Y[0] of cell $abc$68314$auto$blifparse.cc:377:parse_blif$72102 ($_NOT_) |
| port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$23284 ($_SDFFE_PN0P_) |
| found and reported 6 problems. |
| |
| 13. Executing SHARE pass (SAT-based resource sharing). |
| |
| 14. Executing OPT pass (performing simple optimizations). |
| |
| 14.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| |
| 14.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \mgmt_core.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \mgmt_core. |
| Performed a total of 0 changes. |
| |
| 14.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\mgmt_core'. |
| Removed a total of 0 cells. |
| |
| 14.6. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 14.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| |
| 14.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module mgmt_core. |
| |
| 14.9. Finished OPT passes. (There is nothing left to do.) |
| |
| 15. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 0 unused cells and 666 unused wires. |
| <suppressed ~666 debug messages> |
| |
| 16. Printing statistics. |
| |
| === mgmt_core === |
| |
| Number of wires: 19734 |
| Number of wire bits: 25430 |
| Number of public wires: 495 |
| Number of public wire bits: 5578 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 23822 |
| $_ANDNOT_ 4581 |
| $_AND_ 962 |
| $_DFFE_NN0P_ 12 |
| $_DFFE_NN1P_ 32 |
| $_DFFE_NP0N_ 3 |
| $_DFFE_NP0P_ 26 |
| $_DFFE_PN0N_ 7 |
| $_DFFE_PN0P_ 182 |
| $_DFFE_PN1N_ 5 |
| $_DFFE_PN1P_ 23 |
| $_DFFE_PN_ 7 |
| $_DFFE_PP0P_ 9 |
| $_DFFE_PP_ 1654 |
| $_DFFSRE_NPPP_ 12 |
| $_DFFSRE_PPPP_ 6 |
| $_DFF_NP0_ 4 |
| $_DFF_NP1_ 1 |
| $_DFF_N_ 2 |
| $_DFF_PN0_ 25 |
| $_DFF_PN1_ 8 |
| $_DFF_PP1_ 1 |
| $_DFF_P_ 152 |
| $_MUX_ 5743 |
| $_NAND_ 761 |
| $_NOR_ 724 |
| $_NOT_ 1113 |
| $_ORNOT_ 608 |
| $_OR_ 4021 |
| $_SDFFCE_PN0P_ 42 |
| $_SDFFCE_PN1P_ 8 |
| $_SDFFCE_PP0P_ 177 |
| $_SDFFCE_PP1P_ 5 |
| $_SDFFE_PN0N_ 1 |
| $_SDFFE_PN0P_ 916 |
| $_SDFFE_PN1N_ 4 |
| $_SDFFE_PN1P_ 285 |
| $_SDFFE_PP0P_ 20 |
| $_SDFFE_PP1N_ 2 |
| $_SDFFE_PP1P_ 11 |
| $_SDFF_PN0_ 181 |
| $_SDFF_PN1_ 3 |
| $_SDFF_PP0_ 38 |
| $_SDFF_PP1_ 2 |
| $_XNOR_ 246 |
| $_XOR_ 1195 |
| DFFRAM 1 |
| digital_pll 1 |
| |
| 17. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). |
| cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_. |
| cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_. |
| cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_. |
| cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_. |
| final dff cell mappings: |
| unmapped dff cell: $_DFF_N_ |
| \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q)); |
| unmapped dff cell: $_DFF_NN0_ |
| unmapped dff cell: $_DFF_NN1_ |
| unmapped dff cell: $_DFF_NP0_ |
| unmapped dff cell: $_DFF_NP1_ |
| \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R)); |
| \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R)); |
| unmapped dff cell: $_DFF_PP0_ |
| unmapped dff cell: $_DFF_PP1_ |
| \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S)); |
| unmapped dff cell: $_DFFSR_NNP_ |
| unmapped dff cell: $_DFFSR_NPN_ |
| unmapped dff cell: $_DFFSR_NPP_ |
| unmapped dff cell: $_DFFSR_PNN_ |
| unmapped dff cell: $_DFFSR_PNP_ |
| unmapped dff cell: $_DFFSR_PPN_ |
| unmapped dff cell: $_DFFSR_PPP_ |
| |
| 17.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). |
| Mapping DFF cells in module `\mgmt_core': |
| mapped 18 $_DFFSR_NNN_ cells to \sky130_fd_sc_hd__dfbbn_2 cells. |
| mapped 268 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_4 cells. |
| mapped 70 $_DFF_PN1_ cells to \sky130_fd_sc_hd__dfstp_4 cells. |
| mapped 3510 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_4 cells. |
| |
| 18. Printing statistics. |
| |
| === mgmt_core === |
| |
| Number of wires: 25068 |
| Number of wire bits: 30764 |
| Number of public wires: 495 |
| Number of public wire bits: 5578 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 29132 |
| $_ANDNOT_ 4581 |
| $_AND_ 962 |
| $_MUX_ 10887 |
| $_NAND_ 761 |
| $_NOR_ 724 |
| $_NOT_ 1279 |
| $_ORNOT_ 608 |
| $_OR_ 4021 |
| $_XNOR_ 246 |
| $_XOR_ 1195 |
| DFFRAM 1 |
| digital_pll 1 |
| sky130_fd_sc_hd__dfbbn_2 18 |
| sky130_fd_sc_hd__dfrtp_4 268 |
| sky130_fd_sc_hd__dfstp_4 70 |
| sky130_fd_sc_hd__dfxtp_4 3510 |
| |
| 19. Executing ABC pass (technology mapping using ABC). |
| |
| 19.1. Extracting gate netlist of module `\mgmt_core' to `/tmp/yosys-abc-sDrnpm/input.blif'.. |
| Extracted 25264 gates and 29653 wires to a netlist network with 4387 inputs and 4051 outputs. |
| |
| 19.1.1. Executing ABC. |
| Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-sDrnpm/abc.script 2>&1 |
| ABC: ABC command line: "source /tmp/yosys-abc-sDrnpm/abc.script". |
| ABC: |
| ABC: + read_blif /tmp/yosys-abc-sDrnpm/input.blif |
| ABC: + read_lib -w /project/openlane/mgmt_core/runs/mgmt_core/tmp/trimmed.lib |
| ABC: Parsing finished successfully. Parsing time = 0.02 sec |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4". |
| ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/mgmt_core/runs/mgmt_core/tmp/trimmed.lib" has 43 cells (6 skipped: 6 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.03 sec |
| ABC: Memory = 1.82 MB. Time = 0.03 sec |
| ABC: + read_constr -v /project/openlane/mgmt_core/runs/mgmt_core/tmp/synthesis/yosys.sdc |
| ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8". |
| ABC: Setting output load to be 17.650000. |
| ABC: + read_constr /project/openlane/mgmt_core/runs/mgmt_core/tmp/synthesis/yosys.sdc |
| ABC: + fx |
| ABC: + mfs |
| ABC: + strash |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + retime -D -D 50000 -M 5 |
| ABC: + scleanup |
| ABC: Error: The network is combinational. |
| ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 |
| ABC: + retime -D -D 50000 |
| ABC: + buffer -N 4 -S 5000.0 |
| ABC: Node 10356 has dup fanin 10352. |
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| ABC: Node 12922 has dup fanin 8713. |
| ABC: Node 12922 has dup fanin 12913. |
| ABC: Node 12930 has dup fanin 8716. |
| ABC: Node 12930 has dup fanin 12929. |
| ABC: Node 12930 has dup fanin 8716. |
| ABC: Node 12930 has dup fanin 12929. |
| ABC: Node 12933 has dup fanin 8718. |
| ABC: Node 12933 has dup fanin 12932. |
| ABC: Node 12933 has dup fanin 8718. |
| ABC: Node 12933 has dup fanin 12932. |
| ABC: Node 12935 has dup fanin 8719. |
| ABC: Node 12935 has dup fanin 12934. |
| ABC: Node 12935 has dup fanin 8719. |
| ABC: Node 12935 has dup fanin 12934. |
| ABC: Node 12940 has dup fanin 8717. |
| ABC: Node 12940 has dup fanin 12931. |
| ABC: Node 12940 has dup fanin 8717. |
| ABC: Node 12940 has dup fanin 12931. |
| ABC: Node 12948 has dup fanin 8720. |
| ABC: Node 12948 has dup fanin 12947. |
| ABC: Node 12948 has dup fanin 8720. |
| ABC: Node 12948 has dup fanin 12947. |
| ABC: Node 12951 has dup fanin 8722. |
| ABC: Node 12951 has dup fanin 12950. |
| ABC: Node 12951 has dup fanin 8722. |
| ABC: Node 12951 has dup fanin 12950. |
| ABC: Node 12953 has dup fanin 8723. |
| ABC: Node 12953 has dup fanin 12952. |
| ABC: Node 12953 has dup fanin 8723. |
| ABC: Node 12953 has dup fanin 12952. |
| ABC: Node 12958 has dup fanin 8721. |
| ABC: Node 12958 has dup fanin 12949. |
| ABC: Node 12958 has dup fanin 8721. |
| ABC: Node 12958 has dup fanin 12949. |
| ABC: Node 12966 has dup fanin 8724. |
| ABC: Node 12966 has dup fanin 12965. |
| ABC: Node 12966 has dup fanin 8724. |
| ABC: Node 12966 has dup fanin 12965. |
| ABC: Node 12969 has dup fanin 8726. |
| ABC: Node 12969 has dup fanin 12968. |
| ABC: Node 12969 has dup fanin 8726. |
| ABC: Node 12969 has dup fanin 12968. |
| ABC: Node 12971 has dup fanin 8727. |
| ABC: Node 12971 has dup fanin 12970. |
| ABC: Node 12971 has dup fanin 8727. |
| ABC: Node 12971 has dup fanin 12970. |
| ABC: Node 12976 has dup fanin 8725. |
| ABC: Node 12976 has dup fanin 12967. |
| ABC: Node 12976 has dup fanin 8725. |
| ABC: Node 12976 has dup fanin 12967. |
| ABC: Node 12984 has dup fanin 8728. |
| ABC: Node 12984 has dup fanin 12983. |
| ABC: Node 12984 has dup fanin 8728. |
| ABC: Node 12984 has dup fanin 12983. |
| ABC: Node 12987 has dup fanin 8730. |
| ABC: Node 12987 has dup fanin 12986. |
| ABC: Node 12987 has dup fanin 8730. |
| ABC: Node 12987 has dup fanin 12986. |
| ABC: Node 12989 has dup fanin 8731. |
| ABC: Node 12989 has dup fanin 12988. |
| ABC: Node 12989 has dup fanin 8731. |
| ABC: Node 12989 has dup fanin 12988. |
| ABC: Node 12994 has dup fanin 8729. |
| ABC: Node 12994 has dup fanin 12985. |
| ABC: Node 12994 has dup fanin 8729. |
| ABC: Node 12994 has dup fanin 12985. |
| ABC: Node 13002 has dup fanin 8732. |
| ABC: Node 13002 has dup fanin 13001. |
| ABC: Node 13002 has dup fanin 8732. |
| ABC: Node 13002 has dup fanin 13001. |
| ABC: Node 13005 has dup fanin 8734. |
| ABC: Node 13005 has dup fanin 13004. |
| ABC: Node 13005 has dup fanin 8734. |
| ABC: Node 13005 has dup fanin 13004. |
| ABC: Node 13007 has dup fanin 8735. |
| ABC: Node 13007 has dup fanin 13006. |
| ABC: Node 13007 has dup fanin 8735. |
| ABC: Node 13007 has dup fanin 13006. |
| ABC: Node 13012 has dup fanin 8733. |
| ABC: Node 13012 has dup fanin 13003. |
| ABC: Node 13012 has dup fanin 8733. |
| ABC: Node 13012 has dup fanin 13003. |
| ABC: Node 13020 has dup fanin 8736. |
| ABC: Node 13020 has dup fanin 13019. |
| ABC: Node 13020 has dup fanin 8736. |
| ABC: Node 13020 has dup fanin 13019. |
| ABC: Node 13023 has dup fanin 8738. |
| ABC: Node 13023 has dup fanin 13022. |
| ABC: Node 13023 has dup fanin 8738. |
| ABC: Node 13023 has dup fanin 13022. |
| ABC: Node 13025 has dup fanin 8739. |
| ABC: Node 13025 has dup fanin 13024. |
| ABC: Node 13025 has dup fanin 8739. |
| ABC: Node 13025 has dup fanin 13024. |
| ABC: Node 13030 has dup fanin 8737. |
| ABC: Node 13030 has dup fanin 13021. |
| ABC: Node 13030 has dup fanin 8737. |
| ABC: Node 13030 has dup fanin 13021. |
| ABC: Node 13038 has dup fanin 8740. |
| ABC: Node 13038 has dup fanin 13037. |
| ABC: Node 13038 has dup fanin 8740. |
| ABC: Node 13038 has dup fanin 13037. |
| ABC: Node 13043 has dup fanin 8701. |
| ABC: Node 13043 has dup fanin 8743. |
| ABC: Node 13043 has dup fanin 8701. |
| ABC: Node 13043 has dup fanin 8743. |
| ABC: Node 13048 has dup fanin 8741. |
| ABC: Node 13048 has dup fanin 13039. |
| ABC: Node 13048 has dup fanin 8741. |
| ABC: Node 13048 has dup fanin 13039. |
| ABC: Node 13063 has dup fanin 8702. |
| ABC: Node 13063 has dup fanin 8747. |
| ABC: Node 13063 has dup fanin 8702. |
| ABC: Node 13063 has dup fanin 8747. |
| ABC: Node 13083 has dup fanin 8703. |
| ABC: Node 13083 has dup fanin 8751. |
| ABC: Node 13083 has dup fanin 8703. |
| ABC: Node 13083 has dup fanin 8751. |
| ABC: Node 13103 has dup fanin 8704. |
| ABC: Node 13103 has dup fanin 8755. |
| ABC: Node 13103 has dup fanin 8704. |
| ABC: Node 13103 has dup fanin 8755. |
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| ABC: Node 13123 has dup fanin 8759. |
| ABC: Node 13123 has dup fanin 8705. |
| ABC: Node 13123 has dup fanin 8759. |
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| ABC: Node 13143 has dup fanin 8763. |
| ABC: Node 13143 has dup fanin 8706. |
| ABC: Node 13143 has dup fanin 8763. |
| ABC: Node 13163 has dup fanin 8707. |
| ABC: Node 13163 has dup fanin 8767. |
| ABC: Node 13163 has dup fanin 8707. |
| ABC: Node 13163 has dup fanin 8767. |
| ABC: Node 13195 has dup fanin 8709. |
| ABC: Node 13195 has dup fanin 13194. |
| ABC: Node 13195 has dup fanin 8709. |
| ABC: Node 13195 has dup fanin 13194. |
| ABC: Node 13197 has dup fanin 8710. |
| ABC: Node 13197 has dup fanin 13196. |
| ABC: Node 13197 has dup fanin 8710. |
| ABC: Node 13197 has dup fanin 13196. |
| ABC: Node 13199 has dup fanin 8711. |
| ABC: Node 13199 has dup fanin 13198. |
| ABC: Node 13199 has dup fanin 8711. |
| ABC: Node 13199 has dup fanin 13198. |
| ABC: Node 13206 has dup fanin 8708. |
| ABC: Node 13206 has dup fanin 13205. |
| ABC: Node 13206 has dup fanin 8708. |
| ABC: Node 13206 has dup fanin 13205. |
| ABC: Node 13388 has dup fanin 735. |
| ABC: Node 13388 has dup fanin 735. |
| ABC: Node 13416 has dup fanin 735. |
| ABC: Node 13416 has dup fanin 735. |
| ABC: Node 13440 has dup fanin 735. |
| ABC: Node 13440 has dup fanin 735. |
| ABC: Node 13489 has dup fanin 13387. |
| ABC: Node 13489 has dup fanin 13387. |
| ABC: Node 13541 has dup fanin 536. |
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| ABC: Node 13541 has dup fanin 536. |
| ABC: Node 13541 has dup fanin 9477. |
| ABC: Node 13548 has dup fanin 541. |
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| ABC: Node 13548 has dup fanin 541. |
| ABC: Node 13548 has dup fanin 9481. |
| ABC: Node 13549 has dup fanin 542. |
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| ABC: Node 13549 has dup fanin 542. |
| ABC: Node 13549 has dup fanin 9482. |
| ABC: Node 13550 has dup fanin 543. |
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| ABC: Node 13550 has dup fanin 543. |
| ABC: Node 13550 has dup fanin 9483. |
| ABC: Node 13553 has dup fanin 545. |
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| ABC: Node 13553 has dup fanin 545. |
| ABC: Node 13553 has dup fanin 9485. |
| ABC: Node 13554 has dup fanin 546. |
| ABC: Node 13554 has dup fanin 9486. |
| ABC: Node 13554 has dup fanin 546. |
| ABC: Node 13554 has dup fanin 9486. |
| ABC: Node 13555 has dup fanin 547. |
| ABC: Node 13555 has dup fanin 9487. |
| ABC: Node 13555 has dup fanin 547. |
| ABC: Node 13555 has dup fanin 9487. |
| ABC: Node 13558 has dup fanin 549. |
| ABC: Node 13558 has dup fanin 9489. |
| ABC: Node 13558 has dup fanin 549. |
| ABC: Node 13558 has dup fanin 9489. |
| ABC: Node 13559 has dup fanin 550. |
| ABC: Node 13559 has dup fanin 9490. |
| ABC: Node 13559 has dup fanin 550. |
| ABC: Node 13559 has dup fanin 9490. |
| ABC: Node 13560 has dup fanin 551. |
| ABC: Node 13560 has dup fanin 9491. |
| ABC: Node 13560 has dup fanin 551. |
| ABC: Node 13560 has dup fanin 9491. |
| ABC: Node 13581 has dup fanin 562. |
| ABC: Node 13581 has dup fanin 9502. |
| ABC: Node 13581 has dup fanin 562. |
| ABC: Node 13581 has dup fanin 9502. |
| ABC: Node 13582 has dup fanin 563. |
| ABC: Node 13582 has dup fanin 9503. |
| ABC: Node 13582 has dup fanin 563. |
| ABC: Node 13582 has dup fanin 9503. |
| ABC: Node 13786 has dup fanin 13785. |
| ABC: Node 13786 has dup fanin 13785. |
| ABC: Node 13804 has dup fanin 9600. |
| ABC: Node 13804 has dup fanin 9684. |
| ABC: Node 13804 has dup fanin 9600. |
| ABC: Node 13804 has dup fanin 9684. |
| ABC: Node 13966 has dup fanin 9830. |
| ABC: Node 13966 has dup fanin 13965. |
| ABC: Node 13966 has dup fanin 9830. |
| ABC: Node 13966 has dup fanin 13965. |
| ABC: Node 14014 has dup fanin 8960. |
| ABC: Node 14014 has dup fanin 14013. |
| ABC: Node 14014 has dup fanin 8960. |
| ABC: Node 14014 has dup fanin 14013. |
| ABC: Node 14016 has dup fanin 8958. |
| ABC: Node 14016 has dup fanin 14015. |
| ABC: Node 14016 has dup fanin 8958. |
| ABC: Node 14016 has dup fanin 14015. |
| ABC: Node 14023 has dup fanin 8932. |
| ABC: Node 14023 has dup fanin 14022. |
| ABC: Node 14023 has dup fanin 8932. |
| ABC: Node 14023 has dup fanin 14022. |
| ABC: Node 14027 has dup fanin 8930. |
| ABC: Node 14027 has dup fanin 14026. |
| ABC: Node 14027 has dup fanin 8930. |
| ABC: Node 14027 has dup fanin 14026. |
| ABC: Node 14029 has dup fanin 13963. |
| ABC: Node 14029 has dup fanin 14028. |
| ABC: Node 14029 has dup fanin 13963. |
| ABC: Node 14029 has dup fanin 14028. |
| ABC: Node 14032 has dup fanin 763. |
| ABC: Node 14032 has dup fanin 14031. |
| ABC: Node 14032 has dup fanin 763. |
| ABC: Node 14032 has dup fanin 14031. |
| ABC: Node 14061 has dup fanin 763. |
| ABC: Node 14061 has dup fanin 9829. |
| ABC: Node 14061 has dup fanin 763. |
| ABC: Node 14061 has dup fanin 9829. |
| ABC: Node 14402 has dup fanin 14401. |
| ABC: Node 14402 has dup fanin 14401. |
| ABC: Node 14404 has dup fanin 14403. |
| ABC: Node 14404 has dup fanin 14403. |
| ABC: Node 14405 has dup fanin 14403. |
| ABC: Node 14405 has dup fanin 14403. |
| ABC: Node 14406 has dup fanin 14403. |
| ABC: Node 14406 has dup fanin 14403. |
| ABC: Node 14407 has dup fanin 14403. |
| ABC: Node 14407 has dup fanin 14403. |
| ABC: Node 14408 has dup fanin 14403. |
| ABC: Node 14408 has dup fanin 14403. |
| ABC: Node 14409 has dup fanin 14403. |
| ABC: Node 14409 has dup fanin 14403. |
| ABC: Node 14410 has dup fanin 14403. |
| ABC: Node 14410 has dup fanin 14403. |
| ABC: Node 14411 has dup fanin 14403. |
| ABC: Node 14411 has dup fanin 14403. |
| ABC: Node 14412 has dup fanin 14401. |
| ABC: Node 14412 has dup fanin 14401. |
| ABC: Node 14413 has dup fanin 14401. |
| ABC: Node 14413 has dup fanin 14401. |
| ABC: Node 14414 has dup fanin 14401. |
| ABC: Node 14414 has dup fanin 14401. |
| ABC: Node 14415 has dup fanin 14401. |
| ABC: Node 14415 has dup fanin 14401. |
| ABC: Node 14416 has dup fanin 14401. |
| ABC: Node 14416 has dup fanin 14401. |
| ABC: Node 14417 has dup fanin 14401. |
| ABC: Node 14417 has dup fanin 14401. |
| ABC: Node 14442 has dup fanin 14441. |
| ABC: Node 14442 has dup fanin 14441. |
| ABC: Node 14443 has dup fanin 14441. |
| ABC: Node 14443 has dup fanin 14441. |
| ABC: Node 14444 has dup fanin 14441. |
| ABC: Node 14444 has dup fanin 14441. |
| ABC: Node 14445 has dup fanin 14441. |
| ABC: Node 14445 has dup fanin 14441. |
| ABC: Node 14446 has dup fanin 14441. |
| ABC: Node 14446 has dup fanin 14441. |
| ABC: Node 14447 has dup fanin 14441. |
| ABC: Node 14447 has dup fanin 14441. |
| ABC: Node 14448 has dup fanin 14441. |
| ABC: Node 14448 has dup fanin 14441. |
| ABC: Node 14449 has dup fanin 14441. |
| ABC: Node 14449 has dup fanin 14441. |
| ABC: Node 14453 has dup fanin 14452. |
| ABC: Node 14453 has dup fanin 14452. |
| ABC: Node 14454 has dup fanin 14452. |
| ABC: Node 14454 has dup fanin 14452. |
| ABC: Node 14455 has dup fanin 14452. |
| ABC: Node 14455 has dup fanin 14452. |
| ABC: Node 14456 has dup fanin 14452. |
| ABC: Node 14456 has dup fanin 14452. |
| ABC: Node 14475 has dup fanin 14452. |
| ABC: Node 14475 has dup fanin 14452. |
| ABC: Node 14496 has dup fanin 11491. |
| ABC: Node 14496 has dup fanin 14495. |
| ABC: Node 14496 has dup fanin 11491. |
| ABC: Node 14496 has dup fanin 14495. |
| ABC: Node 14500 has dup fanin 11490. |
| ABC: Node 14500 has dup fanin 14499. |
| ABC: Node 14500 has dup fanin 11490. |
| ABC: Node 14500 has dup fanin 14499. |
| ABC: Node 14504 has dup fanin 14502. |
| ABC: Node 14504 has dup fanin 14503. |
| ABC: Node 14504 has dup fanin 14502. |
| ABC: Node 14504 has dup fanin 14503. |
| ABC: Node 14509 has dup fanin 11467. |
| ABC: Node 14509 has dup fanin 14508. |
| ABC: Node 14509 has dup fanin 11467. |
| ABC: Node 14509 has dup fanin 14508. |
| ABC: Node 14517 has dup fanin 11456. |
| ABC: Node 14517 has dup fanin 14516. |
| ABC: Node 14517 has dup fanin 11456. |
| ABC: Node 14517 has dup fanin 14516. |
| ABC: Node 14530 has dup fanin 733. |
| ABC: Node 14530 has dup fanin 14529. |
| ABC: Node 14530 has dup fanin 733. |
| ABC: Node 14530 has dup fanin 14529. |
| ABC: Node 14546 has dup fanin 11447. |
| ABC: Node 14546 has dup fanin 14545. |
| ABC: Node 14546 has dup fanin 11447. |
| ABC: Node 14546 has dup fanin 14545. |
| ABC: Node 14550 has dup fanin 11461. |
| ABC: Node 14550 has dup fanin 14549. |
| ABC: Node 14550 has dup fanin 11461. |
| ABC: Node 14550 has dup fanin 14549. |
| ABC: Node 14557 has dup fanin 14554. |
| ABC: Node 14557 has dup fanin 14556. |
| ABC: Node 14557 has dup fanin 14554. |
| ABC: Node 14557 has dup fanin 14556. |
| ABC: Node 14559 has dup fanin 11486. |
| ABC: Node 14559 has dup fanin 14558. |
| ABC: Node 14559 has dup fanin 11486. |
| ABC: Node 14559 has dup fanin 14558. |
| ABC: Node 14561 has dup fanin 745. |
| ABC: Node 14561 has dup fanin 14560. |
| ABC: Node 14561 has dup fanin 745. |
| ABC: Node 14561 has dup fanin 14560. |
| ABC: Node 14564 has dup fanin 11485. |
| ABC: Node 14564 has dup fanin 14563. |
| ABC: Node 14564 has dup fanin 11485. |
| ABC: Node 14564 has dup fanin 14563. |
| ABC: Node 14567 has dup fanin 11464. |
| ABC: Node 14567 has dup fanin 14566. |
| ABC: Node 14567 has dup fanin 11464. |
| ABC: Node 14567 has dup fanin 14566. |
| ABC: Node 14570 has dup fanin 8905. |
| ABC: Node 14570 has dup fanin 14569. |
| ABC: Node 14570 has dup fanin 8905. |
| ABC: Node 14570 has dup fanin 14569. |
| ABC: Node 14575 has dup fanin 11452. |
| ABC: Node 14575 has dup fanin 14574. |
| ABC: Node 14575 has dup fanin 11452. |
| ABC: Node 14575 has dup fanin 14574. |
| ABC: Node 14608 has dup fanin 14607. |
| ABC: Node 14608 has dup fanin 14607. |
| ABC: Node 14609 has dup fanin 14607. |
| ABC: Node 14609 has dup fanin 14607. |
| ABC: Node 14610 has dup fanin 14607. |
| ABC: Node 14610 has dup fanin 14607. |
| ABC: Node 14611 has dup fanin 14607. |
| ABC: Node 14611 has dup fanin 14607. |
| ABC: Node 14612 has dup fanin 14607. |
| ABC: Node 14612 has dup fanin 14607. |
| ABC: Node 14613 has dup fanin 14607. |
| ABC: Node 14613 has dup fanin 14607. |
| ABC: Node 14614 has dup fanin 14607. |
| ABC: Node 14614 has dup fanin 14607. |
| ABC: Node 14615 has dup fanin 14607. |
| ABC: Node 14615 has dup fanin 14607. |
| ABC: Node 14616 has dup fanin 13785. |
| ABC: Node 14616 has dup fanin 13785. |
| ABC: Node 14617 has dup fanin 13785. |
| ABC: Node 14617 has dup fanin 13785. |
| ABC: Node 14618 has dup fanin 13785. |
| ABC: Node 14618 has dup fanin 13785. |
| ABC: Node 14619 has dup fanin 13785. |
| ABC: Node 14619 has dup fanin 13785. |
| ABC: Node 14629 has dup fanin 14628. |
| ABC: Node 14629 has dup fanin 14628. |
| ABC: Node 14630 has dup fanin 14628. |
| ABC: Node 14630 has dup fanin 14628. |
| ABC: Node 14631 has dup fanin 14628. |
| ABC: Node 14631 has dup fanin 14628. |
| ABC: Node 14632 has dup fanin 14628. |
| ABC: Node 14632 has dup fanin 14628. |
| ABC: Node 14633 has dup fanin 14628. |
| ABC: Node 14633 has dup fanin 14628. |
| ABC: Node 14634 has dup fanin 14628. |
| ABC: Node 14634 has dup fanin 14628. |
| ABC: Node 14635 has dup fanin 14628. |
| ABC: Node 14635 has dup fanin 14628. |
| ABC: Node 14636 has dup fanin 14628. |
| ABC: Node 14636 has dup fanin 14628. |
| ABC: Node 17484 has dup fanin 17483. |
| ABC: Node 17484 has dup fanin 17483. |
| ABC: Node 17485 has dup fanin 17483. |
| ABC: Node 17485 has dup fanin 17483. |
| ABC: Node 17486 has dup fanin 17483. |
| ABC: Node 17486 has dup fanin 17483. |
| ABC: Node 17487 has dup fanin 17483. |
| ABC: Node 17487 has dup fanin 17483. |
| ABC: Node 17488 has dup fanin 17483. |
| ABC: Node 17488 has dup fanin 17483. |
| ABC: Node 17489 has dup fanin 17483. |
| ABC: Node 17489 has dup fanin 17483. |
| ABC: Node 17490 has dup fanin 17483. |
| ABC: Node 17490 has dup fanin 17483. |
| ABC: Node 17491 has dup fanin 17483. |
| ABC: Node 17491 has dup fanin 17483. |
| ABC: Node 17493 has dup fanin 17492. |
| ABC: Node 17493 has dup fanin 17492. |
| ABC: Node 17494 has dup fanin 17492. |
| ABC: Node 17494 has dup fanin 17492. |
| ABC: Node 17495 has dup fanin 17492. |
| ABC: Node 17495 has dup fanin 17492. |
| ABC: Node 17496 has dup fanin 17492. |
| ABC: Node 17496 has dup fanin 17492. |
| ABC: Node 17497 has dup fanin 17492. |
| ABC: Node 17497 has dup fanin 17492. |
| ABC: Node 17498 has dup fanin 17492. |
| ABC: Node 17498 has dup fanin 17492. |
| ABC: Node 17499 has dup fanin 17492. |
| ABC: Node 17499 has dup fanin 17492. |
| ABC: Node 17500 has dup fanin 17492. |
| ABC: Node 17500 has dup fanin 17492. |
| ABC: Node 17529 has dup fanin 735. |
| ABC: Node 17529 has dup fanin 735. |
| ABC: Node 17542 has dup fanin 17528. |
| ABC: Node 17542 has dup fanin 17528. |
| ABC: Node 17553 has dup fanin 17528. |
| ABC: Node 17553 has dup fanin 17528. |
| ABC: Node 17554 has dup fanin 735. |
| ABC: Node 17554 has dup fanin 735. |
| ABC: Node 17565 has dup fanin 17528. |
| ABC: Node 17565 has dup fanin 17528. |
| ABC: Node 17576 has dup fanin 17528. |
| ABC: Node 17576 has dup fanin 17528. |
| ABC: Node 17587 has dup fanin 17528. |
| ABC: Node 17587 has dup fanin 17528. |
| ABC: Node 17598 has dup fanin 17528. |
| ABC: Node 17598 has dup fanin 17528. |
| ABC: Node 17610 has dup fanin 17528. |
| ABC: Node 17610 has dup fanin 17528. |
| ABC: Node 17616 has dup fanin 134. |
| ABC: Node 17616 has dup fanin 1067. |
| ABC: Node 17616 has dup fanin 134. |
| ABC: Node 17616 has dup fanin 1067. |
| ABC: Node 19372 has dup fanin 1629. |
| ABC: Node 19372 has dup fanin 1629. |
| ABC: Node 20029 has dup fanin 1687. |
| ABC: Node 20029 has dup fanin 20019. |
| ABC: Node 20029 has dup fanin 1687. |
| ABC: Node 20029 has dup fanin 20019. |
| ABC: Node 20034 has dup fanin 14401. |
| ABC: Node 20034 has dup fanin 14401. |
| ABC: Node 20067 has dup fanin 20066. |
| ABC: Node 20067 has dup fanin 20066. |
| ABC: Node 20068 has dup fanin 20066. |
| ABC: Node 20068 has dup fanin 20066. |
| ABC: Node 20069 has dup fanin 20066. |
| ABC: Node 20069 has dup fanin 20066. |
| ABC: Node 20070 has dup fanin 20066. |
| ABC: Node 20070 has dup fanin 20066. |
| ABC: Node 20071 has dup fanin 20066. |
| ABC: Node 20071 has dup fanin 20066. |
| ABC: Node 20072 has dup fanin 20066. |
| ABC: Node 20072 has dup fanin 20066. |
| ABC: Node 20073 has dup fanin 20066. |
| ABC: Node 20073 has dup fanin 20066. |
| ABC: Node 20074 has dup fanin 20066. |
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| ABC: Node 20105 has dup fanin 9422. |
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| ABC: Node 20105 has dup fanin 9422. |
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| ABC: Node 20116 has dup fanin 8871. |
| ABC: Node 20116 has dup fanin 8871. |
| ABC: Node 21473 has dup fanin 8607. |
| ABC: Node 21473 has dup fanin 9965. |
| ABC: Node 21473 has dup fanin 8607. |
| ABC: Node 21473 has dup fanin 9965. |
| ABC: Node 21478 has dup fanin 8612. |
| ABC: Node 21478 has dup fanin 9960. |
| ABC: Node 21478 has dup fanin 8612. |
| ABC: Node 21478 has dup fanin 9960. |
| ABC: Node 21479 has dup fanin 8613. |
| ABC: Node 21479 has dup fanin 9959. |
| ABC: Node 21479 has dup fanin 8613. |
| ABC: Node 21479 has dup fanin 9959. |
| ABC: Node 21498 has dup fanin 8632. |
| ABC: Node 21498 has dup fanin 9940. |
| ABC: Node 21498 has dup fanin 8632. |
| ABC: Node 21498 has dup fanin 9940. |
| ABC: Node 21499 has dup fanin 8633. |
| ABC: Node 21499 has dup fanin 9939. |
| ABC: Node 21499 has dup fanin 8633. |
| ABC: Node 21499 has dup fanin 9939. |
| ABC: Node 21502 has dup fanin 8636. |
| ABC: Node 21502 has dup fanin 9936. |
| ABC: Node 21502 has dup fanin 8636. |
| ABC: Node 21502 has dup fanin 9936. |
| ABC: Node 22274 has dup fanin 3898. |
| ABC: Node 22274 has dup fanin 22273. |
| ABC: Node 22274 has dup fanin 3898. |
| ABC: Node 22274 has dup fanin 22273. |
| ABC: Node 22563 has dup fanin 11833. |
| ABC: Node 22563 has dup fanin 11833. |
| ABC: Node 22568 has dup fanin 11833. |
| ABC: Node 22568 has dup fanin 11833. |
| ABC: Node 22590 has dup fanin 1787. |
| ABC: Node 22590 has dup fanin 1788. |
| ABC: Node 22590 has dup fanin 1787. |
| ABC: Node 22590 has dup fanin 1788. |
| ABC: Node 22599 has dup fanin 1771. |
| ABC: Node 22599 has dup fanin 1771. |
| ABC: Node 22608 has dup fanin 21212. |
| ABC: Node 22608 has dup fanin 21212. |
| ABC: Node 22618 has dup fanin 11850. |
| ABC: Node 22618 has dup fanin 11850. |
| ABC: Node 22623 has dup fanin 11850. |
| ABC: Node 22623 has dup fanin 11850. |
| ABC: Node 22645 has dup fanin 1796. |
| ABC: Node 22645 has dup fanin 1797. |
| ABC: Node 22645 has dup fanin 1796. |
| ABC: Node 22645 has dup fanin 1797. |
| ABC: Node 22654 has dup fanin 1776. |
| ABC: Node 22654 has dup fanin 1776. |
| ABC: Node 22663 has dup fanin 21229. |
| ABC: Node 22663 has dup fanin 21229. |
| ABC: Node 22713 has dup fanin 22673. |
| ABC: Node 22713 has dup fanin 22673. |
| ABC: Node 22719 has dup fanin 22673. |
| ABC: Node 22719 has dup fanin 22673. |
| ABC: Node 22725 has dup fanin 22673. |
| ABC: Node 22725 has dup fanin 22673. |
| ABC: Node 22731 has dup fanin 22673. |
| ABC: Node 22731 has dup fanin 22673. |
| ABC: Node 22737 has dup fanin 22673. |
| ABC: Node 22737 has dup fanin 22673. |
| ABC: Node 22743 has dup fanin 22673. |
| ABC: Node 22743 has dup fanin 22673. |
| ABC: Node 22749 has dup fanin 22673. |
| ABC: Node 22749 has dup fanin 22673. |
| ABC: Node 22755 has dup fanin 22673. |
| ABC: Node 22755 has dup fanin 22673. |
| ABC: Node 22761 has dup fanin 22673. |
| ABC: Node 22761 has dup fanin 22673. |
| ABC: Node 22767 has dup fanin 22673. |
| ABC: Node 22767 has dup fanin 22673. |
| ABC: Node 22773 has dup fanin 22673. |
| ABC: Node 22773 has dup fanin 22673. |
| ABC: Node 22779 has dup fanin 22673. |
| ABC: Node 22779 has dup fanin 22673. |
| ABC: Node 22785 has dup fanin 22673. |
| ABC: Node 22785 has dup fanin 22673. |
| ABC: Node 22791 has dup fanin 22673. |
| ABC: Node 22791 has dup fanin 22673. |
| ABC: Node 22797 has dup fanin 22673. |
| ABC: Node 22797 has dup fanin 22673. |
| ABC: Node 22803 has dup fanin 22673. |
| ABC: Node 22803 has dup fanin 22673. |
| ABC: Node 22809 has dup fanin 22673. |
| ABC: Node 22809 has dup fanin 22673. |
| ABC: Node 22815 has dup fanin 22673. |
| ABC: Node 22815 has dup fanin 22673. |
| ABC: Node 22821 has dup fanin 22673. |
| ABC: Node 22821 has dup fanin 22673. |
| ABC: Node 22827 has dup fanin 22673. |
| ABC: Node 22827 has dup fanin 22673. |
| ABC: Node 22833 has dup fanin 22673. |
| ABC: Node 22833 has dup fanin 22673. |
| ABC: Node 22839 has dup fanin 22673. |
| ABC: Node 22839 has dup fanin 22673. |
| ABC: Node 22845 has dup fanin 22673. |
| ABC: Node 22845 has dup fanin 22673. |
| ABC: Node 22851 has dup fanin 22673. |
| ABC: Node 22851 has dup fanin 22673. |
| ABC: Node 22857 has dup fanin 22673. |
| ABC: Node 22857 has dup fanin 22673. |
| ABC: Node 22863 has dup fanin 22673. |
| ABC: Node 22863 has dup fanin 22673. |
| ABC: Node 22869 has dup fanin 22673. |
| ABC: Node 22869 has dup fanin 22673. |
| ABC: Node 22875 has dup fanin 22673. |
| ABC: Node 22875 has dup fanin 22673. |
| ABC: Node 22881 has dup fanin 22673. |
| ABC: Node 22881 has dup fanin 22673. |
| ABC: Node 22887 has dup fanin 22673. |
| ABC: Node 22887 has dup fanin 22673. |
| ABC: Node 22893 has dup fanin 22673. |
| ABC: Node 22893 has dup fanin 22673. |
| ABC: Node 22901 has dup fanin 22673. |
| ABC: Node 22901 has dup fanin 22673. |
| ABC: Node 22903 has dup fanin 22902. |
| ABC: Node 22903 has dup fanin 22902. |
| ABC: Node 22904 has dup fanin 22902. |
| ABC: Node 22904 has dup fanin 22902. |
| ABC: Node 22905 has dup fanin 22902. |
| ABC: Node 22905 has dup fanin 22902. |
| ABC: Node 22906 has dup fanin 22902. |
| ABC: Node 22906 has dup fanin 22902. |
| ABC: Node 22907 has dup fanin 22902. |
| ABC: Node 22907 has dup fanin 22902. |
| ABC: Node 22908 has dup fanin 22902. |
| ABC: Node 22908 has dup fanin 22902. |
| ABC: Node 22909 has dup fanin 22902. |
| ABC: Node 22909 has dup fanin 22902. |
| ABC: Node 22910 has dup fanin 22902. |
| ABC: Node 22910 has dup fanin 22902. |
| ABC: Node 22911 has dup fanin 22902. |
| ABC: Node 22911 has dup fanin 22902. |
| ABC: Node 22912 has dup fanin 22902. |
| ABC: Node 22912 has dup fanin 22902. |
| ABC: Node 22913 has dup fanin 22902. |
| ABC: Node 22913 has dup fanin 22902. |
| ABC: Node 22914 has dup fanin 22902. |
| ABC: Node 22914 has dup fanin 22902. |
| ABC: Node 22915 has dup fanin 22902. |
| ABC: Node 22915 has dup fanin 22902. |
| ABC: Node 22916 has dup fanin 22902. |
| ABC: Node 22916 has dup fanin 22902. |
| ABC: Node 22917 has dup fanin 22902. |
| ABC: Node 22917 has dup fanin 22902. |
| ABC: Node 22918 has dup fanin 22902. |
| ABC: Node 22918 has dup fanin 22902. |
| ABC: Node 22919 has dup fanin 22902. |
| ABC: Node 22919 has dup fanin 22902. |
| ABC: Node 22920 has dup fanin 22902. |
| ABC: Node 22920 has dup fanin 22902. |
| ABC: Node 22921 has dup fanin 22902. |
| ABC: Node 22921 has dup fanin 22902. |
| ABC: Node 22922 has dup fanin 22902. |
| ABC: Node 22922 has dup fanin 22902. |
| ABC: Node 22923 has dup fanin 22902. |
| ABC: Node 22923 has dup fanin 22902. |
| ABC: Node 22924 has dup fanin 22902. |
| ABC: Node 22924 has dup fanin 22902. |
| ABC: Node 22925 has dup fanin 22902. |
| ABC: Node 22925 has dup fanin 22902. |
| ABC: Node 22926 has dup fanin 22902. |
| ABC: Node 22926 has dup fanin 22902. |
| ABC: Node 22927 has dup fanin 22902. |
| ABC: Node 22927 has dup fanin 22902. |
| ABC: Node 22928 has dup fanin 22902. |
| ABC: Node 22928 has dup fanin 22902. |
| ABC: Node 22929 has dup fanin 22902. |
| ABC: Node 22929 has dup fanin 22902. |
| ABC: Node 22930 has dup fanin 22902. |
| ABC: Node 22930 has dup fanin 22902. |
| ABC: Node 22931 has dup fanin 22902. |
| ABC: Node 22931 has dup fanin 22902. |
| ABC: Node 22932 has dup fanin 22902. |
| ABC: Node 22932 has dup fanin 22902. |
| ABC: Node 22933 has dup fanin 22902. |
| ABC: Node 22933 has dup fanin 22902. |
| ABC: Node 22934 has dup fanin 22902. |
| ABC: Node 22934 has dup fanin 22902. |
| ABC: Node 22936 has dup fanin 22935. |
| ABC: Node 22936 has dup fanin 22935. |
| ABC: Node 22937 has dup fanin 22935. |
| ABC: Node 22937 has dup fanin 22935. |
| ABC: Node 22938 has dup fanin 22935. |
| ABC: Node 22938 has dup fanin 22935. |
| ABC: Node 22939 has dup fanin 22935. |
| ABC: Node 22939 has dup fanin 22935. |
| ABC: Node 22940 has dup fanin 22935. |
| ABC: Node 22940 has dup fanin 22935. |
| ABC: Node 22941 has dup fanin 22935. |
| ABC: Node 22941 has dup fanin 22935. |
| ABC: Node 22942 has dup fanin 22935. |
| ABC: Node 22942 has dup fanin 22935. |
| ABC: Node 22943 has dup fanin 22935. |
| ABC: Node 22943 has dup fanin 22935. |
| ABC: Node 22944 has dup fanin 22935. |
| ABC: Node 22944 has dup fanin 22935. |
| ABC: Node 22945 has dup fanin 22935. |
| ABC: Node 22945 has dup fanin 22935. |
| ABC: Node 22946 has dup fanin 22935. |
| ABC: Node 22946 has dup fanin 22935. |
| ABC: Node 22947 has dup fanin 22935. |
| ABC: Node 22947 has dup fanin 22935. |
| ABC: Node 22948 has dup fanin 22935. |
| ABC: Node 22948 has dup fanin 22935. |
| ABC: Node 22949 has dup fanin 22935. |
| ABC: Node 22949 has dup fanin 22935. |
| ABC: Node 22950 has dup fanin 22935. |
| ABC: Node 22950 has dup fanin 22935. |
| ABC: Node 22951 has dup fanin 22935. |
| ABC: Node 22951 has dup fanin 22935. |
| ABC: Node 22952 has dup fanin 22935. |
| ABC: Node 22952 has dup fanin 22935. |
| ABC: Node 22953 has dup fanin 22935. |
| ABC: Node 22953 has dup fanin 22935. |
| ABC: Node 22954 has dup fanin 22935. |
| ABC: Node 22954 has dup fanin 22935. |
| ABC: Node 22955 has dup fanin 22935. |
| ABC: Node 22955 has dup fanin 22935. |
| ABC: Node 22956 has dup fanin 22935. |
| ABC: Node 22956 has dup fanin 22935. |
| ABC: Node 22957 has dup fanin 22935. |
| ABC: Node 22957 has dup fanin 22935. |
| ABC: Node 22958 has dup fanin 22935. |
| ABC: Node 22958 has dup fanin 22935. |
| ABC: Node 22959 has dup fanin 22935. |
| ABC: Node 22959 has dup fanin 22935. |
| ABC: Node 22960 has dup fanin 22935. |
| ABC: Node 22960 has dup fanin 22935. |
| ABC: Node 22961 has dup fanin 22935. |
| ABC: Node 22961 has dup fanin 22935. |
| ABC: Node 22962 has dup fanin 22935. |
| ABC: Node 22962 has dup fanin 22935. |
| ABC: Node 22963 has dup fanin 22935. |
| ABC: Node 22963 has dup fanin 22935. |
| ABC: Node 22964 has dup fanin 22935. |
| ABC: Node 22964 has dup fanin 22935. |
| ABC: Node 22965 has dup fanin 22935. |
| ABC: Node 22965 has dup fanin 22935. |
| ABC: Node 22966 has dup fanin 22935. |
| ABC: Node 22966 has dup fanin 22935. |
| ABC: Node 22967 has dup fanin 22935. |
| ABC: Node 22967 has dup fanin 22935. |
| ABC: Node 22969 has dup fanin 22968. |
| ABC: Node 22969 has dup fanin 22968. |
| ABC: Node 22970 has dup fanin 22968. |
| ABC: Node 22970 has dup fanin 22968. |
| ABC: Node 22971 has dup fanin 22968. |
| ABC: Node 22971 has dup fanin 22968. |
| ABC: Node 22972 has dup fanin 22968. |
| ABC: Node 22972 has dup fanin 22968. |
| ABC: Node 22973 has dup fanin 22968. |
| ABC: Node 22973 has dup fanin 22968. |
| ABC: Node 22974 has dup fanin 22968. |
| ABC: Node 22974 has dup fanin 22968. |
| ABC: Node 22975 has dup fanin 22968. |
| ABC: Node 22975 has dup fanin 22968. |
| ABC: Node 22976 has dup fanin 22968. |
| ABC: Node 22976 has dup fanin 22968. |
| ABC: Node 22977 has dup fanin 22968. |
| ABC: Node 22977 has dup fanin 22968. |
| ABC: Node 22978 has dup fanin 22968. |
| ABC: Node 22978 has dup fanin 22968. |
| ABC: Node 22979 has dup fanin 22968. |
| ABC: Node 22979 has dup fanin 22968. |
| ABC: Node 22980 has dup fanin 22968. |
| ABC: Node 22980 has dup fanin 22968. |
| ABC: Node 22981 has dup fanin 22968. |
| ABC: Node 22981 has dup fanin 22968. |
| ABC: Node 22982 has dup fanin 22968. |
| ABC: Node 22982 has dup fanin 22968. |
| ABC: Node 22983 has dup fanin 22968. |
| ABC: Node 22983 has dup fanin 22968. |
| ABC: Node 22984 has dup fanin 22968. |
| ABC: Node 22984 has dup fanin 22968. |
| ABC: Node 22985 has dup fanin 22968. |
| ABC: Node 22985 has dup fanin 22968. |
| ABC: Node 22986 has dup fanin 22968. |
| ABC: Node 22986 has dup fanin 22968. |
| ABC: Node 22987 has dup fanin 22968. |
| ABC: Node 22987 has dup fanin 22968. |
| ABC: Node 22988 has dup fanin 22968. |
| ABC: Node 22988 has dup fanin 22968. |
| ABC: Node 22989 has dup fanin 22968. |
| ABC: Node 22989 has dup fanin 22968. |
| ABC: Node 22990 has dup fanin 22968. |
| ABC: Node 22990 has dup fanin 22968. |
| ABC: Node 22991 has dup fanin 22968. |
| ABC: Node 22991 has dup fanin 22968. |
| ABC: Node 22992 has dup fanin 22968. |
| ABC: Node 22992 has dup fanin 22968. |
| ABC: Node 22993 has dup fanin 22968. |
| ABC: Node 22993 has dup fanin 22968. |
| ABC: Node 22994 has dup fanin 22968. |
| ABC: Node 22994 has dup fanin 22968. |
| ABC: Node 22995 has dup fanin 22968. |
| ABC: Node 22995 has dup fanin 22968. |
| ABC: Node 22996 has dup fanin 22968. |
| ABC: Node 22996 has dup fanin 22968. |
| ABC: Node 22997 has dup fanin 22968. |
| ABC: Node 22997 has dup fanin 22968. |
| ABC: Node 22998 has dup fanin 22968. |
| ABC: Node 22998 has dup fanin 22968. |
| ABC: Node 22999 has dup fanin 22968. |
| ABC: Node 22999 has dup fanin 22968. |
| ABC: Node 23000 has dup fanin 22968. |
| ABC: Node 23000 has dup fanin 22968. |
| ABC: Node 23003 has dup fanin 23002. |
| ABC: Node 23003 has dup fanin 23002. |
| ABC: Node 23004 has dup fanin 23002. |
| ABC: Node 23004 has dup fanin 23002. |
| ABC: Node 23005 has dup fanin 23002. |
| ABC: Node 23005 has dup fanin 23002. |
| ABC: Node 23006 has dup fanin 23002. |
| ABC: Node 23006 has dup fanin 23002. |
| ABC: Node 23007 has dup fanin 23002. |
| ABC: Node 23007 has dup fanin 23002. |
| ABC: Node 23008 has dup fanin 23002. |
| ABC: Node 23008 has dup fanin 23002. |
| ABC: Node 23009 has dup fanin 23002. |
| ABC: Node 23009 has dup fanin 23002. |
| ABC: Node 23010 has dup fanin 23002. |
| ABC: Node 23010 has dup fanin 23002. |
| ABC: Node 23011 has dup fanin 23002. |
| ABC: Node 23011 has dup fanin 23002. |
| ABC: Node 23012 has dup fanin 23002. |
| ABC: Node 23012 has dup fanin 23002. |
| ABC: Node 23013 has dup fanin 23002. |
| ABC: Node 23013 has dup fanin 23002. |
| ABC: Node 23014 has dup fanin 23002. |
| ABC: Node 23014 has dup fanin 23002. |
| ABC: Node 23015 has dup fanin 23002. |
| ABC: Node 23015 has dup fanin 23002. |
| ABC: Node 23016 has dup fanin 23002. |
| ABC: Node 23016 has dup fanin 23002. |
| ABC: Node 23017 has dup fanin 23002. |
| ABC: Node 23017 has dup fanin 23002. |
| ABC: Node 23018 has dup fanin 23002. |
| ABC: Node 23018 has dup fanin 23002. |
| ABC: Node 23019 has dup fanin 23002. |
| ABC: Node 23019 has dup fanin 23002. |
| ABC: Node 23020 has dup fanin 23002. |
| ABC: Node 23020 has dup fanin 23002. |
| ABC: Node 23021 has dup fanin 23002. |
| ABC: Node 23021 has dup fanin 23002. |
| ABC: Node 23022 has dup fanin 23002. |
| ABC: Node 23022 has dup fanin 23002. |
| ABC: Node 23023 has dup fanin 23002. |
| ABC: Node 23023 has dup fanin 23002. |
| ABC: Node 23024 has dup fanin 23002. |
| ABC: Node 23024 has dup fanin 23002. |
| ABC: Node 23025 has dup fanin 23002. |
| ABC: Node 23025 has dup fanin 23002. |
| ABC: Node 23026 has dup fanin 23002. |
| ABC: Node 23026 has dup fanin 23002. |
| ABC: Node 23027 has dup fanin 23002. |
| ABC: Node 23027 has dup fanin 23002. |
| ABC: Node 23028 has dup fanin 23002. |
| ABC: Node 23028 has dup fanin 23002. |
| ABC: Node 23029 has dup fanin 23002. |
| ABC: Node 23029 has dup fanin 23002. |
| ABC: Node 23030 has dup fanin 23002. |
| ABC: Node 23030 has dup fanin 23002. |
| ABC: Node 23031 has dup fanin 23002. |
| ABC: Node 23031 has dup fanin 23002. |
| ABC: Node 23032 has dup fanin 23002. |
| ABC: Node 23032 has dup fanin 23002. |
| ABC: Node 23033 has dup fanin 23002. |
| ABC: Node 23033 has dup fanin 23002. |
| ABC: Node 23034 has dup fanin 23002. |
| ABC: Node 23034 has dup fanin 23002. |
| ABC: Node 23072 has dup fanin 9599. |
| ABC: Node 23072 has dup fanin 23071. |
| ABC: Node 23072 has dup fanin 9599. |
| ABC: Node 23072 has dup fanin 23071. |
| ABC: Node 23075 has dup fanin 13646. |
| ABC: Node 23075 has dup fanin 13646. |
| ABC: Node 23077 has dup fanin 13627. |
| ABC: Node 23077 has dup fanin 23076. |
| ABC: Node 23077 has dup fanin 13627. |
| ABC: Node 23077 has dup fanin 23076. |
| ABC: Node 23083 has dup fanin 13645. |
| ABC: Node 23083 has dup fanin 13645. |
| ABC: Node 23085 has dup fanin 13626. |
| ABC: Node 23085 has dup fanin 23084. |
| ABC: Node 23085 has dup fanin 13626. |
| ABC: Node 23085 has dup fanin 23084. |
| ABC: Node 23091 has dup fanin 13645. |
| ABC: Node 23091 has dup fanin 13645. |
| ABC: Node 23093 has dup fanin 13625. |
| ABC: Node 23093 has dup fanin 23092. |
| ABC: Node 23093 has dup fanin 13625. |
| ABC: Node 23093 has dup fanin 23092. |
| ABC: Node 23099 has dup fanin 13645. |
| ABC: Node 23099 has dup fanin 13645. |
| ABC: Node 23101 has dup fanin 9603. |
| ABC: Node 23101 has dup fanin 23100. |
| ABC: Node 23101 has dup fanin 9603. |
| ABC: Node 23101 has dup fanin 23100. |
| ABC: Node 23104 has dup fanin 13646. |
| ABC: Node 23104 has dup fanin 13646. |
| ABC: Node 23106 has dup fanin 9604. |
| ABC: Node 23106 has dup fanin 23105. |
| ABC: Node 23106 has dup fanin 9604. |
| ABC: Node 23106 has dup fanin 23105. |
| ABC: Node 23109 has dup fanin 13646. |
| ABC: Node 23109 has dup fanin 13646. |
| ABC: Node 23111 has dup fanin 9605. |
| ABC: Node 23111 has dup fanin 23110. |
| ABC: Node 23111 has dup fanin 9605. |
| ABC: Node 23111 has dup fanin 23110. |
| ABC: Node 23114 has dup fanin 13646. |
| ABC: Node 23114 has dup fanin 13646. |
| ABC: Node 23116 has dup fanin 13618. |
| ABC: Node 23116 has dup fanin 23115. |
| ABC: Node 23116 has dup fanin 13618. |
| ABC: Node 23116 has dup fanin 23115. |
| ABC: Node 23122 has dup fanin 13645. |
| ABC: Node 23122 has dup fanin 13645. |
| ABC: Node 23124 has dup fanin 9607. |
| ABC: Node 23124 has dup fanin 23123. |
| ABC: Node 23124 has dup fanin 9607. |
| ABC: Node 23124 has dup fanin 23123. |
| ABC: Node 23127 has dup fanin 13646. |
| ABC: Node 23127 has dup fanin 13646. |
| ABC: Node 23129 has dup fanin 9608. |
| ABC: Node 23129 has dup fanin 23128. |
| ABC: Node 23129 has dup fanin 9608. |
| ABC: Node 23129 has dup fanin 23128. |
| ABC: Node 23132 has dup fanin 13646. |
| ABC: Node 23132 has dup fanin 13646. |
| ABC: Node 23134 has dup fanin 9609. |
| ABC: Node 23134 has dup fanin 23133. |
| ABC: Node 23134 has dup fanin 9609. |
| ABC: Node 23134 has dup fanin 23133. |
| ABC: Node 23137 has dup fanin 13646. |
| ABC: Node 23137 has dup fanin 13646. |
| ABC: Node 23139 has dup fanin 13611. |
| ABC: Node 23139 has dup fanin 23138. |
| ABC: Node 23139 has dup fanin 13611. |
| ABC: Node 23139 has dup fanin 23138. |
| ABC: Node 23145 has dup fanin 13645. |
| ABC: Node 23145 has dup fanin 13645. |
| ABC: Node 23147 has dup fanin 9611. |
| ABC: Node 23147 has dup fanin 23146. |
| ABC: Node 23147 has dup fanin 9611. |
| ABC: Node 23147 has dup fanin 23146. |
| ABC: Node 23150 has dup fanin 13646. |
| ABC: Node 23150 has dup fanin 13646. |
| ABC: Node 23152 has dup fanin 9612. |
| ABC: Node 23152 has dup fanin 23151. |
| ABC: Node 23152 has dup fanin 9612. |
| ABC: Node 23152 has dup fanin 23151. |
| ABC: Node 23155 has dup fanin 13646. |
| ABC: Node 23155 has dup fanin 13646. |
| ABC: Node 23157 has dup fanin 9613. |
| ABC: Node 23157 has dup fanin 23156. |
| ABC: Node 23157 has dup fanin 9613. |
| ABC: Node 23157 has dup fanin 23156. |
| ABC: Node 23160 has dup fanin 13646. |
| ABC: Node 23160 has dup fanin 13646. |
| ABC: Node 23162 has dup fanin 13604. |
| ABC: Node 23162 has dup fanin 23161. |
| ABC: Node 23162 has dup fanin 13604. |
| ABC: Node 23162 has dup fanin 23161. |
| ABC: Node 23168 has dup fanin 13645. |
| ABC: Node 23168 has dup fanin 13645. |
| ABC: Node 23170 has dup fanin 13603. |
| ABC: Node 23170 has dup fanin 23169. |
| ABC: Node 23170 has dup fanin 13603. |
| ABC: Node 23170 has dup fanin 23169. |
| ABC: Node 23176 has dup fanin 13645. |
| ABC: Node 23176 has dup fanin 13645. |
| ABC: Node 23178 has dup fanin 13602. |
| ABC: Node 23178 has dup fanin 23177. |
| ABC: Node 23178 has dup fanin 13602. |
| ABC: Node 23178 has dup fanin 23177. |
| ABC: Node 23184 has dup fanin 13645. |
| ABC: Node 23184 has dup fanin 13645. |
| ABC: Node 23186 has dup fanin 13601. |
| ABC: Node 23186 has dup fanin 23185. |
| ABC: Node 23186 has dup fanin 13601. |
| ABC: Node 23186 has dup fanin 23185. |
| ABC: Node 23192 has dup fanin 13645. |
| ABC: Node 23192 has dup fanin 13645. |
| ABC: Node 23194 has dup fanin 13600. |
| ABC: Node 23194 has dup fanin 23193. |
| ABC: Node 23194 has dup fanin 13600. |
| ABC: Node 23194 has dup fanin 23193. |
| ABC: Node 23200 has dup fanin 13645. |
| ABC: Node 23200 has dup fanin 13645. |
| ABC: Node 23202 has dup fanin 13599. |
| ABC: Node 23202 has dup fanin 23201. |
| ABC: Node 23202 has dup fanin 13599. |
| ABC: Node 23202 has dup fanin 23201. |
| ABC: Node 23208 has dup fanin 13645. |
| ABC: Node 23208 has dup fanin 13645. |
| ABC: Node 23210 has dup fanin 13598. |
| ABC: Node 23210 has dup fanin 23209. |
| ABC: Node 23210 has dup fanin 13598. |
| ABC: Node 23210 has dup fanin 23209. |
| ABC: Node 23216 has dup fanin 13645. |
| ABC: Node 23216 has dup fanin 13645. |
| ABC: Node 23218 has dup fanin 13597. |
| ABC: Node 23218 has dup fanin 23217. |
| ABC: Node 23218 has dup fanin 13597. |
| ABC: Node 23218 has dup fanin 23217. |
| ABC: Node 23224 has dup fanin 13645. |
| ABC: Node 23224 has dup fanin 13645. |
| ABC: Node 23226 has dup fanin 13596. |
| ABC: Node 23226 has dup fanin 23225. |
| ABC: Node 23226 has dup fanin 13596. |
| ABC: Node 23226 has dup fanin 23225. |
| ABC: Node 23232 has dup fanin 13645. |
| ABC: Node 23232 has dup fanin 13645. |
| ABC: Node 23234 has dup fanin 13595. |
| ABC: Node 23234 has dup fanin 23233. |
| ABC: Node 23234 has dup fanin 13595. |
| ABC: Node 23234 has dup fanin 23233. |
| ABC: Node 23240 has dup fanin 13645. |
| ABC: Node 23240 has dup fanin 13645. |
| ABC: Node 23242 has dup fanin 9624. |
| ABC: Node 23242 has dup fanin 23241. |
| ABC: Node 23242 has dup fanin 9624. |
| ABC: Node 23242 has dup fanin 23241. |
| ABC: Node 23245 has dup fanin 13646. |
| ABC: Node 23245 has dup fanin 13646. |
| ABC: Node 23247 has dup fanin 9625. |
| ABC: Node 23247 has dup fanin 23246. |
| ABC: Node 23247 has dup fanin 9625. |
| ABC: Node 23247 has dup fanin 23246. |
| ABC: Node 23250 has dup fanin 13646. |
| ABC: Node 23250 has dup fanin 13646. |
| ABC: Node 23252 has dup fanin 13590. |
| ABC: Node 23252 has dup fanin 23251. |
| ABC: Node 23252 has dup fanin 13590. |
| ABC: Node 23252 has dup fanin 23251. |
| ABC: Node 23258 has dup fanin 13645. |
| ABC: Node 23258 has dup fanin 13645. |
| ABC: Node 23260 has dup fanin 13589. |
| ABC: Node 23260 has dup fanin 23259. |
| ABC: Node 23260 has dup fanin 13589. |
| ABC: Node 23260 has dup fanin 23259. |
| ABC: Node 23266 has dup fanin 13645. |
| ABC: Node 23266 has dup fanin 13645. |
| ABC: Node 23271 has dup fanin 13646. |
| ABC: Node 23271 has dup fanin 13646. |
| ABC: Node 23274 has dup fanin 13645. |
| ABC: Node 23274 has dup fanin 13645. |
| ABC: Node 23277 has dup fanin 23276. |
| ABC: Node 23277 has dup fanin 23276. |
| ABC: Node 23278 has dup fanin 23276. |
| ABC: Node 23278 has dup fanin 23276. |
| ABC: Node 23279 has dup fanin 23276. |
| ABC: Node 23279 has dup fanin 23276. |
| ABC: Node 23280 has dup fanin 23276. |
| ABC: Node 23280 has dup fanin 23276. |
| ABC: Node 23281 has dup fanin 23276. |
| ABC: Node 23281 has dup fanin 23276. |
| ABC: Node 23282 has dup fanin 23276. |
| ABC: Node 23282 has dup fanin 23276. |
| ABC: Node 23283 has dup fanin 23276. |
| ABC: Node 23283 has dup fanin 23276. |
| ABC: Node 23284 has dup fanin 23276. |
| ABC: Node 23284 has dup fanin 23276. |
| ABC: Node 23285 has dup fanin 23276. |
| ABC: Node 23285 has dup fanin 23276. |
| ABC: Node 23286 has dup fanin 23276. |
| ABC: Node 23286 has dup fanin 23276. |
| ABC: Node 23287 has dup fanin 23276. |
| ABC: Node 23287 has dup fanin 23276. |
| ABC: Node 23288 has dup fanin 23276. |
| ABC: Node 23288 has dup fanin 23276. |
| ABC: Node 23289 has dup fanin 23276. |
| ABC: Node 23289 has dup fanin 23276. |
| ABC: Node 23290 has dup fanin 23276. |
| ABC: Node 23290 has dup fanin 23276. |
| ABC: Node 23291 has dup fanin 23276. |
| ABC: Node 23291 has dup fanin 23276. |
| ABC: Node 23292 has dup fanin 23276. |
| ABC: Node 23292 has dup fanin 23276. |
| ABC: Node 23293 has dup fanin 23276. |
| ABC: Node 23293 has dup fanin 23276. |
| ABC: Node 23294 has dup fanin 23276. |
| ABC: Node 23294 has dup fanin 23276. |
| ABC: Node 23295 has dup fanin 23276. |
| ABC: Node 23295 has dup fanin 23276. |
| ABC: Node 23296 has dup fanin 23276. |
| ABC: Node 23296 has dup fanin 23276. |
| ABC: Node 23297 has dup fanin 23276. |
| ABC: Node 23297 has dup fanin 23276. |
| ABC: Node 23298 has dup fanin 23276. |
| ABC: Node 23298 has dup fanin 23276. |
| ABC: Node 23299 has dup fanin 23276. |
| ABC: Node 23299 has dup fanin 23276. |
| ABC: Node 23300 has dup fanin 23276. |
| ABC: Node 23300 has dup fanin 23276. |
| ABC: Node 23301 has dup fanin 23276. |
| ABC: Node 23301 has dup fanin 23276. |
| ABC: Node 23302 has dup fanin 23276. |
| ABC: Node 23302 has dup fanin 23276. |
| ABC: Node 23303 has dup fanin 23276. |
| ABC: Node 23303 has dup fanin 23276. |
| ABC: Node 23304 has dup fanin 23276. |
| ABC: Node 23304 has dup fanin 23276. |
| ABC: Node 23305 has dup fanin 23276. |
| ABC: Node 23305 has dup fanin 23276. |
| ABC: Node 23306 has dup fanin 23276. |
| ABC: Node 23306 has dup fanin 23276. |
| ABC: Node 23307 has dup fanin 23276. |
| ABC: Node 23307 has dup fanin 23276. |
| ABC: Node 23308 has dup fanin 23276. |
| ABC: Node 23308 has dup fanin 23276. |
| ABC: Node 23311 has dup fanin 23310. |
| ABC: Node 23311 has dup fanin 23310. |
| ABC: Node 23312 has dup fanin 23310. |
| ABC: Node 23312 has dup fanin 23310. |
| ABC: Node 23313 has dup fanin 23310. |
| ABC: Node 23313 has dup fanin 23310. |
| ABC: Node 23314 has dup fanin 23310. |
| ABC: Node 23314 has dup fanin 23310. |
| ABC: Node 23315 has dup fanin 23310. |
| ABC: Node 23315 has dup fanin 23310. |
| ABC: Node 23316 has dup fanin 23310. |
| ABC: Node 23316 has dup fanin 23310. |
| ABC: Node 23317 has dup fanin 23310. |
| ABC: Node 23317 has dup fanin 23310. |
| ABC: Node 23318 has dup fanin 23310. |
| ABC: Node 23318 has dup fanin 23310. |
| ABC: Node 23319 has dup fanin 23310. |
| ABC: Node 23319 has dup fanin 23310. |
| ABC: Node 23320 has dup fanin 23310. |
| ABC: Node 23320 has dup fanin 23310. |
| ABC: Node 23321 has dup fanin 23310. |
| ABC: Node 23321 has dup fanin 23310. |
| ABC: Node 23322 has dup fanin 23310. |
| ABC: Node 23322 has dup fanin 23310. |
| ABC: Node 23323 has dup fanin 23310. |
| ABC: Node 23323 has dup fanin 23310. |
| ABC: Node 23324 has dup fanin 23310. |
| ABC: Node 23324 has dup fanin 23310. |
| ABC: Node 23325 has dup fanin 23310. |
| ABC: Node 23325 has dup fanin 23310. |
| ABC: Node 23326 has dup fanin 23310. |
| ABC: Node 23326 has dup fanin 23310. |
| ABC: Node 23327 has dup fanin 23310. |
| ABC: Node 23327 has dup fanin 23310. |
| ABC: Node 23328 has dup fanin 23310. |
| ABC: Node 23328 has dup fanin 23310. |
| ABC: Node 23329 has dup fanin 23310. |
| ABC: Node 23329 has dup fanin 23310. |
| ABC: Node 23330 has dup fanin 23310. |
| ABC: Node 23330 has dup fanin 23310. |
| ABC: Node 23331 has dup fanin 23310. |
| ABC: Node 23331 has dup fanin 23310. |
| ABC: Node 23332 has dup fanin 23310. |
| ABC: Node 23332 has dup fanin 23310. |
| ABC: Node 23333 has dup fanin 23310. |
| ABC: Node 23333 has dup fanin 23310. |
| ABC: Node 23334 has dup fanin 23310. |
| ABC: Node 23334 has dup fanin 23310. |
| ABC: Node 23335 has dup fanin 23310. |
| ABC: Node 23335 has dup fanin 23310. |
| ABC: Node 23336 has dup fanin 23310. |
| ABC: Node 23336 has dup fanin 23310. |
| ABC: Node 23337 has dup fanin 23310. |
| ABC: Node 23337 has dup fanin 23310. |
| ABC: Node 23338 has dup fanin 23310. |
| ABC: Node 23338 has dup fanin 23310. |
| ABC: Node 23339 has dup fanin 23310. |
| ABC: Node 23339 has dup fanin 23310. |
| ABC: Node 23340 has dup fanin 23310. |
| ABC: Node 23340 has dup fanin 23310. |
| ABC: Node 23341 has dup fanin 23310. |
| ABC: Node 23341 has dup fanin 23310. |
| ABC: Node 23342 has dup fanin 23310. |
| ABC: Node 23342 has dup fanin 23310. |
| ABC: Node 23343 has dup fanin 12788. |
| ABC: Node 23343 has dup fanin 12788. |
| ABC: Node 23344 has dup fanin 12788. |
| ABC: Node 23344 has dup fanin 12788. |
| ABC: Node 23345 has dup fanin 12788. |
| ABC: Node 23345 has dup fanin 12788. |
| ABC: Node 23346 has dup fanin 12788. |
| ABC: Node 23346 has dup fanin 12788. |
| ABC: Node 23347 has dup fanin 12788. |
| ABC: Node 23347 has dup fanin 12788. |
| ABC: Node 23348 has dup fanin 12788. |
| ABC: Node 23348 has dup fanin 12788. |
| ABC: Node 23349 has dup fanin 12788. |
| ABC: Node 23349 has dup fanin 12788. |
| ABC: Node 23350 has dup fanin 12788. |
| ABC: Node 23350 has dup fanin 12788. |
| ABC: Node 23351 has dup fanin 12788. |
| ABC: Node 23351 has dup fanin 12788. |
| ABC: Node 23352 has dup fanin 12788. |
| ABC: Node 23352 has dup fanin 12788. |
| ABC: Node 23353 has dup fanin 12788. |
| ABC: Node 23353 has dup fanin 12788. |
| ABC: Node 23354 has dup fanin 12788. |
| ABC: Node 23354 has dup fanin 12788. |
| ABC: Node 23355 has dup fanin 12788. |
| ABC: Node 23355 has dup fanin 12788. |
| ABC: Node 23356 has dup fanin 12788. |
| ABC: Node 23356 has dup fanin 12788. |
| ABC: Node 23357 has dup fanin 12788. |
| ABC: Node 23357 has dup fanin 12788. |
| ABC: Node 23358 has dup fanin 12788. |
| ABC: Node 23358 has dup fanin 12788. |
| ABC: Node 23359 has dup fanin 12788. |
| ABC: Node 23359 has dup fanin 12788. |
| ABC: Node 23396 has dup fanin 12738. |
| ABC: Node 23396 has dup fanin 12738. |
| ABC: Node 23587 has dup fanin 12858. |
| ABC: Node 23587 has dup fanin 12858. |
| ABC: Node 23596 has dup fanin 12858. |
| ABC: Node 23596 has dup fanin 12858. |
| ABC: Node 23615 has dup fanin 12858. |
| ABC: Node 23615 has dup fanin 12858. |
| ABC: Node 23627 has dup fanin 12858. |
| ABC: Node 23627 has dup fanin 12858. |
| ABC: Node 23643 has dup fanin 12858. |
| ABC: Node 23643 has dup fanin 12858. |
| ABC: Node 23668 has dup fanin 12858. |
| ABC: Node 23668 has dup fanin 12858. |
| ABC: Node 23700 has dup fanin 12859. |
| ABC: Node 23700 has dup fanin 12859. |
| ABC: Node 23728 has dup fanin 12859. |
| ABC: Node 23728 has dup fanin 12859. |
| ABC: Node 23753 has dup fanin 12858. |
| ABC: Node 23753 has dup fanin 12858. |
| ABC: Node 23774 has dup fanin 12738. |
| ABC: Node 23774 has dup fanin 12738. |
| ABC: Node 23775 has dup fanin 12738. |
| ABC: Node 23775 has dup fanin 12738. |
| ABC: Node 23776 has dup fanin 12738. |
| ABC: Node 23776 has dup fanin 12738. |
| ABC: Node 23777 has dup fanin 12738. |
| ABC: Node 23777 has dup fanin 12738. |
| ABC: Node 23778 has dup fanin 12738. |
| ABC: Node 23778 has dup fanin 12738. |
| ABC: Node 23779 has dup fanin 12738. |
| ABC: Node 23779 has dup fanin 12738. |
| ABC: Node 23780 has dup fanin 12738. |
| ABC: Node 23780 has dup fanin 12738. |
| ABC: Node 23782 has dup fanin 23781. |
| ABC: Node 23782 has dup fanin 23781. |
| ABC: Node 23783 has dup fanin 23781. |
| ABC: Node 23783 has dup fanin 23781. |
| ABC: Node 23784 has dup fanin 23781. |
| ABC: Node 23784 has dup fanin 23781. |
| ABC: Node 23785 has dup fanin 23781. |
| ABC: Node 23785 has dup fanin 23781. |
| ABC: Node 23786 has dup fanin 23781. |
| ABC: Node 23786 has dup fanin 23781. |
| ABC: Node 23787 has dup fanin 23781. |
| ABC: Node 23787 has dup fanin 23781. |
| ABC: Node 23788 has dup fanin 23781. |
| ABC: Node 23788 has dup fanin 23781. |
| ABC: Node 23789 has dup fanin 23781. |
| ABC: Node 23789 has dup fanin 23781. |
| ABC: Node 23790 has dup fanin 23781. |
| ABC: Node 23790 has dup fanin 23781. |
| ABC: Node 23791 has dup fanin 23781. |
| ABC: Node 23791 has dup fanin 23781. |
| ABC: Node 23792 has dup fanin 23781. |
| ABC: Node 23792 has dup fanin 23781. |
| ABC: Node 23793 has dup fanin 23781. |
| ABC: Node 23793 has dup fanin 23781. |
| ABC: Node 23794 has dup fanin 23781. |
| ABC: Node 23794 has dup fanin 23781. |
| ABC: Node 23795 has dup fanin 23781. |
| ABC: Node 23795 has dup fanin 23781. |
| ABC: Node 23796 has dup fanin 23781. |
| ABC: Node 23796 has dup fanin 23781. |
| ABC: Node 23797 has dup fanin 23781. |
| ABC: Node 23797 has dup fanin 23781. |
| ABC: Node 23798 has dup fanin 23781. |
| ABC: Node 23798 has dup fanin 23781. |
| ABC: Node 23799 has dup fanin 23781. |
| ABC: Node 23799 has dup fanin 23781. |
| ABC: Node 23800 has dup fanin 23781. |
| ABC: Node 23800 has dup fanin 23781. |
| ABC: Node 23801 has dup fanin 23781. |
| ABC: Node 23801 has dup fanin 23781. |
| ABC: Node 23802 has dup fanin 23781. |
| ABC: Node 23802 has dup fanin 23781. |
| ABC: Node 23803 has dup fanin 23781. |
| ABC: Node 23803 has dup fanin 23781. |
| ABC: Node 23804 has dup fanin 23781. |
| ABC: Node 23804 has dup fanin 23781. |
| ABC: Node 23805 has dup fanin 23781. |
| ABC: Node 23805 has dup fanin 23781. |
| ABC: Node 23806 has dup fanin 23781. |
| ABC: Node 23806 has dup fanin 23781. |
| ABC: Node 23807 has dup fanin 23781. |
| ABC: Node 23807 has dup fanin 23781. |
| ABC: Node 23808 has dup fanin 23781. |
| ABC: Node 23808 has dup fanin 23781. |
| ABC: Node 23809 has dup fanin 23781. |
| ABC: Node 23809 has dup fanin 23781. |
| ABC: Node 23810 has dup fanin 23781. |
| ABC: Node 23810 has dup fanin 23781. |
| ABC: Node 23811 has dup fanin 23781. |
| ABC: Node 23811 has dup fanin 23781. |
| ABC: Node 23812 has dup fanin 23781. |
| ABC: Node 23812 has dup fanin 23781. |
| ABC: Node 23813 has dup fanin 23781. |
| ABC: Node 23813 has dup fanin 23781. |
| ABC: Node 23815 has dup fanin 23814. |
| ABC: Node 23815 has dup fanin 23814. |
| ABC: Node 23816 has dup fanin 23814. |
| ABC: Node 23816 has dup fanin 23814. |
| ABC: Node 23817 has dup fanin 23814. |
| ABC: Node 23817 has dup fanin 23814. |
| ABC: Node 23818 has dup fanin 23814. |
| ABC: Node 23818 has dup fanin 23814. |
| ABC: Node 23819 has dup fanin 23814. |
| ABC: Node 23819 has dup fanin 23814. |
| ABC: Node 23820 has dup fanin 23814. |
| ABC: Node 23820 has dup fanin 23814. |
| ABC: Node 23821 has dup fanin 23814. |
| ABC: Node 23821 has dup fanin 23814. |
| ABC: Node 23822 has dup fanin 23814. |
| ABC: Node 23822 has dup fanin 23814. |
| ABC: Node 23823 has dup fanin 23814. |
| ABC: Node 23823 has dup fanin 23814. |
| ABC: Node 23824 has dup fanin 23814. |
| ABC: Node 23824 has dup fanin 23814. |
| ABC: Node 23825 has dup fanin 23814. |
| ABC: Node 23825 has dup fanin 23814. |
| ABC: Node 23826 has dup fanin 23814. |
| ABC: Node 23826 has dup fanin 23814. |
| ABC: Node 23827 has dup fanin 23814. |
| ABC: Node 23827 has dup fanin 23814. |
| ABC: Node 23828 has dup fanin 23814. |
| ABC: Node 23828 has dup fanin 23814. |
| ABC: Node 23829 has dup fanin 23814. |
| ABC: Node 23829 has dup fanin 23814. |
| ABC: Node 23830 has dup fanin 23814. |
| ABC: Node 23830 has dup fanin 23814. |
| ABC: Node 23831 has dup fanin 23814. |
| ABC: Node 23831 has dup fanin 23814. |
| ABC: Node 23832 has dup fanin 23814. |
| ABC: Node 23832 has dup fanin 23814. |
| ABC: Node 23833 has dup fanin 23814. |
| ABC: Node 23833 has dup fanin 23814. |
| ABC: Node 23834 has dup fanin 23814. |
| ABC: Node 23834 has dup fanin 23814. |
| ABC: Node 23835 has dup fanin 23814. |
| ABC: Node 23835 has dup fanin 23814. |
| ABC: Node 23836 has dup fanin 23814. |
| ABC: Node 23836 has dup fanin 23814. |
| ABC: Node 23837 has dup fanin 23814. |
| ABC: Node 23837 has dup fanin 23814. |
| ABC: Node 23838 has dup fanin 23814. |
| ABC: Node 23838 has dup fanin 23814. |
| ABC: Node 23839 has dup fanin 23814. |
| ABC: Node 23839 has dup fanin 23814. |
| ABC: Node 23840 has dup fanin 23814. |
| ABC: Node 23840 has dup fanin 23814. |
| ABC: Node 23841 has dup fanin 23814. |
| ABC: Node 23841 has dup fanin 23814. |
| ABC: Node 23842 has dup fanin 23814. |
| ABC: Node 23842 has dup fanin 23814. |
| ABC: Node 23843 has dup fanin 23814. |
| ABC: Node 23843 has dup fanin 23814. |
| ABC: Node 23844 has dup fanin 23814. |
| ABC: Node 23844 has dup fanin 23814. |
| ABC: Node 23845 has dup fanin 23814. |
| ABC: Node 23845 has dup fanin 23814. |
| ABC: Node 23846 has dup fanin 23814. |
| ABC: Node 23846 has dup fanin 23814. |
| ABC: Node 23849 has dup fanin 23848. |
| ABC: Node 23849 has dup fanin 23848. |
| ABC: Node 23850 has dup fanin 23848. |
| ABC: Node 23850 has dup fanin 23848. |
| ABC: Node 23851 has dup fanin 23848. |
| ABC: Node 23851 has dup fanin 23848. |
| ABC: Node 23852 has dup fanin 23848. |
| ABC: Node 23852 has dup fanin 23848. |
| ABC: Node 23853 has dup fanin 23848. |
| ABC: Node 23853 has dup fanin 23848. |
| ABC: Node 23854 has dup fanin 23848. |
| ABC: Node 23854 has dup fanin 23848. |
| ABC: Node 23855 has dup fanin 23848. |
| ABC: Node 23855 has dup fanin 23848. |
| ABC: Node 23856 has dup fanin 23848. |
| ABC: Node 23856 has dup fanin 23848. |
| ABC: Node 23857 has dup fanin 23848. |
| ABC: Node 23857 has dup fanin 23848. |
| ABC: Node 23858 has dup fanin 23848. |
| ABC: Node 23858 has dup fanin 23848. |
| ABC: Node 23859 has dup fanin 23848. |
| ABC: Node 23859 has dup fanin 23848. |
| ABC: Node 23860 has dup fanin 23848. |
| ABC: Node 23860 has dup fanin 23848. |
| ABC: Node 23861 has dup fanin 23848. |
| ABC: Node 23861 has dup fanin 23848. |
| ABC: Node 23862 has dup fanin 23848. |
| ABC: Node 23862 has dup fanin 23848. |
| ABC: Node 23863 has dup fanin 23848. |
| ABC: Node 23863 has dup fanin 23848. |
| ABC: Node 23864 has dup fanin 23848. |
| ABC: Node 23864 has dup fanin 23848. |
| ABC: Node 23865 has dup fanin 23848. |
| ABC: Node 23865 has dup fanin 23848. |
| ABC: Node 23866 has dup fanin 23848. |
| ABC: Node 23866 has dup fanin 23848. |
| ABC: Node 23867 has dup fanin 23848. |
| ABC: Node 23867 has dup fanin 23848. |
| ABC: Node 23868 has dup fanin 23848. |
| ABC: Node 23868 has dup fanin 23848. |
| ABC: Node 23869 has dup fanin 23848. |
| ABC: Node 23869 has dup fanin 23848. |
| ABC: Node 23870 has dup fanin 23848. |
| ABC: Node 23870 has dup fanin 23848. |
| ABC: Node 23871 has dup fanin 23848. |
| ABC: Node 23871 has dup fanin 23848. |
| ABC: Node 23872 has dup fanin 23848. |
| ABC: Node 23872 has dup fanin 23848. |
| ABC: Node 23873 has dup fanin 23848. |
| ABC: Node 23873 has dup fanin 23848. |
| ABC: Node 23874 has dup fanin 23848. |
| ABC: Node 23874 has dup fanin 23848. |
| ABC: Node 23875 has dup fanin 23848. |
| ABC: Node 23875 has dup fanin 23848. |
| ABC: Node 23876 has dup fanin 23848. |
| ABC: Node 23876 has dup fanin 23848. |
| ABC: Node 23877 has dup fanin 23848. |
| ABC: Node 23877 has dup fanin 23848. |
| ABC: Node 23878 has dup fanin 23848. |
| ABC: Node 23878 has dup fanin 23848. |
| ABC: Node 23879 has dup fanin 23848. |
| ABC: Node 23879 has dup fanin 23848. |
| ABC: Node 23880 has dup fanin 23848. |
| ABC: Node 23880 has dup fanin 23848. |
| ABC: Node 23885 has dup fanin 17008. |
| ABC: Node 23885 has dup fanin 17008. |
| ABC: Node 23958 has dup fanin 23760. |
| ABC: Node 23958 has dup fanin 23760. |
| ABC: Node 23959 has dup fanin 23760. |
| ABC: Node 23959 has dup fanin 23760. |
| ABC: Node 23960 has dup fanin 23760. |
| ABC: Node 23960 has dup fanin 23760. |
| ABC: Node 23961 has dup fanin 23760. |
| ABC: Node 23961 has dup fanin 23760. |
| ABC: Node 23962 has dup fanin 23760. |
| ABC: Node 23962 has dup fanin 23760. |
| ABC: Node 23963 has dup fanin 23760. |
| ABC: Node 23963 has dup fanin 23760. |
| ABC: Node 23964 has dup fanin 23760. |
| ABC: Node 23964 has dup fanin 23760. |
| ABC: Node 23965 has dup fanin 23760. |
| ABC: Node 23965 has dup fanin 23760. |
| ABC: Node 23968 has dup fanin 12726. |
| ABC: Node 23968 has dup fanin 12726. |
| ABC: Node 23970 has dup fanin 12726. |
| ABC: Node 23970 has dup fanin 12726. |
| ABC: Node 23972 has dup fanin 12726. |
| ABC: Node 23972 has dup fanin 12726. |
| ABC: Node 23974 has dup fanin 12726. |
| ABC: Node 23974 has dup fanin 12726. |
| ABC: Node 23976 has dup fanin 12726. |
| ABC: Node 23976 has dup fanin 12726. |
| ABC: Node 23978 has dup fanin 12726. |
| ABC: Node 23978 has dup fanin 12726. |
| ABC: Node 23980 has dup fanin 12726. |
| ABC: Node 23980 has dup fanin 12726. |
| ABC: Node 23982 has dup fanin 12726. |
| ABC: Node 23982 has dup fanin 12726. |
| ABC: Node 23984 has dup fanin 12726. |
| ABC: Node 23984 has dup fanin 12726. |
| ABC: Node 23986 has dup fanin 12726. |
| ABC: Node 23986 has dup fanin 12726. |
| ABC: Node 23988 has dup fanin 12726. |
| ABC: Node 23988 has dup fanin 12726. |
| ABC: Node 23990 has dup fanin 12726. |
| ABC: Node 23990 has dup fanin 12726. |
| ABC: Node 23992 has dup fanin 12726. |
| ABC: Node 23992 has dup fanin 12726. |
| ABC: Node 23994 has dup fanin 12726. |
| ABC: Node 23994 has dup fanin 12726. |
| ABC: Node 23996 has dup fanin 12726. |
| ABC: Node 23996 has dup fanin 12726. |
| ABC: Node 23998 has dup fanin 12726. |
| ABC: Node 23998 has dup fanin 12726. |
| ABC: Node 24000 has dup fanin 12726. |
| ABC: Node 24000 has dup fanin 12726. |
| ABC: Node 24002 has dup fanin 12726. |
| ABC: Node 24002 has dup fanin 12726. |
| ABC: Node 24004 has dup fanin 12726. |
| ABC: Node 24004 has dup fanin 12726. |
| ABC: Node 24006 has dup fanin 12726. |
| ABC: Node 24006 has dup fanin 12726. |
| ABC: Node 24008 has dup fanin 12726. |
| ABC: Node 24008 has dup fanin 12726. |
| ABC: Node 24010 has dup fanin 12726. |
| ABC: Node 24010 has dup fanin 12726. |
| ABC: Node 24012 has dup fanin 12726. |
| ABC: Node 24012 has dup fanin 12726. |
| ABC: Node 24014 has dup fanin 12726. |
| ABC: Node 24014 has dup fanin 12726. |
| ABC: Node 24016 has dup fanin 12726. |
| ABC: Node 24016 has dup fanin 12726. |
| ABC: Node 24018 has dup fanin 12726. |
| ABC: Node 24018 has dup fanin 12726. |
| ABC: Node 24020 has dup fanin 12726. |
| ABC: Node 24020 has dup fanin 12726. |
| ABC: Node 24022 has dup fanin 12726. |
| ABC: Node 24022 has dup fanin 12726. |
| ABC: Node 24024 has dup fanin 12726. |
| ABC: Node 24024 has dup fanin 12726. |
| ABC: Node 24027 has dup fanin 24025. |
| ABC: Node 24027 has dup fanin 24026. |
| ABC: Node 24027 has dup fanin 24025. |
| ABC: Node 24027 has dup fanin 24026. |
| ABC: Node 24029 has dup fanin 23967. |
| ABC: Node 24029 has dup fanin 23967. |
| ABC: Node 24032 has dup fanin 23966. |
| ABC: Node 24032 has dup fanin 23966. |
| ABC: Node 24152 has dup fanin 24151. |
| ABC: Node 24152 has dup fanin 24151. |
| ABC: Node 24153 has dup fanin 24151. |
| ABC: Node 24153 has dup fanin 24151. |
| ABC: Node 24154 has dup fanin 24151. |
| ABC: Node 24154 has dup fanin 24151. |
| ABC: Node 24155 has dup fanin 24151. |
| ABC: Node 24155 has dup fanin 24151. |
| ABC: Node 24156 has dup fanin 24151. |
| ABC: Node 24156 has dup fanin 24151. |
| ABC: Node 24157 has dup fanin 24151. |
| ABC: Node 24157 has dup fanin 24151. |
| ABC: Node 24158 has dup fanin 24151. |
| ABC: Node 24158 has dup fanin 24151. |
| ABC: Node 24159 has dup fanin 24151. |
| ABC: Node 24159 has dup fanin 24151. |
| ABC: Node 24160 has dup fanin 24151. |
| ABC: Node 24160 has dup fanin 24151. |
| ABC: Node 24161 has dup fanin 24151. |
| ABC: Node 24161 has dup fanin 24151. |
| ABC: Node 24162 has dup fanin 24151. |
| ABC: Node 24162 has dup fanin 24151. |
| ABC: Node 24163 has dup fanin 24151. |
| ABC: Node 24163 has dup fanin 24151. |
| ABC: Node 24164 has dup fanin 24151. |
| ABC: Node 24164 has dup fanin 24151. |
| ABC: Node 24165 has dup fanin 24151. |
| ABC: Node 24165 has dup fanin 24151. |
| ABC: Node 24166 has dup fanin 24151. |
| ABC: Node 24166 has dup fanin 24151. |
| ABC: Node 24167 has dup fanin 24151. |
| ABC: Node 24167 has dup fanin 24151. |
| ABC: Node 24168 has dup fanin 24151. |
| ABC: Node 24168 has dup fanin 24151. |
| ABC: Node 24169 has dup fanin 24151. |
| ABC: Node 24169 has dup fanin 24151. |
| ABC: Node 24170 has dup fanin 24151. |
| ABC: Node 24170 has dup fanin 24151. |
| ABC: Node 24171 has dup fanin 24151. |
| ABC: Node 24171 has dup fanin 24151. |
| ABC: Node 24172 has dup fanin 24151. |
| ABC: Node 24172 has dup fanin 24151. |
| ABC: Node 24173 has dup fanin 24151. |
| ABC: Node 24173 has dup fanin 24151. |
| ABC: Node 24174 has dup fanin 24151. |
| ABC: Node 24174 has dup fanin 24151. |
| ABC: Node 24175 has dup fanin 24151. |
| ABC: Node 24175 has dup fanin 24151. |
| ABC: Node 24176 has dup fanin 24151. |
| ABC: Node 24176 has dup fanin 24151. |
| ABC: Node 24177 has dup fanin 24151. |
| ABC: Node 24177 has dup fanin 24151. |
| ABC: Node 24178 has dup fanin 24151. |
| ABC: Node 24178 has dup fanin 24151. |
| ABC: Node 24179 has dup fanin 24151. |
| ABC: Node 24179 has dup fanin 24151. |
| ABC: Node 24180 has dup fanin 24151. |
| ABC: Node 24180 has dup fanin 24151. |
| ABC: Node 24181 has dup fanin 24151. |
| ABC: Node 24181 has dup fanin 24151. |
| ABC: Node 24182 has dup fanin 24151. |
| ABC: Node 24182 has dup fanin 24151. |
| ABC: Node 24183 has dup fanin 24151. |
| ABC: Node 24183 has dup fanin 24151. |
| ABC: Node 24268 has dup fanin 24186. |
| ABC: Node 24268 has dup fanin 24186. |
| ABC: Node 24296 has dup fanin 24186. |
| ABC: Node 24296 has dup fanin 24186. |
| ABC: Node 24300 has dup fanin 24186. |
| ABC: Node 24300 has dup fanin 24186. |
| ABC: Node 24412 has dup fanin 24186. |
| ABC: Node 24412 has dup fanin 24186. |
| ABC: Node 24416 has dup fanin 24186. |
| ABC: Node 24416 has dup fanin 24186. |
| ABC: Node 24432 has dup fanin 24186. |
| ABC: Node 24432 has dup fanin 24186. |
| ABC: Node 24436 has dup fanin 24186. |
| ABC: Node 24436 has dup fanin 24186. |
| ABC: Node 24442 has dup fanin 13505. |
| ABC: Node 24442 has dup fanin 13505. |
| ABC: Node 24446 has dup fanin 13505. |
| ABC: Node 24446 has dup fanin 13505. |
| ABC: Node 24450 has dup fanin 13505. |
| ABC: Node 24450 has dup fanin 13505. |
| ABC: Node 24454 has dup fanin 13505. |
| ABC: Node 24454 has dup fanin 13505. |
| ABC: Node 24458 has dup fanin 13505. |
| ABC: Node 24458 has dup fanin 13505. |
| ABC: Node 24462 has dup fanin 13505. |
| ABC: Node 24462 has dup fanin 13505. |
| ABC: Node 24467 has dup fanin 13505. |
| ABC: Node 24467 has dup fanin 13505. |
| ABC: Node 24476 has dup fanin 13505. |
| ABC: Node 24476 has dup fanin 13505. |
| ABC: Node 24480 has dup fanin 13505. |
| ABC: Node 24480 has dup fanin 13505. |
| ABC: Node 24484 has dup fanin 13505. |
| ABC: Node 24484 has dup fanin 13505. |
| ABC: Node 24489 has dup fanin 13505. |
| ABC: Node 24489 has dup fanin 13505. |
| ABC: Node 24498 has dup fanin 13505. |
| ABC: Node 24498 has dup fanin 13505. |
| ABC: Node 24502 has dup fanin 13505. |
| ABC: Node 24502 has dup fanin 13505. |
| ABC: Node 24506 has dup fanin 13505. |
| ABC: Node 24506 has dup fanin 13505. |
| ABC: Node 24510 has dup fanin 13505. |
| ABC: Node 24510 has dup fanin 13505. |
| ABC: Node 24514 has dup fanin 13505. |
| ABC: Node 24514 has dup fanin 13505. |
| ABC: Node 24518 has dup fanin 13505. |
| ABC: Node 24518 has dup fanin 13505. |
| ABC: Node 24523 has dup fanin 13505. |
| ABC: Node 24523 has dup fanin 13505. |
| ABC: Node 24527 has dup fanin 13505. |
| ABC: Node 24527 has dup fanin 13505. |
| ABC: Node 24531 has dup fanin 13505. |
| ABC: Node 24531 has dup fanin 13505. |
| ABC: Node 24535 has dup fanin 13505. |
| ABC: Node 24535 has dup fanin 13505. |
| ABC: Node 24539 has dup fanin 13505. |
| ABC: Node 24539 has dup fanin 13505. |
| ABC: Node 24543 has dup fanin 13505. |
| ABC: Node 24543 has dup fanin 13505. |
| ABC: Node 24547 has dup fanin 13505. |
| ABC: Node 24547 has dup fanin 13505. |
| ABC: Node 24551 has dup fanin 13505. |
| ABC: Node 24551 has dup fanin 13505. |
| ABC: Node 24558 has dup fanin 13505. |
| ABC: Node 24558 has dup fanin 13505. |
| ABC: Node 24563 has dup fanin 13505. |
| ABC: Node 24563 has dup fanin 13505. |
| ABC: Node 24568 has dup fanin 13505. |
| ABC: Node 24568 has dup fanin 13505. |
| ABC: Node 24573 has dup fanin 13505. |
| ABC: Node 24573 has dup fanin 13505. |
| ABC: Node 25118 has dup fanin 24577. |
| ABC: Node 25118 has dup fanin 24577. |
| ABC: Node 25145 has dup fanin 24577. |
| ABC: Node 25145 has dup fanin 24577. |
| ABC: Node 25246 has dup fanin 11402. |
| ABC: Node 25246 has dup fanin 11402. |
| ABC: Node 25249 has dup fanin 14606. |
| ABC: Node 25249 has dup fanin 14606. |
| ABC: Node 25253 has dup fanin 24577. |
| ABC: Node 25253 has dup fanin 24577. |
| ABC: Node 25272 has dup fanin 11402. |
| ABC: Node 25272 has dup fanin 11402. |
| ABC: Node 25275 has dup fanin 14606. |
| ABC: Node 25275 has dup fanin 14606. |
| ABC: Node 25279 has dup fanin 24577. |
| ABC: Node 25279 has dup fanin 24577. |
| ABC: Node 25298 has dup fanin 11402. |
| ABC: Node 25298 has dup fanin 11402. |
| ABC: Node 25301 has dup fanin 14606. |
| ABC: Node 25301 has dup fanin 14606. |
| ABC: Node 25305 has dup fanin 24577. |
| ABC: Node 25305 has dup fanin 24577. |
| ABC: Node 25329 has dup fanin 14606. |
| ABC: Node 25329 has dup fanin 14606. |
| ABC: Node 25332 has dup fanin 11402. |
| ABC: Node 25332 has dup fanin 11402. |
| ABC: Node 25336 has dup fanin 24577. |
| ABC: Node 25336 has dup fanin 24577. |
| ABC: Node 25359 has dup fanin 14606. |
| ABC: Node 25359 has dup fanin 14606. |
| ABC: Node 25362 has dup fanin 11402. |
| ABC: Node 25362 has dup fanin 11402. |
| ABC: Node 25366 has dup fanin 24577. |
| ABC: Node 25366 has dup fanin 24577. |
| ABC: Node 25370 has dup fanin 13506. |
| ABC: Node 25370 has dup fanin 13506. |
| ABC: Node 25439 has dup fanin 25371. |
| ABC: Node 25439 has dup fanin 25371. |
| ABC: Node 25503 has dup fanin 25371. |
| ABC: Node 25503 has dup fanin 25371. |
| ABC: Node 25567 has dup fanin 25371. |
| ABC: Node 25567 has dup fanin 25371. |
| ABC: Node 25631 has dup fanin 25371. |
| ABC: Node 25631 has dup fanin 25371. |
| ABC: Node 25695 has dup fanin 25371. |
| ABC: Node 25695 has dup fanin 25371. |
| ABC: Node 25759 has dup fanin 25371. |
| ABC: Node 25759 has dup fanin 25371. |
| ABC: Node 25823 has dup fanin 25371. |
| ABC: Node 25823 has dup fanin 25371. |
| ABC: Node 25887 has dup fanin 25371. |
| ABC: Node 25887 has dup fanin 25371. |
| ABC: Node 25951 has dup fanin 25371. |
| ABC: Node 25951 has dup fanin 25371. |
| ABC: Node 26015 has dup fanin 25371. |
| ABC: Node 26015 has dup fanin 25371. |
| ABC: Node 26079 has dup fanin 25371. |
| ABC: Node 26079 has dup fanin 25371. |
| ABC: Node 26143 has dup fanin 25371. |
| ABC: Node 26143 has dup fanin 25371. |
| ABC: Node 26207 has dup fanin 25371. |
| ABC: Node 26207 has dup fanin 25371. |
| ABC: Node 26271 has dup fanin 25371. |
| ABC: Node 26271 has dup fanin 25371. |
| ABC: Node 26335 has dup fanin 25371. |
| ABC: Node 26335 has dup fanin 25371. |
| ABC: Node 26399 has dup fanin 25371. |
| ABC: Node 26399 has dup fanin 25371. |
| ABC: Node 26463 has dup fanin 25371. |
| ABC: Node 26463 has dup fanin 25371. |
| ABC: Node 26527 has dup fanin 25371. |
| ABC: Node 26527 has dup fanin 25371. |
| ABC: Node 26591 has dup fanin 25371. |
| ABC: Node 26591 has dup fanin 25371. |
| ABC: Node 26655 has dup fanin 25371. |
| ABC: Node 26655 has dup fanin 25371. |
| ABC: Node 26719 has dup fanin 25371. |
| ABC: Node 26719 has dup fanin 25371. |
| ABC: Node 26783 has dup fanin 25371. |
| ABC: Node 26783 has dup fanin 25371. |
| ABC: Node 26847 has dup fanin 25371. |
| ABC: Node 26847 has dup fanin 25371. |
| ABC: Node 26911 has dup fanin 25371. |
| ABC: Node 26911 has dup fanin 25371. |
| ABC: Node 26975 has dup fanin 25371. |
| ABC: Node 26975 has dup fanin 25371. |
| ABC: Node 27039 has dup fanin 25371. |
| ABC: Node 27039 has dup fanin 25371. |
| ABC: Node 27103 has dup fanin 25371. |
| ABC: Node 27103 has dup fanin 25371. |
| ABC: Node 27168 has dup fanin 25371. |
| ABC: Node 27168 has dup fanin 25371. |
| ABC: Node 27233 has dup fanin 25371. |
| ABC: Node 27233 has dup fanin 25371. |
| ABC: Node 27298 has dup fanin 25371. |
| ABC: Node 27298 has dup fanin 25371. |
| ABC: Node 27363 has dup fanin 25371. |
| ABC: Node 27363 has dup fanin 25371. |
| ABC: Node 27428 has dup fanin 25371. |
| ABC: Node 27428 has dup fanin 25371. |
| ABC: Node 27813 has dup fanin 10377. |
| ABC: Node 27813 has dup fanin 10377. |
| ABC: Node 28208 has dup fanin 10245. |
| ABC: Node 28208 has dup fanin 10245. |
| ABC: Node 28214 has dup fanin 28213. |
| ABC: Node 28214 has dup fanin 28213. |
| ABC: Node 28215 has dup fanin 28213. |
| ABC: Node 28215 has dup fanin 28213. |
| ABC: Node 28216 has dup fanin 28213. |
| ABC: Node 28216 has dup fanin 28213. |
| ABC: Node 28217 has dup fanin 28213. |
| ABC: Node 28217 has dup fanin 28213. |
| ABC: Node 28218 has dup fanin 28213. |
| ABC: Node 28218 has dup fanin 28213. |
| ABC: Node 28219 has dup fanin 28213. |
| ABC: Node 28219 has dup fanin 28213. |
| ABC: Node 28220 has dup fanin 28213. |
| ABC: Node 28220 has dup fanin 28213. |
| ABC: Node 28221 has dup fanin 28213. |
| ABC: Node 28221 has dup fanin 28213. |
| ABC: Node 28222 has dup fanin 28213. |
| ABC: Node 28222 has dup fanin 28213. |
| ABC: Node 28223 has dup fanin 28213. |
| ABC: Node 28223 has dup fanin 28213. |
| ABC: Node 28224 has dup fanin 28213. |
| ABC: Node 28224 has dup fanin 28213. |
| ABC: Node 28225 has dup fanin 28213. |
| ABC: Node 28225 has dup fanin 28213. |
| ABC: Node 28226 has dup fanin 28213. |
| ABC: Node 28226 has dup fanin 28213. |
| ABC: Node 28227 has dup fanin 28213. |
| ABC: Node 28227 has dup fanin 28213. |
| ABC: Node 28228 has dup fanin 28213. |
| ABC: Node 28228 has dup fanin 28213. |
| ABC: Node 28229 has dup fanin 28213. |
| ABC: Node 28229 has dup fanin 28213. |
| ABC: Node 28231 has dup fanin 28230. |
| ABC: Node 28231 has dup fanin 28230. |
| ABC: Node 28232 has dup fanin 28230. |
| ABC: Node 28232 has dup fanin 28230. |
| ABC: Node 28233 has dup fanin 28230. |
| ABC: Node 28233 has dup fanin 28230. |
| ABC: Node 28234 has dup fanin 28230. |
| ABC: Node 28234 has dup fanin 28230. |
| ABC: Node 28235 has dup fanin 28230. |
| ABC: Node 28235 has dup fanin 28230. |
| ABC: Node 28236 has dup fanin 28230. |
| ABC: Node 28236 has dup fanin 28230. |
| ABC: Node 28237 has dup fanin 28230. |
| ABC: Node 28237 has dup fanin 28230. |
| ABC: Node 28238 has dup fanin 28230. |
| ABC: Node 28238 has dup fanin 28230. |
| ABC: Node 28239 has dup fanin 28230. |
| ABC: Node 28239 has dup fanin 28230. |
| ABC: Node 28240 has dup fanin 28230. |
| ABC: Node 28240 has dup fanin 28230. |
| ABC: Node 28241 has dup fanin 28230. |
| ABC: Node 28241 has dup fanin 28230. |
| ABC: Node 28242 has dup fanin 28230. |
| ABC: Node 28242 has dup fanin 28230. |
| ABC: Node 28243 has dup fanin 28230. |
| ABC: Node 28243 has dup fanin 28230. |
| ABC: Node 28244 has dup fanin 28230. |
| ABC: Node 28244 has dup fanin 28230. |
| ABC: Node 28245 has dup fanin 28230. |
| ABC: Node 28245 has dup fanin 28230. |
| ABC: Node 28246 has dup fanin 28230. |
| ABC: Node 28246 has dup fanin 28230. |
| ABC: Node 28247 has dup fanin 28230. |
| ABC: Node 28247 has dup fanin 28230. |
| ABC: Node 28248 has dup fanin 28230. |
| ABC: Node 28248 has dup fanin 28230. |
| ABC: Node 28249 has dup fanin 28230. |
| ABC: Node 28249 has dup fanin 28230. |
| ABC: Node 28250 has dup fanin 28230. |
| ABC: Node 28250 has dup fanin 28230. |
| ABC: Node 28251 has dup fanin 28230. |
| ABC: Node 28251 has dup fanin 28230. |
| ABC: Node 28252 has dup fanin 28230. |
| ABC: Node 28252 has dup fanin 28230. |
| ABC: Node 28253 has dup fanin 28230. |
| ABC: Node 28253 has dup fanin 28230. |
| ABC: Node 28254 has dup fanin 28230. |
| ABC: Node 28254 has dup fanin 28230. |
| ABC: Node 28255 has dup fanin 28230. |
| ABC: Node 28255 has dup fanin 28230. |
| ABC: Node 28256 has dup fanin 28230. |
| ABC: Node 28256 has dup fanin 28230. |
| ABC: Node 28257 has dup fanin 28230. |
| ABC: Node 28257 has dup fanin 28230. |
| ABC: Node 28258 has dup fanin 28230. |
| ABC: Node 28258 has dup fanin 28230. |
| ABC: Node 28259 has dup fanin 28230. |
| ABC: Node 28259 has dup fanin 28230. |
| ABC: Node 28260 has dup fanin 28230. |
| ABC: Node 28260 has dup fanin 28230. |
| ABC: Node 28261 has dup fanin 28230. |
| ABC: Node 28261 has dup fanin 28230. |
| ABC: Node 28262 has dup fanin 28230. |
| ABC: Node 28262 has dup fanin 28230. |
| ABC: Node 28264 has dup fanin 28263. |
| ABC: Node 28264 has dup fanin 28263. |
| ABC: Node 28265 has dup fanin 28263. |
| ABC: Node 28265 has dup fanin 28263. |
| ABC: Node 28266 has dup fanin 28263. |
| ABC: Node 28266 has dup fanin 28263. |
| ABC: Node 28267 has dup fanin 28263. |
| ABC: Node 28267 has dup fanin 28263. |
| ABC: Node 28268 has dup fanin 28263. |
| ABC: Node 28268 has dup fanin 28263. |
| ABC: Node 28269 has dup fanin 28263. |
| ABC: Node 28269 has dup fanin 28263. |
| ABC: Node 28270 has dup fanin 28263. |
| ABC: Node 28270 has dup fanin 28263. |
| ABC: Node 28271 has dup fanin 28263. |
| ABC: Node 28271 has dup fanin 28263. |
| ABC: Node 28272 has dup fanin 28263. |
| ABC: Node 28272 has dup fanin 28263. |
| ABC: Node 28273 has dup fanin 28263. |
| ABC: Node 28273 has dup fanin 28263. |
| ABC: Node 28274 has dup fanin 28263. |
| ABC: Node 28274 has dup fanin 28263. |
| ABC: Node 28275 has dup fanin 28263. |
| ABC: Node 28275 has dup fanin 28263. |
| ABC: Node 28276 has dup fanin 28263. |
| ABC: Node 28276 has dup fanin 28263. |
| ABC: Node 28277 has dup fanin 28263. |
| ABC: Node 28277 has dup fanin 28263. |
| ABC: Node 28278 has dup fanin 28263. |
| ABC: Node 28278 has dup fanin 28263. |
| ABC: Node 28279 has dup fanin 28263. |
| ABC: Node 28279 has dup fanin 28263. |
| ABC: Node 28280 has dup fanin 28263. |
| ABC: Node 28280 has dup fanin 28263. |
| ABC: Node 28281 has dup fanin 28263. |
| ABC: Node 28281 has dup fanin 28263. |
| ABC: Node 28282 has dup fanin 28263. |
| ABC: Node 28282 has dup fanin 28263. |
| ABC: Node 28283 has dup fanin 28263. |
| ABC: Node 28283 has dup fanin 28263. |
| ABC: Node 28284 has dup fanin 28263. |
| ABC: Node 28284 has dup fanin 28263. |
| ABC: Node 28285 has dup fanin 28263. |
| ABC: Node 28285 has dup fanin 28263. |
| ABC: Node 28286 has dup fanin 28263. |
| ABC: Node 28286 has dup fanin 28263. |
| ABC: Node 28287 has dup fanin 28263. |
| ABC: Node 28287 has dup fanin 28263. |
| ABC: Node 28288 has dup fanin 28263. |
| ABC: Node 28288 has dup fanin 28263. |
| ABC: Node 28289 has dup fanin 28263. |
| ABC: Node 28289 has dup fanin 28263. |
| ABC: Node 28290 has dup fanin 28263. |
| ABC: Node 28290 has dup fanin 28263. |
| ABC: Node 28291 has dup fanin 28263. |
| ABC: Node 28291 has dup fanin 28263. |
| ABC: Node 28292 has dup fanin 28263. |
| ABC: Node 28292 has dup fanin 28263. |
| ABC: Node 28293 has dup fanin 28263. |
| ABC: Node 28293 has dup fanin 28263. |
| ABC: Node 28294 has dup fanin 28263. |
| ABC: Node 28294 has dup fanin 28263. |
| ABC: Node 28295 has dup fanin 28263. |
| ABC: Node 28295 has dup fanin 28263. |
| ABC: Node 28297 has dup fanin 28296. |
| ABC: Node 28297 has dup fanin 28296. |
| ABC: Node 28298 has dup fanin 28296. |
| ABC: Node 28298 has dup fanin 28296. |
| ABC: Node 28299 has dup fanin 28296. |
| ABC: Node 28299 has dup fanin 28296. |
| ABC: Node 28300 has dup fanin 28296. |
| ABC: Node 28300 has dup fanin 28296. |
| ABC: Node 28301 has dup fanin 28296. |
| ABC: Node 28301 has dup fanin 28296. |
| ABC: Node 28302 has dup fanin 28296. |
| ABC: Node 28302 has dup fanin 28296. |
| ABC: Node 28303 has dup fanin 28296. |
| ABC: Node 28303 has dup fanin 28296. |
| ABC: Node 28304 has dup fanin 28296. |
| ABC: Node 28304 has dup fanin 28296. |
| ABC: Node 28305 has dup fanin 28296. |
| ABC: Node 28305 has dup fanin 28296. |
| ABC: Node 28306 has dup fanin 28296. |
| ABC: Node 28306 has dup fanin 28296. |
| ABC: Node 28307 has dup fanin 28296. |
| ABC: Node 28307 has dup fanin 28296. |
| ABC: Node 28308 has dup fanin 28296. |
| ABC: Node 28308 has dup fanin 28296. |
| ABC: Node 28309 has dup fanin 28296. |
| ABC: Node 28309 has dup fanin 28296. |
| ABC: Node 28310 has dup fanin 28296. |
| ABC: Node 28310 has dup fanin 28296. |
| ABC: Node 28311 has dup fanin 28296. |
| ABC: Node 28311 has dup fanin 28296. |
| ABC: Node 28312 has dup fanin 28296. |
| ABC: Node 28312 has dup fanin 28296. |
| ABC: Node 28313 has dup fanin 28296. |
| ABC: Node 28313 has dup fanin 28296. |
| ABC: Node 28314 has dup fanin 28296. |
| ABC: Node 28314 has dup fanin 28296. |
| ABC: Node 28315 has dup fanin 28296. |
| ABC: Node 28315 has dup fanin 28296. |
| ABC: Node 28316 has dup fanin 28296. |
| ABC: Node 28316 has dup fanin 28296. |
| ABC: Node 28317 has dup fanin 28296. |
| ABC: Node 28317 has dup fanin 28296. |
| ABC: Node 28318 has dup fanin 28296. |
| ABC: Node 28318 has dup fanin 28296. |
| ABC: Node 28319 has dup fanin 28296. |
| ABC: Node 28319 has dup fanin 28296. |
| ABC: Node 28320 has dup fanin 28296. |
| ABC: Node 28320 has dup fanin 28296. |
| ABC: Node 28321 has dup fanin 28296. |
| ABC: Node 28321 has dup fanin 28296. |
| ABC: Node 28322 has dup fanin 28296. |
| ABC: Node 28322 has dup fanin 28296. |
| ABC: Node 28323 has dup fanin 28296. |
| ABC: Node 28323 has dup fanin 28296. |
| ABC: Node 28324 has dup fanin 28296. |
| ABC: Node 28324 has dup fanin 28296. |
| ABC: Node 28325 has dup fanin 28296. |
| ABC: Node 28325 has dup fanin 28296. |
| ABC: Node 28326 has dup fanin 28296. |
| ABC: Node 28326 has dup fanin 28296. |
| ABC: Node 28327 has dup fanin 28296. |
| ABC: Node 28327 has dup fanin 28296. |
| ABC: Node 28328 has dup fanin 28296. |
| ABC: Node 28328 has dup fanin 28296. |
| ABC: Node 28330 has dup fanin 28329. |
| ABC: Node 28330 has dup fanin 28329. |
| ABC: Node 28331 has dup fanin 28329. |
| ABC: Node 28331 has dup fanin 28329. |
| ABC: Node 28332 has dup fanin 28329. |
| ABC: Node 28332 has dup fanin 28329. |
| ABC: Node 28333 has dup fanin 28329. |
| ABC: Node 28333 has dup fanin 28329. |
| ABC: Node 28334 has dup fanin 28329. |
| ABC: Node 28334 has dup fanin 28329. |
| ABC: Node 28335 has dup fanin 28329. |
| ABC: Node 28335 has dup fanin 28329. |
| ABC: Node 28336 has dup fanin 28329. |
| ABC: Node 28336 has dup fanin 28329. |
| ABC: Node 28337 has dup fanin 28329. |
| ABC: Node 28337 has dup fanin 28329. |
| ABC: Node 28338 has dup fanin 28329. |
| ABC: Node 28338 has dup fanin 28329. |
| ABC: Node 28339 has dup fanin 28329. |
| ABC: Node 28339 has dup fanin 28329. |
| ABC: Node 28340 has dup fanin 28329. |
| ABC: Node 28340 has dup fanin 28329. |
| ABC: Node 28341 has dup fanin 28329. |
| ABC: Node 28341 has dup fanin 28329. |
| ABC: Node 28342 has dup fanin 28329. |
| ABC: Node 28342 has dup fanin 28329. |
| ABC: Node 28343 has dup fanin 28329. |
| ABC: Node 28343 has dup fanin 28329. |
| ABC: Node 28344 has dup fanin 28329. |
| ABC: Node 28344 has dup fanin 28329. |
| ABC: Node 28345 has dup fanin 28329. |
| ABC: Node 28345 has dup fanin 28329. |
| ABC: Node 28346 has dup fanin 28329. |
| ABC: Node 28346 has dup fanin 28329. |
| ABC: Node 28347 has dup fanin 28329. |
| ABC: Node 28347 has dup fanin 28329. |
| ABC: Node 28348 has dup fanin 28329. |
| ABC: Node 28348 has dup fanin 28329. |
| ABC: Node 28349 has dup fanin 28329. |
| ABC: Node 28349 has dup fanin 28329. |
| ABC: Node 28350 has dup fanin 28329. |
| ABC: Node 28350 has dup fanin 28329. |
| ABC: Node 28351 has dup fanin 28329. |
| ABC: Node 28351 has dup fanin 28329. |
| ABC: Node 28352 has dup fanin 28329. |
| ABC: Node 28352 has dup fanin 28329. |
| ABC: Node 28353 has dup fanin 28329. |
| ABC: Node 28353 has dup fanin 28329. |
| ABC: Node 28354 has dup fanin 28329. |
| ABC: Node 28354 has dup fanin 28329. |
| ABC: Node 28355 has dup fanin 28329. |
| ABC: Node 28355 has dup fanin 28329. |
| ABC: Node 28356 has dup fanin 28329. |
| ABC: Node 28356 has dup fanin 28329. |
| ABC: Node 28357 has dup fanin 28329. |
| ABC: Node 28357 has dup fanin 28329. |
| ABC: Node 28358 has dup fanin 28329. |
| ABC: Node 28358 has dup fanin 28329. |
| ABC: Node 28359 has dup fanin 28329. |
| ABC: Node 28359 has dup fanin 28329. |
| ABC: Node 28360 has dup fanin 28329. |
| ABC: Node 28360 has dup fanin 28329. |
| ABC: Node 28361 has dup fanin 28329. |
| ABC: Node 28361 has dup fanin 28329. |
| ABC: Node 28363 has dup fanin 28362. |
| ABC: Node 28363 has dup fanin 28362. |
| ABC: Node 28364 has dup fanin 28362. |
| ABC: Node 28364 has dup fanin 28362. |
| ABC: Node 28365 has dup fanin 28362. |
| ABC: Node 28365 has dup fanin 28362. |
| ABC: Node 28366 has dup fanin 28362. |
| ABC: Node 28366 has dup fanin 28362. |
| ABC: Node 28367 has dup fanin 28362. |
| ABC: Node 28367 has dup fanin 28362. |
| ABC: Node 28368 has dup fanin 28362. |
| ABC: Node 28368 has dup fanin 28362. |
| ABC: Node 28369 has dup fanin 28362. |
| ABC: Node 28369 has dup fanin 28362. |
| ABC: Node 28370 has dup fanin 28362. |
| ABC: Node 28370 has dup fanin 28362. |
| ABC: Node 28371 has dup fanin 28362. |
| ABC: Node 28371 has dup fanin 28362. |
| ABC: Node 28372 has dup fanin 28362. |
| ABC: Node 28372 has dup fanin 28362. |
| ABC: Node 28373 has dup fanin 28362. |
| ABC: Node 28373 has dup fanin 28362. |
| ABC: Node 28374 has dup fanin 28362. |
| ABC: Node 28374 has dup fanin 28362. |
| ABC: Node 28375 has dup fanin 28362. |
| ABC: Node 28375 has dup fanin 28362. |
| ABC: Node 28376 has dup fanin 28362. |
| ABC: Node 28376 has dup fanin 28362. |
| ABC: Node 28377 has dup fanin 28362. |
| ABC: Node 28377 has dup fanin 28362. |
| ABC: Node 28378 has dup fanin 28362. |
| ABC: Node 28378 has dup fanin 28362. |
| ABC: Node 28379 has dup fanin 28362. |
| ABC: Node 28379 has dup fanin 28362. |
| ABC: Node 28380 has dup fanin 28362. |
| ABC: Node 28380 has dup fanin 28362. |
| ABC: Node 28381 has dup fanin 28362. |
| ABC: Node 28381 has dup fanin 28362. |
| ABC: Node 28382 has dup fanin 28362. |
| ABC: Node 28382 has dup fanin 28362. |
| ABC: Node 28383 has dup fanin 28362. |
| ABC: Node 28383 has dup fanin 28362. |
| ABC: Node 28384 has dup fanin 28362. |
| ABC: Node 28384 has dup fanin 28362. |
| ABC: Node 28385 has dup fanin 28362. |
| ABC: Node 28385 has dup fanin 28362. |
| ABC: Node 28386 has dup fanin 28362. |
| ABC: Node 28386 has dup fanin 28362. |
| ABC: Node 28387 has dup fanin 28362. |
| ABC: Node 28387 has dup fanin 28362. |
| ABC: Node 28388 has dup fanin 28362. |
| ABC: Node 28388 has dup fanin 28362. |
| ABC: Node 28389 has dup fanin 28362. |
| ABC: Node 28389 has dup fanin 28362. |
| ABC: Node 28390 has dup fanin 28362. |
| ABC: Node 28390 has dup fanin 28362. |
| ABC: Node 28391 has dup fanin 28362. |
| ABC: Node 28391 has dup fanin 28362. |
| ABC: Node 28392 has dup fanin 28362. |
| ABC: Node 28392 has dup fanin 28362. |
| ABC: Node 28393 has dup fanin 28362. |
| ABC: Node 28393 has dup fanin 28362. |
| ABC: Node 28394 has dup fanin 28362. |
| ABC: Node 28394 has dup fanin 28362. |
| ABC: Node 28396 has dup fanin 28395. |
| ABC: Node 28396 has dup fanin 28395. |
| ABC: Node 28397 has dup fanin 28395. |
| ABC: Node 28397 has dup fanin 28395. |
| ABC: Node 28398 has dup fanin 28395. |
| ABC: Node 28398 has dup fanin 28395. |
| ABC: Node 28399 has dup fanin 28395. |
| ABC: Node 28399 has dup fanin 28395. |
| ABC: Node 28400 has dup fanin 28395. |
| ABC: Node 28400 has dup fanin 28395. |
| ABC: Node 28401 has dup fanin 28395. |
| ABC: Node 28401 has dup fanin 28395. |
| ABC: Node 28402 has dup fanin 28395. |
| ABC: Node 28402 has dup fanin 28395. |
| ABC: Node 28403 has dup fanin 28395. |
| ABC: Node 28403 has dup fanin 28395. |
| ABC: Node 28404 has dup fanin 28395. |
| ABC: Node 28404 has dup fanin 28395. |
| ABC: Node 28405 has dup fanin 28395. |
| ABC: Node 28405 has dup fanin 28395. |
| ABC: Node 28406 has dup fanin 28395. |
| ABC: Node 28406 has dup fanin 28395. |
| ABC: Node 28407 has dup fanin 28395. |
| ABC: Node 28407 has dup fanin 28395. |
| ABC: Node 28408 has dup fanin 28395. |
| ABC: Node 28408 has dup fanin 28395. |
| ABC: Node 28409 has dup fanin 28395. |
| ABC: Node 28409 has dup fanin 28395. |
| ABC: Node 28410 has dup fanin 28395. |
| ABC: Node 28410 has dup fanin 28395. |
| ABC: Node 28411 has dup fanin 28395. |
| ABC: Node 28411 has dup fanin 28395. |
| ABC: Node 28412 has dup fanin 28395. |
| ABC: Node 28412 has dup fanin 28395. |
| ABC: Node 28413 has dup fanin 28395. |
| ABC: Node 28413 has dup fanin 28395. |
| ABC: Node 28414 has dup fanin 28395. |
| ABC: Node 28414 has dup fanin 28395. |
| ABC: Node 28415 has dup fanin 28395. |
| ABC: Node 28415 has dup fanin 28395. |
| ABC: Node 28416 has dup fanin 28395. |
| ABC: Node 28416 has dup fanin 28395. |
| ABC: Node 28417 has dup fanin 28395. |
| ABC: Node 28417 has dup fanin 28395. |
| ABC: Node 28418 has dup fanin 28395. |
| ABC: Node 28418 has dup fanin 28395. |
| ABC: Node 28419 has dup fanin 28395. |
| ABC: Node 28419 has dup fanin 28395. |
| ABC: Node 28420 has dup fanin 28395. |
| ABC: Node 28420 has dup fanin 28395. |
| ABC: Node 28421 has dup fanin 28395. |
| ABC: Node 28421 has dup fanin 28395. |
| ABC: Node 28422 has dup fanin 28395. |
| ABC: Node 28422 has dup fanin 28395. |
| ABC: Node 28423 has dup fanin 28395. |
| ABC: Node 28423 has dup fanin 28395. |
| ABC: Node 28424 has dup fanin 28395. |
| ABC: Node 28424 has dup fanin 28395. |
| ABC: Node 28425 has dup fanin 28395. |
| ABC: Node 28425 has dup fanin 28395. |
| ABC: Node 28426 has dup fanin 28395. |
| ABC: Node 28426 has dup fanin 28395. |
| ABC: Node 28427 has dup fanin 28395. |
| ABC: Node 28427 has dup fanin 28395. |
| ABC: Node 28432 has dup fanin 10377. |
| ABC: Node 28432 has dup fanin 10377. |
| ABC: Node 28438 has dup fanin 28437. |
| ABC: Node 28438 has dup fanin 28437. |
| ABC: Node 28439 has dup fanin 28437. |
| ABC: Node 28439 has dup fanin 28437. |
| ABC: Node 28440 has dup fanin 28437. |
| ABC: Node 28440 has dup fanin 28437. |
| ABC: Node 28441 has dup fanin 28437. |
| ABC: Node 28441 has dup fanin 28437. |
| ABC: Node 28442 has dup fanin 28437. |
| ABC: Node 28442 has dup fanin 28437. |
| ABC: Node 28443 has dup fanin 28437. |
| ABC: Node 28443 has dup fanin 28437. |
| ABC: Node 28444 has dup fanin 28437. |
| ABC: Node 28444 has dup fanin 28437. |
| ABC: Node 28445 has dup fanin 28437. |
| ABC: Node 28445 has dup fanin 28437. |
| ABC: Node 28446 has dup fanin 28437. |
| ABC: Node 28446 has dup fanin 28437. |
| ABC: Node 28447 has dup fanin 28437. |
| ABC: Node 28447 has dup fanin 28437. |
| ABC: Node 28448 has dup fanin 28437. |
| ABC: Node 28448 has dup fanin 28437. |
| ABC: Node 28449 has dup fanin 28437. |
| ABC: Node 28449 has dup fanin 28437. |
| ABC: Node 28450 has dup fanin 28437. |
| ABC: Node 28450 has dup fanin 28437. |
| ABC: Node 28451 has dup fanin 28437. |
| ABC: Node 28451 has dup fanin 28437. |
| ABC: Node 28452 has dup fanin 28437. |
| ABC: Node 28452 has dup fanin 28437. |
| ABC: Node 28453 has dup fanin 28437. |
| ABC: Node 28453 has dup fanin 28437. |
| ABC: Node 28454 has dup fanin 28437. |
| ABC: Node 28454 has dup fanin 28437. |
| ABC: Node 28455 has dup fanin 28437. |
| ABC: Node 28455 has dup fanin 28437. |
| ABC: Node 28456 has dup fanin 28437. |
| ABC: Node 28456 has dup fanin 28437. |
| ABC: Node 28457 has dup fanin 28437. |
| ABC: Node 28457 has dup fanin 28437. |
| ABC: Node 28458 has dup fanin 28437. |
| ABC: Node 28458 has dup fanin 28437. |
| ABC: Node 28459 has dup fanin 28437. |
| ABC: Node 28459 has dup fanin 28437. |
| ABC: Node 28460 has dup fanin 28437. |
| ABC: Node 28460 has dup fanin 28437. |
| ABC: Node 28461 has dup fanin 28437. |
| ABC: Node 28461 has dup fanin 28437. |
| ABC: Node 28462 has dup fanin 28437. |
| ABC: Node 28462 has dup fanin 28437. |
| ABC: Node 28463 has dup fanin 28437. |
| ABC: Node 28463 has dup fanin 28437. |
| ABC: Node 28464 has dup fanin 28437. |
| ABC: Node 28464 has dup fanin 28437. |
| ABC: Node 28465 has dup fanin 28437. |
| ABC: Node 28465 has dup fanin 28437. |
| ABC: Node 28466 has dup fanin 28437. |
| ABC: Node 28466 has dup fanin 28437. |
| ABC: Node 28467 has dup fanin 28437. |
| ABC: Node 28467 has dup fanin 28437. |
| ABC: Node 28468 has dup fanin 28437. |
| ABC: Node 28468 has dup fanin 28437. |
| ABC: Node 28469 has dup fanin 28437. |
| ABC: Node 28469 has dup fanin 28437. |
| ABC: Node 28471 has dup fanin 28470. |
| ABC: Node 28471 has dup fanin 28470. |
| ABC: Node 28472 has dup fanin 28470. |
| ABC: Node 28472 has dup fanin 28470. |
| ABC: Node 28473 has dup fanin 28470. |
| ABC: Node 28473 has dup fanin 28470. |
| ABC: Node 28474 has dup fanin 28470. |
| ABC: Node 28474 has dup fanin 28470. |
| ABC: Node 28475 has dup fanin 28470. |
| ABC: Node 28475 has dup fanin 28470. |
| ABC: Node 28476 has dup fanin 28470. |
| ABC: Node 28476 has dup fanin 28470. |
| ABC: Node 28477 has dup fanin 28470. |
| ABC: Node 28477 has dup fanin 28470. |
| ABC: Node 28478 has dup fanin 28470. |
| ABC: Node 28478 has dup fanin 28470. |
| ABC: Node 28479 has dup fanin 28470. |
| ABC: Node 28479 has dup fanin 28470. |
| ABC: Node 28480 has dup fanin 28470. |
| ABC: Node 28480 has dup fanin 28470. |
| ABC: Node 28481 has dup fanin 28470. |
| ABC: Node 28481 has dup fanin 28470. |
| ABC: Node 28482 has dup fanin 28470. |
| ABC: Node 28482 has dup fanin 28470. |
| ABC: Node 28483 has dup fanin 28470. |
| ABC: Node 28483 has dup fanin 28470. |
| ABC: Node 28484 has dup fanin 28470. |
| ABC: Node 28484 has dup fanin 28470. |
| ABC: Node 28485 has dup fanin 28470. |
| ABC: Node 28485 has dup fanin 28470. |
| ABC: Node 28486 has dup fanin 28470. |
| ABC: Node 28486 has dup fanin 28470. |
| ABC: Node 28487 has dup fanin 28470. |
| ABC: Node 28487 has dup fanin 28470. |
| ABC: Node 28488 has dup fanin 28470. |
| ABC: Node 28488 has dup fanin 28470. |
| ABC: Node 28489 has dup fanin 28470. |
| ABC: Node 28489 has dup fanin 28470. |
| ABC: Node 28490 has dup fanin 28470. |
| ABC: Node 28490 has dup fanin 28470. |
| ABC: Node 28491 has dup fanin 28470. |
| ABC: Node 28491 has dup fanin 28470. |
| ABC: Node 28492 has dup fanin 28470. |
| ABC: Node 28492 has dup fanin 28470. |
| ABC: Node 28493 has dup fanin 28470. |
| ABC: Node 28493 has dup fanin 28470. |
| ABC: Node 28494 has dup fanin 28470. |
| ABC: Node 28494 has dup fanin 28470. |
| ABC: Node 28495 has dup fanin 28470. |
| ABC: Node 28495 has dup fanin 28470. |
| ABC: Node 28496 has dup fanin 28470. |
| ABC: Node 28496 has dup fanin 28470. |
| ABC: Node 28497 has dup fanin 28470. |
| ABC: Node 28497 has dup fanin 28470. |
| ABC: Node 28498 has dup fanin 28470. |
| ABC: Node 28498 has dup fanin 28470. |
| ABC: Node 28499 has dup fanin 28470. |
| ABC: Node 28499 has dup fanin 28470. |
| ABC: Node 28500 has dup fanin 28470. |
| ABC: Node 28500 has dup fanin 28470. |
| ABC: Node 28501 has dup fanin 28470. |
| ABC: Node 28501 has dup fanin 28470. |
| ABC: Node 28502 has dup fanin 28470. |
| ABC: Node 28502 has dup fanin 28470. |
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| ABC: Node 28504 has dup fanin 28503. |
| ABC: Node 28505 has dup fanin 28503. |
| ABC: Node 28505 has dup fanin 28503. |
| ABC: Node 28506 has dup fanin 28503. |
| ABC: Node 28506 has dup fanin 28503. |
| ABC: Node 28507 has dup fanin 28503. |
| ABC: Node 28507 has dup fanin 28503. |
| ABC: Node 28508 has dup fanin 28503. |
| ABC: Node 28508 has dup fanin 28503. |
| ABC: Node 28509 has dup fanin 28503. |
| ABC: Node 28509 has dup fanin 28503. |
| ABC: Node 28510 has dup fanin 28503. |
| ABC: Node 28510 has dup fanin 28503. |
| ABC: Node 28511 has dup fanin 28503. |
| ABC: Node 28511 has dup fanin 28503. |
| ABC: Node 28512 has dup fanin 28503. |
| ABC: Node 28512 has dup fanin 28503. |
| ABC: Node 28513 has dup fanin 28503. |
| ABC: Node 28513 has dup fanin 28503. |
| ABC: Node 28514 has dup fanin 28503. |
| ABC: Node 28514 has dup fanin 28503. |
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| ABC: Node 28515 has dup fanin 28503. |
| ABC: Node 28516 has dup fanin 28503. |
| ABC: Node 28516 has dup fanin 28503. |
| ABC: Node 28517 has dup fanin 28503. |
| ABC: Node 28517 has dup fanin 28503. |
| ABC: Node 28518 has dup fanin 28503. |
| ABC: Node 28518 has dup fanin 28503. |
| ABC: Node 28519 has dup fanin 28503. |
| ABC: Node 28519 has dup fanin 28503. |
| ABC: Node 28520 has dup fanin 28503. |
| ABC: Node 28520 has dup fanin 28503. |
| ABC: Node 28521 has dup fanin 28503. |
| ABC: Node 28521 has dup fanin 28503. |
| ABC: Node 28522 has dup fanin 28503. |
| ABC: Node 28522 has dup fanin 28503. |
| ABC: Node 28523 has dup fanin 28503. |
| ABC: Node 28523 has dup fanin 28503. |
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| ABC: Node 28524 has dup fanin 28503. |
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| ABC: Node 28525 has dup fanin 28503. |
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| ABC: Node 28526 has dup fanin 28503. |
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| ABC: Node 28527 has dup fanin 28503. |
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| ABC: Node 28528 has dup fanin 28503. |
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| ABC: Node 28535 has dup fanin 28503. |
| ABC: Node 28537 has dup fanin 28536. |
| ABC: Node 28537 has dup fanin 28536. |
| ABC: Node 28538 has dup fanin 28536. |
| ABC: Node 28538 has dup fanin 28536. |
| ABC: Node 28539 has dup fanin 28536. |
| ABC: Node 28539 has dup fanin 28536. |
| ABC: Node 28540 has dup fanin 28536. |
| ABC: Node 28540 has dup fanin 28536. |
| ABC: Node 28541 has dup fanin 28536. |
| ABC: Node 28541 has dup fanin 28536. |
| ABC: Node 28542 has dup fanin 28536. |
| ABC: Node 28542 has dup fanin 28536. |
| ABC: Node 28543 has dup fanin 28536. |
| ABC: Node 28543 has dup fanin 28536. |
| ABC: Node 28544 has dup fanin 28536. |
| ABC: Node 28544 has dup fanin 28536. |
| ABC: Node 28545 has dup fanin 28536. |
| ABC: Node 28545 has dup fanin 28536. |
| ABC: Node 28546 has dup fanin 28536. |
| ABC: Node 28546 has dup fanin 28536. |
| ABC: Node 28547 has dup fanin 28536. |
| ABC: Node 28547 has dup fanin 28536. |
| ABC: Node 28548 has dup fanin 28536. |
| ABC: Node 28548 has dup fanin 28536. |
| ABC: Node 28549 has dup fanin 28536. |
| ABC: Node 28549 has dup fanin 28536. |
| ABC: Node 28550 has dup fanin 28536. |
| ABC: Node 28550 has dup fanin 28536. |
| ABC: Node 28551 has dup fanin 28536. |
| ABC: Node 28551 has dup fanin 28536. |
| ABC: Node 28552 has dup fanin 28536. |
| ABC: Node 28552 has dup fanin 28536. |
| ABC: Node 28553 has dup fanin 28536. |
| ABC: Node 28553 has dup fanin 28536. |
| ABC: Node 28554 has dup fanin 28536. |
| ABC: Node 28554 has dup fanin 28536. |
| ABC: Node 28555 has dup fanin 28536. |
| ABC: Node 28555 has dup fanin 28536. |
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| ABC: Node 28556 has dup fanin 28536. |
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| ABC: Node 28557 has dup fanin 28536. |
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| ABC: Node 28558 has dup fanin 28536. |
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| ABC: Node 28559 has dup fanin 28536. |
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| ABC: Node 28560 has dup fanin 28536. |
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| ABC: Node 28562 has dup fanin 28536. |
| ABC: Node 28563 has dup fanin 28536. |
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| ABC: Node 28564 has dup fanin 28536. |
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| ABC: Node 28565 has dup fanin 28536. |
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| ABC: Node 28568 has dup fanin 28536. |
| ABC: Node 28570 has dup fanin 28569. |
| ABC: Node 28570 has dup fanin 28569. |
| ABC: Node 28571 has dup fanin 28569. |
| ABC: Node 28571 has dup fanin 28569. |
| ABC: Node 28572 has dup fanin 28569. |
| ABC: Node 28572 has dup fanin 28569. |
| ABC: Node 28573 has dup fanin 28569. |
| ABC: Node 28573 has dup fanin 28569. |
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| ABC: Node 28575 has dup fanin 28569. |
| ABC: Node 28575 has dup fanin 28569. |
| ABC: Node 28576 has dup fanin 28569. |
| ABC: Node 28576 has dup fanin 28569. |
| ABC: Node 28577 has dup fanin 28569. |
| ABC: Node 28577 has dup fanin 28569. |
| ABC: Node 28578 has dup fanin 28569. |
| ABC: Node 28578 has dup fanin 28569. |
| ABC: Node 28579 has dup fanin 28569. |
| ABC: Node 28579 has dup fanin 28569. |
| ABC: Node 28580 has dup fanin 28569. |
| ABC: Node 28580 has dup fanin 28569. |
| ABC: Node 28581 has dup fanin 28569. |
| ABC: Node 28581 has dup fanin 28569. |
| ABC: Node 28582 has dup fanin 28569. |
| ABC: Node 28582 has dup fanin 28569. |
| ABC: Node 28583 has dup fanin 28569. |
| ABC: Node 28583 has dup fanin 28569. |
| ABC: Node 28584 has dup fanin 28569. |
| ABC: Node 28584 has dup fanin 28569. |
| ABC: Node 28585 has dup fanin 28569. |
| ABC: Node 28585 has dup fanin 28569. |
| ABC: Node 28586 has dup fanin 28569. |
| ABC: Node 28586 has dup fanin 28569. |
| ABC: Node 28587 has dup fanin 28569. |
| ABC: Node 28587 has dup fanin 28569. |
| ABC: Node 28588 has dup fanin 28569. |
| ABC: Node 28588 has dup fanin 28569. |
| ABC: Node 28589 has dup fanin 28569. |
| ABC: Node 28589 has dup fanin 28569. |
| ABC: Node 28590 has dup fanin 28569. |
| ABC: Node 28590 has dup fanin 28569. |
| ABC: Node 28591 has dup fanin 28569. |
| ABC: Node 28591 has dup fanin 28569. |
| ABC: Node 28592 has dup fanin 28569. |
| ABC: Node 28592 has dup fanin 28569. |
| ABC: Node 28593 has dup fanin 28569. |
| ABC: Node 28593 has dup fanin 28569. |
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| ABC: Node 28595 has dup fanin 28569. |
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| ABC: Node 28596 has dup fanin 28569. |
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| ABC: Node 28597 has dup fanin 28569. |
| ABC: Node 28598 has dup fanin 28569. |
| ABC: Node 28598 has dup fanin 28569. |
| ABC: Node 28599 has dup fanin 28569. |
| ABC: Node 28599 has dup fanin 28569. |
| ABC: Node 28600 has dup fanin 28569. |
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| ABC: Node 28601 has dup fanin 28569. |
| ABC: Node 28601 has dup fanin 28569. |
| ABC: Node 28603 has dup fanin 28602. |
| ABC: Node 28603 has dup fanin 28602. |
| ABC: Node 28604 has dup fanin 28602. |
| ABC: Node 28604 has dup fanin 28602. |
| ABC: Node 28605 has dup fanin 28602. |
| ABC: Node 28605 has dup fanin 28602. |
| ABC: Node 28606 has dup fanin 28602. |
| ABC: Node 28606 has dup fanin 28602. |
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| ABC: Node 28607 has dup fanin 28602. |
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| ABC: Node 28608 has dup fanin 28602. |
| ABC: Node 28609 has dup fanin 28602. |
| ABC: Node 28609 has dup fanin 28602. |
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| ABC: Node 28610 has dup fanin 28602. |
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| ABC: Node 28611 has dup fanin 28602. |
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| ABC: Node 28616 has dup fanin 28602. |
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| ABC: Node 28624 has dup fanin 28602. |
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| ABC: Node 28628 has dup fanin 28602. |
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| ABC: Node 28634 has dup fanin 28602. |
| ABC: Node 28636 has dup fanin 28635. |
| ABC: Node 28636 has dup fanin 28635. |
| ABC: Node 28637 has dup fanin 28635. |
| ABC: Node 28637 has dup fanin 28635. |
| ABC: Node 28638 has dup fanin 28635. |
| ABC: Node 28638 has dup fanin 28635. |
| ABC: Node 28639 has dup fanin 28635. |
| ABC: Node 28639 has dup fanin 28635. |
| ABC: Node 28640 has dup fanin 28635. |
| ABC: Node 28640 has dup fanin 28635. |
| ABC: Node 28641 has dup fanin 28635. |
| ABC: Node 28641 has dup fanin 28635. |
| ABC: Node 28642 has dup fanin 28635. |
| ABC: Node 28642 has dup fanin 28635. |
| ABC: Node 28643 has dup fanin 28635. |
| ABC: Node 28643 has dup fanin 28635. |
| ABC: Node 28644 has dup fanin 28635. |
| ABC: Node 28644 has dup fanin 28635. |
| ABC: Node 28645 has dup fanin 28635. |
| ABC: Node 28645 has dup fanin 28635. |
| ABC: Node 28646 has dup fanin 28635. |
| ABC: Node 28646 has dup fanin 28635. |
| ABC: Node 28647 has dup fanin 28635. |
| ABC: Node 28647 has dup fanin 28635. |
| ABC: Node 28648 has dup fanin 28635. |
| ABC: Node 28648 has dup fanin 28635. |
| ABC: Node 28649 has dup fanin 28635. |
| ABC: Node 28649 has dup fanin 28635. |
| ABC: Node 28650 has dup fanin 28635. |
| ABC: Node 28650 has dup fanin 28635. |
| ABC: Node 28651 has dup fanin 28635. |
| ABC: Node 28651 has dup fanin 28635. |
| ABC: Node 28652 has dup fanin 28635. |
| ABC: Node 28652 has dup fanin 28635. |
| ABC: Node 28653 has dup fanin 28635. |
| ABC: Node 28653 has dup fanin 28635. |
| ABC: Node 28654 has dup fanin 28635. |
| ABC: Node 28654 has dup fanin 28635. |
| ABC: Node 28655 has dup fanin 28635. |
| ABC: Node 28655 has dup fanin 28635. |
| ABC: Node 28656 has dup fanin 28635. |
| ABC: Node 28656 has dup fanin 28635. |
| ABC: Node 28657 has dup fanin 28635. |
| ABC: Node 28657 has dup fanin 28635. |
| ABC: Node 28658 has dup fanin 28635. |
| ABC: Node 28658 has dup fanin 28635. |
| ABC: Node 28659 has dup fanin 28635. |
| ABC: Node 28659 has dup fanin 28635. |
| ABC: Node 28660 has dup fanin 28635. |
| ABC: Node 28660 has dup fanin 28635. |
| ABC: Node 28661 has dup fanin 28635. |
| ABC: Node 28661 has dup fanin 28635. |
| ABC: Node 28662 has dup fanin 28635. |
| ABC: Node 28662 has dup fanin 28635. |
| ABC: Node 28663 has dup fanin 28635. |
| ABC: Node 28663 has dup fanin 28635. |
| ABC: Node 28664 has dup fanin 28635. |
| ABC: Node 28664 has dup fanin 28635. |
| ABC: Node 28665 has dup fanin 28635. |
| ABC: Node 28665 has dup fanin 28635. |
| ABC: Node 28666 has dup fanin 28635. |
| ABC: Node 28666 has dup fanin 28635. |
| ABC: Node 28667 has dup fanin 28635. |
| ABC: Node 28667 has dup fanin 28635. |
| ABC: Node 28669 has dup fanin 28668. |
| ABC: Node 28669 has dup fanin 28668. |
| ABC: Node 28670 has dup fanin 28668. |
| ABC: Node 28670 has dup fanin 28668. |
| ABC: Node 28671 has dup fanin 28668. |
| ABC: Node 28671 has dup fanin 28668. |
| ABC: Node 28672 has dup fanin 28668. |
| ABC: Node 28672 has dup fanin 28668. |
| ABC: Node 28673 has dup fanin 28668. |
| ABC: Node 28673 has dup fanin 28668. |
| ABC: Node 28674 has dup fanin 28668. |
| ABC: Node 28674 has dup fanin 28668. |
| ABC: Node 28675 has dup fanin 28668. |
| ABC: Node 28675 has dup fanin 28668. |
| ABC: Node 28676 has dup fanin 28668. |
| ABC: Node 28676 has dup fanin 28668. |
| ABC: Node 28677 has dup fanin 28668. |
| ABC: Node 28677 has dup fanin 28668. |
| ABC: Node 28678 has dup fanin 28668. |
| ABC: Node 28678 has dup fanin 28668. |
| ABC: Node 28679 has dup fanin 28668. |
| ABC: Node 28679 has dup fanin 28668. |
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| ABC: Node 28680 has dup fanin 28668. |
| ABC: Node 28681 has dup fanin 28668. |
| ABC: Node 28681 has dup fanin 28668. |
| ABC: Node 28682 has dup fanin 28668. |
| ABC: Node 28682 has dup fanin 28668. |
| ABC: Node 28683 has dup fanin 28668. |
| ABC: Node 28683 has dup fanin 28668. |
| ABC: Node 28684 has dup fanin 28668. |
| ABC: Node 28684 has dup fanin 28668. |
| ABC: Node 28685 has dup fanin 28668. |
| ABC: Node 28685 has dup fanin 28668. |
| ABC: Node 28686 has dup fanin 28668. |
| ABC: Node 28686 has dup fanin 28668. |
| ABC: Node 28687 has dup fanin 28668. |
| ABC: Node 28687 has dup fanin 28668. |
| ABC: Node 28688 has dup fanin 28668. |
| ABC: Node 28688 has dup fanin 28668. |
| ABC: Node 28689 has dup fanin 28668. |
| ABC: Node 28689 has dup fanin 28668. |
| ABC: Node 28690 has dup fanin 28668. |
| ABC: Node 28690 has dup fanin 28668. |
| ABC: Node 28691 has dup fanin 28668. |
| ABC: Node 28691 has dup fanin 28668. |
| ABC: Node 28692 has dup fanin 28668. |
| ABC: Node 28692 has dup fanin 28668. |
| ABC: Node 28693 has dup fanin 28668. |
| ABC: Node 28693 has dup fanin 28668. |
| ABC: Node 28694 has dup fanin 28668. |
| ABC: Node 28694 has dup fanin 28668. |
| ABC: Node 28695 has dup fanin 28668. |
| ABC: Node 28695 has dup fanin 28668. |
| ABC: Node 28696 has dup fanin 28668. |
| ABC: Node 28696 has dup fanin 28668. |
| ABC: Node 28697 has dup fanin 28668. |
| ABC: Node 28697 has dup fanin 28668. |
| ABC: Node 28698 has dup fanin 28668. |
| ABC: Node 28698 has dup fanin 28668. |
| ABC: Node 28699 has dup fanin 28668. |
| ABC: Node 28699 has dup fanin 28668. |
| ABC: Node 28700 has dup fanin 28668. |
| ABC: Node 28700 has dup fanin 28668. |
| ABC: Node 28702 has dup fanin 28701. |
| ABC: Node 28702 has dup fanin 28701. |
| ABC: Node 28703 has dup fanin 28701. |
| ABC: Node 28703 has dup fanin 28701. |
| ABC: Node 28704 has dup fanin 28701. |
| ABC: Node 28704 has dup fanin 28701. |
| ABC: Node 28705 has dup fanin 28701. |
| ABC: Node 28705 has dup fanin 28701. |
| ABC: Node 28706 has dup fanin 28701. |
| ABC: Node 28706 has dup fanin 28701. |
| ABC: Node 28707 has dup fanin 28701. |
| ABC: Node 28707 has dup fanin 28701. |
| ABC: Node 28708 has dup fanin 28701. |
| ABC: Node 28708 has dup fanin 28701. |
| ABC: Node 28709 has dup fanin 28701. |
| ABC: Node 28709 has dup fanin 28701. |
| ABC: Node 28710 has dup fanin 28701. |
| ABC: Node 28710 has dup fanin 28701. |
| ABC: Node 28711 has dup fanin 28701. |
| ABC: Node 28711 has dup fanin 28701. |
| ABC: Node 28712 has dup fanin 28701. |
| ABC: Node 28712 has dup fanin 28701. |
| ABC: Node 28713 has dup fanin 28701. |
| ABC: Node 28713 has dup fanin 28701. |
| ABC: Node 28714 has dup fanin 28701. |
| ABC: Node 28714 has dup fanin 28701. |
| ABC: Node 28715 has dup fanin 28701. |
| ABC: Node 28715 has dup fanin 28701. |
| ABC: Node 28716 has dup fanin 28701. |
| ABC: Node 28716 has dup fanin 28701. |
| ABC: Node 28717 has dup fanin 28701. |
| ABC: Node 28717 has dup fanin 28701. |
| ABC: Node 28718 has dup fanin 28701. |
| ABC: Node 28718 has dup fanin 28701. |
| ABC: Node 28719 has dup fanin 28701. |
| ABC: Node 28719 has dup fanin 28701. |
| ABC: Node 28720 has dup fanin 28701. |
| ABC: Node 28720 has dup fanin 28701. |
| ABC: Node 28721 has dup fanin 28701. |
| ABC: Node 28721 has dup fanin 28701. |
| ABC: Node 28722 has dup fanin 28701. |
| ABC: Node 28722 has dup fanin 28701. |
| ABC: Node 28723 has dup fanin 28701. |
| ABC: Node 28723 has dup fanin 28701. |
| ABC: Node 28724 has dup fanin 28701. |
| ABC: Node 28724 has dup fanin 28701. |
| ABC: Node 28725 has dup fanin 28701. |
| ABC: Node 28725 has dup fanin 28701. |
| ABC: Node 28726 has dup fanin 28701. |
| ABC: Node 28726 has dup fanin 28701. |
| ABC: Node 28727 has dup fanin 28701. |
| ABC: Node 28727 has dup fanin 28701. |
| ABC: Node 28728 has dup fanin 28701. |
| ABC: Node 28728 has dup fanin 28701. |
| ABC: Node 28729 has dup fanin 28701. |
| ABC: Node 28729 has dup fanin 28701. |
| ABC: Node 28730 has dup fanin 28701. |
| ABC: Node 28730 has dup fanin 28701. |
| ABC: Node 28731 has dup fanin 28701. |
| ABC: Node 28731 has dup fanin 28701. |
| ABC: Node 28732 has dup fanin 28701. |
| ABC: Node 28732 has dup fanin 28701. |
| ABC: Node 28733 has dup fanin 28701. |
| ABC: Node 28733 has dup fanin 28701. |
| ABC: Node 28735 has dup fanin 28734. |
| ABC: Node 28735 has dup fanin 28734. |
| ABC: Node 28736 has dup fanin 28734. |
| ABC: Node 28736 has dup fanin 28734. |
| ABC: Node 28737 has dup fanin 28734. |
| ABC: Node 28737 has dup fanin 28734. |
| ABC: Node 28738 has dup fanin 28734. |
| ABC: Node 28738 has dup fanin 28734. |
| ABC: Node 28739 has dup fanin 28734. |
| ABC: Node 28739 has dup fanin 28734. |
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| ABC: Node 28740 has dup fanin 28734. |
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| ABC: Node 28741 has dup fanin 28734. |
| ABC: Node 28742 has dup fanin 28734. |
| ABC: Node 28742 has dup fanin 28734. |
| ABC: Node 28743 has dup fanin 28734. |
| ABC: Node 28743 has dup fanin 28734. |
| ABC: Node 28744 has dup fanin 28734. |
| ABC: Node 28744 has dup fanin 28734. |
| ABC: Node 28745 has dup fanin 28734. |
| ABC: Node 28745 has dup fanin 28734. |
| ABC: Node 28746 has dup fanin 28734. |
| ABC: Node 28746 has dup fanin 28734. |
| ABC: Node 28747 has dup fanin 28734. |
| ABC: Node 28747 has dup fanin 28734. |
| ABC: Node 28748 has dup fanin 28734. |
| ABC: Node 28748 has dup fanin 28734. |
| ABC: Node 28749 has dup fanin 28734. |
| ABC: Node 28749 has dup fanin 28734. |
| ABC: Node 28750 has dup fanin 28734. |
| ABC: Node 28750 has dup fanin 28734. |
| ABC: Node 28751 has dup fanin 28734. |
| ABC: Node 28751 has dup fanin 28734. |
| ABC: Node 28752 has dup fanin 28734. |
| ABC: Node 28752 has dup fanin 28734. |
| ABC: Node 28753 has dup fanin 28734. |
| ABC: Node 28753 has dup fanin 28734. |
| ABC: Node 28754 has dup fanin 28734. |
| ABC: Node 28754 has dup fanin 28734. |
| ABC: Node 28755 has dup fanin 28734. |
| ABC: Node 28755 has dup fanin 28734. |
| ABC: Node 28756 has dup fanin 28734. |
| ABC: Node 28756 has dup fanin 28734. |
| ABC: Node 28757 has dup fanin 28734. |
| ABC: Node 28757 has dup fanin 28734. |
| ABC: Node 28758 has dup fanin 28734. |
| ABC: Node 28758 has dup fanin 28734. |
| ABC: Node 28759 has dup fanin 28734. |
| ABC: Node 28759 has dup fanin 28734. |
| ABC: Node 28760 has dup fanin 28734. |
| ABC: Node 28760 has dup fanin 28734. |
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| ABC: Node 28761 has dup fanin 28734. |
| ABC: Node 28762 has dup fanin 28734. |
| ABC: Node 28762 has dup fanin 28734. |
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| ABC: Node 28763 has dup fanin 28734. |
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| ABC: Node 28764 has dup fanin 28734. |
| ABC: Node 28765 has dup fanin 28734. |
| ABC: Node 28765 has dup fanin 28734. |
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| ABC: Node 28769 has dup fanin 28767. |
| ABC: Node 28770 has dup fanin 28767. |
| ABC: Node 28770 has dup fanin 28767. |
| ABC: Node 28771 has dup fanin 28767. |
| ABC: Node 28771 has dup fanin 28767. |
| ABC: Node 28772 has dup fanin 28767. |
| ABC: Node 28772 has dup fanin 28767. |
| ABC: Node 28773 has dup fanin 28767. |
| ABC: Node 28773 has dup fanin 28767. |
| ABC: Node 28774 has dup fanin 28767. |
| ABC: Node 28774 has dup fanin 28767. |
| ABC: Node 28775 has dup fanin 28767. |
| ABC: Node 28775 has dup fanin 28767. |
| ABC: Node 28776 has dup fanin 28767. |
| ABC: Node 28776 has dup fanin 28767. |
| ABC: Node 28777 has dup fanin 28767. |
| ABC: Node 28777 has dup fanin 28767. |
| ABC: Node 28778 has dup fanin 28767. |
| ABC: Node 28778 has dup fanin 28767. |
| ABC: Node 28779 has dup fanin 28767. |
| ABC: Node 28779 has dup fanin 28767. |
| ABC: Node 28780 has dup fanin 28767. |
| ABC: Node 28780 has dup fanin 28767. |
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| ABC: Node 28781 has dup fanin 28767. |
| ABC: Node 28782 has dup fanin 28767. |
| ABC: Node 28782 has dup fanin 28767. |
| ABC: Node 28783 has dup fanin 28767. |
| ABC: Node 28783 has dup fanin 28767. |
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| ABC: Node 28784 has dup fanin 28767. |
| ABC: Node 28785 has dup fanin 28767. |
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| ABC: Node 28786 has dup fanin 28767. |
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| ABC: Node 28787 has dup fanin 28767. |
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| ABC: Node 28788 has dup fanin 28767. |
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| ABC: Node 28789 has dup fanin 28767. |
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| ABC: Node 28790 has dup fanin 28767. |
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| ABC: Node 28791 has dup fanin 28767. |
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| ABC: Node 28800 has dup fanin 28768. |
| ABC: Node 28801 has dup fanin 28768. |
| ABC: Node 28801 has dup fanin 28768. |
| ABC: Node 28803 has dup fanin 28802. |
| ABC: Node 28803 has dup fanin 28802. |
| ABC: Node 28804 has dup fanin 28802. |
| ABC: Node 28804 has dup fanin 28802. |
| ABC: Node 28805 has dup fanin 28802. |
| ABC: Node 28805 has dup fanin 28802. |
| ABC: Node 28806 has dup fanin 28802. |
| ABC: Node 28806 has dup fanin 28802. |
| ABC: Node 28807 has dup fanin 28802. |
| ABC: Node 28807 has dup fanin 28802. |
| ABC: Node 28808 has dup fanin 28802. |
| ABC: Node 28808 has dup fanin 28802. |
| ABC: Node 28809 has dup fanin 28802. |
| ABC: Node 28809 has dup fanin 28802. |
| ABC: Node 28810 has dup fanin 28802. |
| ABC: Node 28810 has dup fanin 28802. |
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| ABC: Node 28811 has dup fanin 28802. |
| ABC: Node 28812 has dup fanin 28802. |
| ABC: Node 28812 has dup fanin 28802. |
| ABC: Node 28813 has dup fanin 28802. |
| ABC: Node 28813 has dup fanin 28802. |
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| ABC: Node 28814 has dup fanin 28802. |
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| ABC: Node 28815 has dup fanin 28802. |
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| ABC: Node 28816 has dup fanin 28802. |
| ABC: Node 28817 has dup fanin 28802. |
| ABC: Node 28817 has dup fanin 28802. |
| ABC: Node 28818 has dup fanin 28802. |
| ABC: Node 28818 has dup fanin 28802. |
| ABC: Node 28819 has dup fanin 28802. |
| ABC: Node 28819 has dup fanin 28802. |
| ABC: Node 28820 has dup fanin 28802. |
| ABC: Node 28820 has dup fanin 28802. |
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| ABC: Node 28821 has dup fanin 28802. |
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| ABC: Node 28822 has dup fanin 28802. |
| ABC: Node 28823 has dup fanin 28802. |
| ABC: Node 28823 has dup fanin 28802. |
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| ABC: Node 28824 has dup fanin 28802. |
| ABC: Node 28825 has dup fanin 28802. |
| ABC: Node 28825 has dup fanin 28802. |
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| ABC: Node 28826 has dup fanin 28802. |
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| ABC: Node 28827 has dup fanin 28802. |
| ABC: Node 28828 has dup fanin 28802. |
| ABC: Node 28828 has dup fanin 28802. |
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| ABC: Node 28829 has dup fanin 28802. |
| ABC: Node 28830 has dup fanin 28802. |
| ABC: Node 28830 has dup fanin 28802. |
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| ABC: Node 28831 has dup fanin 28802. |
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| ABC: Node 28832 has dup fanin 28802. |
| ABC: Node 28833 has dup fanin 28802. |
| ABC: Node 28833 has dup fanin 28802. |
| ABC: Node 28834 has dup fanin 28802. |
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| ABC: Node 28836 has dup fanin 28835. |
| ABC: Node 28837 has dup fanin 28835. |
| ABC: Node 28837 has dup fanin 28835. |
| ABC: Node 28838 has dup fanin 28835. |
| ABC: Node 28838 has dup fanin 28835. |
| ABC: Node 28839 has dup fanin 28835. |
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| ABC: Node 28841 has dup fanin 28835. |
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| ABC: Node 28842 has dup fanin 28835. |
| ABC: Node 28842 has dup fanin 28835. |
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| ABC: Node 28843 has dup fanin 28835. |
| ABC: Node 28844 has dup fanin 28835. |
| ABC: Node 28844 has dup fanin 28835. |
| ABC: Node 28845 has dup fanin 28835. |
| ABC: Node 28845 has dup fanin 28835. |
| ABC: Node 28846 has dup fanin 28835. |
| ABC: Node 28846 has dup fanin 28835. |
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| ABC: Node 28847 has dup fanin 28835. |
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| ABC: Node 28848 has dup fanin 28835. |
| ABC: Node 28849 has dup fanin 28835. |
| ABC: Node 28849 has dup fanin 28835. |
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| ABC: Node 28850 has dup fanin 28835. |
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| ABC: Node 28851 has dup fanin 28835. |
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| ABC: Node 28853 has dup fanin 28835. |
| ABC: Node 28853 has dup fanin 28835. |
| ABC: Node 28854 has dup fanin 28835. |
| ABC: Node 28854 has dup fanin 28835. |
| ABC: Node 28855 has dup fanin 28835. |
| ABC: Node 28855 has dup fanin 28835. |
| ABC: Node 28856 has dup fanin 28835. |
| ABC: Node 28856 has dup fanin 28835. |
| ABC: Node 28857 has dup fanin 28835. |
| ABC: Node 28857 has dup fanin 28835. |
| ABC: Node 28858 has dup fanin 28835. |
| ABC: Node 28858 has dup fanin 28835. |
| ABC: Node 28859 has dup fanin 28835. |
| ABC: Node 28859 has dup fanin 28835. |
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| ABC: Node 28860 has dup fanin 28835. |
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| ABC: Node 28861 has dup fanin 28835. |
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| ABC: Node 28862 has dup fanin 28835. |
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| ABC: Node 28864 has dup fanin 28835. |
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| ABC: Node 28871 has dup fanin 28868. |
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| ABC: Node 28876 has dup fanin 28868. |
| ABC: Node 28877 has dup fanin 28868. |
| ABC: Node 28877 has dup fanin 28868. |
| ABC: Node 28878 has dup fanin 28868. |
| ABC: Node 28878 has dup fanin 28868. |
| ABC: Node 28879 has dup fanin 28868. |
| ABC: Node 28879 has dup fanin 28868. |
| ABC: Node 28880 has dup fanin 28868. |
| ABC: Node 28880 has dup fanin 28868. |
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| ABC: Node 28881 has dup fanin 28868. |
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| ABC: Node 28882 has dup fanin 28868. |
| ABC: Node 28883 has dup fanin 28868. |
| ABC: Node 28883 has dup fanin 28868. |
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| ABC: Node 28884 has dup fanin 28868. |
| ABC: Node 28885 has dup fanin 28868. |
| ABC: Node 28885 has dup fanin 28868. |
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| ABC: Node 28886 has dup fanin 28868. |
| ABC: Node 28887 has dup fanin 28868. |
| ABC: Node 28887 has dup fanin 28868. |
| ABC: Node 28888 has dup fanin 28868. |
| ABC: Node 28888 has dup fanin 28868. |
| ABC: Node 28889 has dup fanin 28868. |
| ABC: Node 28889 has dup fanin 28868. |
| ABC: Node 28890 has dup fanin 28868. |
| ABC: Node 28890 has dup fanin 28868. |
| ABC: Node 28891 has dup fanin 28868. |
| ABC: Node 28891 has dup fanin 28868. |
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| ABC: Node 28892 has dup fanin 28868. |
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| ABC: Node 28893 has dup fanin 28868. |
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| ABC: Node 28894 has dup fanin 28868. |
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| ABC: Node 28895 has dup fanin 28868. |
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| ABC: Node 28896 has dup fanin 28868. |
| ABC: Node 28897 has dup fanin 28868. |
| ABC: Node 28897 has dup fanin 28868. |
| ABC: Node 28898 has dup fanin 28868. |
| ABC: Node 28898 has dup fanin 28868. |
| ABC: Node 28899 has dup fanin 28868. |
| ABC: Node 28899 has dup fanin 28868. |
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| ABC: + upsize -D 50000 |
| ABC: Current delay (12524.61 ps) does not exceed the target delay (50000.00 ps). Upsizing is not performed. |
| ABC: + dnsize -D 50000 |
| ABC: + stime -p |
| ABC: WireLoad = "none" Gates = 31032 ( 39.5 %) Cap = 9.4 ff ( 0.0 %) Area = 309260.34 (100.0 %) Delay = 12524.61 ps ( 0.2 %) |
| ABC: Path 0 -- 3968 : 0 3 pi A = 0.00 Df = 12.0 -8.1 ps S = 25.0 ps Cin = 0.0 ff Cout = 9.6 ff Cmax = 0.0 ff G = 0 |
| ABC: Path 1 -- 24928 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df = 149.3 -1.3 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 2 -- 24929 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df = 303.9 -9.6 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 3 -- 24930 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df = 459.7 -20.5 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 4 -- 24931 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df = 615.4 -31.3 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 5 -- 24932 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df = 771.2 -42.1 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 6 -- 24933 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df = 927.0 -52.9 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 7 -- 24934 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =1082.7 -63.7 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 8 -- 24935 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =1238.5 -74.6 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 9 -- 24936 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =1394.3 -85.4 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 10 -- 24937 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =1550.0 -96.2 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 11 -- 24938 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =1705.8 -107.0 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 12 -- 24939 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =1861.6 -117.8 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 13 -- 24940 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =2017.3 -128.7 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 14 -- 24941 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =2173.1 -139.5 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 15 -- 24942 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =2328.9 -150.3 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 16 -- 24943 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =2484.6 -161.1 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 17 -- 24944 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =2640.4 -171.9 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 18 -- 24945 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =2796.1 -182.8 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 19 -- 24946 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =2951.9 -193.6 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 20 -- 24947 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =3107.7 -204.4 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 21 -- 24948 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =3263.4 -215.2 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 22 -- 24949 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =3419.2 -226.0 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 23 -- 24950 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =3575.0 -236.9 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 24 -- 24951 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =3730.7 -247.7 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 25 -- 24952 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =3886.5 -258.5 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 26 -- 24953 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =4042.3 -269.3 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 27 -- 24954 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =4198.0 -280.1 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 28 -- 24955 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =4353.8 -291.0 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 29 -- 24956 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =4509.6 -301.8 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 30 -- 24957 : 2 3 sky130_fd_sc_hd__and2_4 A = 8.76 Df =4665.3 -312.6 ps S = 50.2 ps Cin = 2.4 ff Cout = 9.7 ff Cmax = 539.3 ff G = 389 |
| ABC: Path 31 -- 24958 : 2 2 sky130_fd_sc_hd__and2_4 A = 8.76 Df =4817.0 -325.7 ps S = 43.6 ps Cin = 2.4 ff Cout = 7.2 ff Cmax = 539.3 ff G = 287 |
| ABC: Path 32 -- 24959 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =4859.6 -338.5 ps S = 31.1 ps Cin = 4.5 ff Cout = 5.0 ff Cmax = 331.4 ff G = 106 |
| ABC: Path 33 -- 24960 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =4979.1 -223.0 ps S = 60.4 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 34 -- 24961 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =5108.7 -103.6 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 35 -- 24962 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =5253.9 -15.6 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 36 -- 24963 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =5502.7 -134.9 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 37 -- 24964 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =5751.6 -254.1 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 38 -- 24965 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =6000.4 -373.4 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 39 -- 24966 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =6249.2 -492.6 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 40 -- 24967 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =6498.0 -611.9 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 41 -- 24968 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =6746.8 -731.1 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 42 -- 24969 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =6995.6 -850.4 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 43 -- 24970 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =7244.4 -969.6 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 44 -- 24971 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =7493.3-1088.9 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 45 -- 24972 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =7742.1-1208.1 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 46 -- 24973 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =7990.9-1327.3 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 47 -- 24974 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =8239.7-1446.6 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 48 -- 24975 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =8488.5-1565.8 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 49 -- 24976 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =8737.3-1685.1 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 50 -- 24977 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =8986.1-1804.3 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 51 -- 24978 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =9235.0-1923.6 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 52 -- 24979 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =9483.8-2042.8 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 53 -- 24980 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =9732.6-2162.1 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 54 -- 24981 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =9981.4-2281.3 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 55 -- 24982 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =10230.2-2400.5 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 56 -- 24983 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =10479.0-2519.8 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 57 -- 24984 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =10727.8-2639.0 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 58 -- 24985 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =10976.7-2758.3 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 59 -- 24986 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =11225.5-2877.5 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 60 -- 24987 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =11474.3-2996.8 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 61 -- 24988 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =11723.1-3116.0 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 62 -- 24989 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =11971.9-3235.3 ps S = 60.0 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 514.5 ff G = 568 |
| ABC: Path 63 -- 24990 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =12226.2-3354.1 ps S = 65.7 ps Cin = 2.4 ff Cout = 16.9 ff Cmax = 514.5 ff G = 672 |
| ABC: Path 64 -- 24992 : 3 1 sky130_fd_sc_hd__o21a_4 A = 15.01 Df =12524.6 -78.3 ps S = 69.6 ps Cin = 4.6 ff Cout = 17.6 ff Cmax = 510.0 ff G = 383 |
| ABC: Start-point = pi3967 (\soc.cpu.picorv32_core.count_cycle [1]). End-point = po1837 ($auto$rtlil.cc:2290:MuxGate$92515). |
| ABC: + print_stats -m |
| ABC: netlist : i/o = 4387/ 4051 lat = 0 nd = 31032 edge = 69653 area =309221.49 delay =75.00 lev = 75 |
| ABC: + write_blif /tmp/yosys-abc-sDrnpm/output.blif |
| |
| 19.1.2. Re-integrating ABC results. |
| ABC RESULTS: sky130_fd_sc_hd__a2111o_4 cells: 11 |
| ABC RESULTS: sky130_fd_sc_hd__a211o_4 cells: 1742 |
| ABC RESULTS: sky130_fd_sc_hd__a21bo_4 cells: 67 |
| ABC RESULTS: sky130_fd_sc_hd__a21o_4 cells: 134 |
| ABC RESULTS: sky130_fd_sc_hd__a21oi_4 cells: 143 |
| ABC RESULTS: sky130_fd_sc_hd__a22oi_4 cells: 169 |
| ABC RESULTS: sky130_fd_sc_hd__a2bb2o_4 cells: 2113 |
| ABC RESULTS: sky130_fd_sc_hd__a32o_4 cells: 711 |
| ABC RESULTS: sky130_fd_sc_hd__a41o_4 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__and2_4 cells: 1499 |
| ABC RESULTS: sky130_fd_sc_hd__and3_4 cells: 1910 |
| ABC RESULTS: sky130_fd_sc_hd__and4_4 cells: 138 |
| ABC RESULTS: sky130_fd_sc_hd__buf_2 cells: 8204 |
| ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 4040 |
| ABC RESULTS: sky130_fd_sc_hd__nand2_4 cells: 323 |
| ABC RESULTS: sky130_fd_sc_hd__nor2_4 cells: 986 |
| ABC RESULTS: sky130_fd_sc_hd__o21a_4 cells: 918 |
| ABC RESULTS: sky130_fd_sc_hd__o21ai_4 cells: 149 |
| ABC RESULTS: sky130_fd_sc_hd__o22a_4 cells: 1814 |
| ABC RESULTS: sky130_fd_sc_hd__o32a_4 cells: 60 |
| ABC RESULTS: sky130_fd_sc_hd__o41a_4 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__or2_4 cells: 4373 |
| ABC RESULTS: sky130_fd_sc_hd__or3_4 cells: 849 |
| ABC RESULTS: sky130_fd_sc_hd__or4_4 cells: 672 |
| ABC RESULTS: internal signals: 21215 |
| ABC RESULTS: input signals: 4387 |
| ABC RESULTS: output signals: 4051 |
| Removing temp directory. |
| |
| 20. Executing SETUNDEF pass (replace undef values with defined constants). |
| |
| 21. Executing HILOMAP pass (mapping to constant drivers). |
| |
| 22. Executing SPLITNETS pass (splitting up multi-bit signals). |
| |
| 23. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \mgmt_core.. |
| Removed 269 unused cells and 30961 unused wires. |
| <suppressed ~1317 debug messages> |
| |
| 24. Executing INSBUF pass (insert buffer cells for connected wires). |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130613: \flash_clk_oeb -> \flash_csb_oeb |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130614: \mgmt_wen [1] -> \mgmt_wen [0] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130615: \mgmt_wen_mask [4] -> \mgmt_wen_mask [0] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130616: \mgmt_wen_mask [5] -> \mgmt_wen_mask [1] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130617: \mgmt_wen_mask [6] -> \mgmt_wen_mask [2] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130618: \mgmt_wen_mask [7] -> \mgmt_wen_mask [3] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130619: \mgmt_addr [2] -> \mprj_adr_o [2] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130620: \mgmt_addr [3] -> \mprj_adr_o [3] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130621: \mgmt_addr [4] -> \mprj_adr_o [4] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130622: \mgmt_addr [5] -> \mprj_adr_o [5] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130623: \mgmt_addr [6] -> \mprj_adr_o [6] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130624: \mgmt_addr [7] -> \mprj_adr_o [7] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130625: \mgmt_wdata [0] -> \mprj_dat_o [0] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130626: \mgmt_wdata [1] -> \mprj_dat_o [1] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130627: \mgmt_wdata [2] -> \mprj_dat_o [2] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130628: \mgmt_wdata [3] -> \mprj_dat_o [3] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130629: \mgmt_wdata [4] -> \mprj_dat_o [4] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130630: \mgmt_wdata [5] -> \mprj_dat_o [5] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130631: \mgmt_wdata [6] -> \mprj_dat_o [6] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130632: \mgmt_wdata [7] -> \mprj_dat_o [7] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130633: \mgmt_wdata [8] -> \mprj_dat_o [8] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130634: \mgmt_wdata [9] -> \mprj_dat_o [9] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130635: \mgmt_wdata [10] -> \mprj_dat_o [10] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130636: \mgmt_wdata [11] -> \mprj_dat_o [11] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130637: \mgmt_wdata [12] -> \mprj_dat_o [12] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130638: \mgmt_wdata [13] -> \mprj_dat_o [13] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130639: \mgmt_wdata [14] -> \mprj_dat_o [14] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130640: \mgmt_wdata [15] -> \mprj_dat_o [15] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130641: \mgmt_wdata [16] -> \mprj_dat_o [16] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130642: \mgmt_wdata [17] -> \mprj_dat_o [17] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130643: \mgmt_wdata [18] -> \mprj_dat_o [18] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130644: \mgmt_wdata [19] -> \mprj_dat_o [19] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130645: \mgmt_wdata [20] -> \mprj_dat_o [20] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130646: \mgmt_wdata [21] -> \mprj_dat_o [21] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130647: \mgmt_wdata [22] -> \mprj_dat_o [22] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130648: \mgmt_wdata [23] -> \mprj_dat_o [23] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130649: \mgmt_wdata [24] -> \mprj_dat_o [24] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130650: \mgmt_wdata [25] -> \mprj_dat_o [25] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130651: \mgmt_wdata [26] -> \mprj_dat_o [26] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130652: \mgmt_wdata [27] -> \mprj_dat_o [27] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130653: \mgmt_wdata [28] -> \mprj_dat_o [28] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130654: \mgmt_wdata [29] -> \mprj_dat_o [29] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130655: \mgmt_wdata [30] -> \mprj_dat_o [30] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130656: \mgmt_wdata [31] -> \mprj_dat_o [31] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130657: \mgmt_addr [2] -> \user_addr [2] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130658: \mgmt_addr [3] -> \user_addr [3] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130659: \mgmt_addr [4] -> \user_addr [4] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130660: \mgmt_addr [5] -> \user_addr [5] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130661: \mgmt_addr [6] -> \user_addr [6] |
| Added mgmt_core.$auto$insbuf.cc:79:execute$130662: \mgmt_addr [7] -> \user_addr [7] |
| |
| 25. Executing CHECK pass (checking for obvious problems). |
| checking module mgmt_core.. |
| Warning: Wire mgmt_core.\user_ena [5] is used but has no driver. |
| Warning: Wire mgmt_core.\user_ena [4] is used but has no driver. |
| Warning: Wire mgmt_core.\user_ena [3] is used but has no driver. |
| Warning: Wire mgmt_core.\user_ena [2] is used but has no driver. |
| Warning: Wire mgmt_core.\user_ena [1] is used but has no driver. |
| Warning: Wire mgmt_core.\user_ena [0] is used but has no driver. |
| Warning: Wire mgmt_core.\user_clk is used but has no driver. |
| Warning: Wire mgmt_core.\user_addr [7] is used but has no driver. |
| Warning: Wire mgmt_core.\user_addr [6] is used but has no driver. |
| Warning: Wire mgmt_core.\user_addr [5] is used but has no driver. |
| Warning: Wire mgmt_core.\user_addr [4] is used but has no driver. |
| Warning: Wire mgmt_core.\user_addr [3] is used but has no driver. |
| Warning: Wire mgmt_core.\user_addr [2] is used but has no driver. |
| Warning: Wire mgmt_core.\user_addr [1] is used but has no driver. |
| Warning: Wire mgmt_core.\user_addr [0] is used but has no driver. |
| Warning: Wire mgmt_core.\sdo_outenb is used but has no driver. |
| Warning: Wire mgmt_core.\sdo_out is used but has no driver. |
| Warning: Wire mgmt_core.\pwr_ctrl_out [3] is used but has no driver. |
| Warning: Wire mgmt_core.\pwr_ctrl_out [2] is used but has no driver. |
| Warning: Wire mgmt_core.\pwr_ctrl_out [1] is used but has no driver. |
| Warning: Wire mgmt_core.\pwr_ctrl_out [0] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_we_o is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_stb_o is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_sel_o [3] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_sel_o [2] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_sel_o [1] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_sel_o [0] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_io_loader_resetn is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_io_loader_data is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_io_loader_clock is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [31] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [30] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [29] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [28] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [27] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [26] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [25] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [24] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [23] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [22] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [21] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [20] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [19] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [18] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [17] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [16] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [15] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [14] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [13] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [12] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [11] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [10] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [9] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [8] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [7] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [6] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [5] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [4] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [3] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [2] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [1] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_dat_o [0] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_cyc_o is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [31] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [30] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [29] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [28] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [27] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [26] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [25] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [24] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [23] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [22] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [21] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [20] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [19] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [18] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [17] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [16] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [15] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [14] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [13] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [12] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [11] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [10] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [7] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [6] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [5] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [4] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [3] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [2] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [1] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [0] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wen_mask [7] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wen_mask [6] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wen_mask [5] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wen_mask [4] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wen_mask [3] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wen_mask [2] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wen_mask [1] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wen_mask [0] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wen [1] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wen [0] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [37] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [36] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [35] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [34] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [33] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [32] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [31] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [30] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [29] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [28] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [27] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [26] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [25] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [24] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [23] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [22] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [21] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [20] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [19] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [18] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [17] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [16] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [15] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [14] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [13] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [12] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [11] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [10] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [9] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [8] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [7] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [6] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [5] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [4] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [3] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [2] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [1] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_out_data [0] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_ena [1] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_ena [0] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_addr [1] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_addr [0] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [127] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [126] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [125] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [124] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [123] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [122] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [121] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [120] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [119] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [118] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [117] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [116] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [115] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [114] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [113] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [112] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [111] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [110] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [109] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [108] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [107] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [106] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [105] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [104] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [103] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [102] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [101] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [100] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [99] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [98] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [97] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [96] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [95] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [94] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [93] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [92] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [91] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [90] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [89] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [88] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [87] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [86] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [85] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [84] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [83] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [82] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [81] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [80] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [79] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [78] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [77] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [76] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [75] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [74] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [73] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [72] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [71] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [70] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [69] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [68] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [67] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [66] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [65] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [64] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [63] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [62] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [61] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [60] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [59] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [58] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [57] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [56] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [55] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [54] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [53] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [52] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [51] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [50] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [49] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [48] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [47] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [46] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [45] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [44] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [43] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [42] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [41] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [40] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [39] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [38] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [37] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [36] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [35] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [34] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [33] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [32] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [31] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [30] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [29] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [28] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [27] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [26] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [25] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [24] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [23] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [22] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [21] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [20] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [19] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [18] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [17] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [16] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [15] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [14] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [13] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [12] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [11] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [10] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [9] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [8] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [7] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [6] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [5] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [4] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [3] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [2] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [1] is used but has no driver. |
| Warning: Wire mgmt_core.\la_output [0] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [127] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [126] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [125] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [124] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [123] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [122] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [121] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [120] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [119] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [118] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [117] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [116] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [115] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [114] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [113] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [112] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [111] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [110] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [109] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [108] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [107] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [106] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [105] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [104] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [103] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [102] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [101] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [100] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [99] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [98] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [97] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [96] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [95] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [94] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [93] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [92] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [91] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [90] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [89] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [88] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [87] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [86] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [85] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [84] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [83] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [82] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [81] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [80] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [79] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [78] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [77] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [76] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [75] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [74] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [73] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [72] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [71] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [70] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [69] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [68] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [67] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [66] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [65] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [64] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [63] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [62] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [61] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [60] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [59] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [58] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [57] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [56] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [55] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [54] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [53] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [52] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [51] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [50] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [49] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [48] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [47] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [46] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [45] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [44] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [43] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [42] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [41] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [40] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [39] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [38] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [37] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [36] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [35] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [34] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [33] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [32] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [31] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [30] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [29] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [28] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [27] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [26] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [25] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [24] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [23] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [22] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [21] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [20] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [19] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [18] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [17] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [16] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [15] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [14] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [13] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [12] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [11] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [10] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [9] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [8] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [7] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [6] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [5] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [4] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [3] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [2] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [1] is used but has no driver. |
| Warning: Wire mgmt_core.\la_oen [0] is used but has no driver. |
| Warning: Wire mgmt_core.\jtag_outenb is used but has no driver. |
| Warning: Wire mgmt_core.\jtag_out is used but has no driver. |
| Warning: Wire mgmt_core.\gpio_outenb_pad is used but has no driver. |
| Warning: Wire mgmt_core.\gpio_out_pad is used but has no driver. |
| Warning: Wire mgmt_core.\gpio_mode1_pad is used but has no driver. |
| Warning: Wire mgmt_core.\gpio_mode0_pad is used but has no driver. |
| Warning: Wire mgmt_core.\gpio_inenb_pad is used but has no driver. |
| Warning: Wire mgmt_core.\flash_io1_oeb is used but has no driver. |
| Warning: Wire mgmt_core.\flash_io1_ieb is used but has no driver. |
| Warning: Wire mgmt_core.\flash_io1_do is used but has no driver. |
| Warning: Wire mgmt_core.\flash_io0_oeb is used but has no driver. |
| Warning: Wire mgmt_core.\flash_io0_ieb is used but has no driver. |
| Warning: Wire mgmt_core.\flash_io0_do is used but has no driver. |
| Warning: Wire mgmt_core.\flash_csb_oeb is used but has no driver. |
| Warning: Wire mgmt_core.\flash_csb_ieb is used but has no driver. |
| Warning: Wire mgmt_core.\flash_csb is used but has no driver. |
| Warning: Wire mgmt_core.\flash_clk_oeb is used but has no driver. |
| Warning: Wire mgmt_core.\flash_clk_ieb is used but has no driver. |
| Warning: Wire mgmt_core.\flash_clk is used but has no driver. |
| Warning: Wire mgmt_core.\core_rstn is used but has no driver. |
| Warning: Wire mgmt_core.\soc.soc_mem.mem.wen[3] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.soc_mem.mem.wen[2] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.soc_mem.mem.wen[1] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.soc_mem.mem.wen[0] is used but has no driver. |
| Warning: Wire mgmt_core.\soc.soc_mem.mem.ena is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [31] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [30] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [29] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [28] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [27] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [26] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [25] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [24] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [23] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [22] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [21] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [20] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [19] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [18] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [17] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [16] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [15] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [14] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [13] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [12] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [11] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [10] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [9] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [8] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [7] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [6] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [5] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [4] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [3] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [2] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [1] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_wdata [0] is used but has no driver. |
| Warning: Wire mgmt_core.\core_clk is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [9] is used but has no driver. |
| Warning: Wire mgmt_core.\mprj_adr_o [8] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_addr [7] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_addr [6] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_addr [5] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_addr [4] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_addr [3] is used but has no driver. |
| Warning: Wire mgmt_core.\mgmt_addr [2] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[25] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[24] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[23] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[22] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[21] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[20] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[19] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[18] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[17] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[16] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[15] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[14] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[13] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[12] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[11] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[10] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[9] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[8] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[7] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[6] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[5] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[4] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[3] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[2] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[1] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_trim[0] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_ena is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_div[4] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_div[3] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_div[2] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_div[1] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_div[0] is used but has no driver. |
| Warning: Wire mgmt_core.\housekeeping.pll_dco_ena is used but has no driver. |
| found and reported 500 problems. |
| |
| 26. Printing statistics. |
| |
| === mgmt_core === |
| |
| Number of wires: 34607 |
| Number of wire bits: 35505 |
| Number of public wires: 3633 |
| Number of public wire bits: 4531 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 34964 |
| DFFRAM 1 |
| digital_pll 1 |
| sky130_fd_sc_hd__a2111o_4 11 |
| sky130_fd_sc_hd__a211o_4 1742 |
| sky130_fd_sc_hd__a21bo_4 67 |
| sky130_fd_sc_hd__a21o_4 134 |
| sky130_fd_sc_hd__a21oi_4 143 |
| sky130_fd_sc_hd__a22oi_4 169 |
| sky130_fd_sc_hd__a2bb2o_4 2113 |
| sky130_fd_sc_hd__a32o_4 711 |
| sky130_fd_sc_hd__a41o_4 2 |
| sky130_fd_sc_hd__and2_4 1499 |
| sky130_fd_sc_hd__and3_4 1910 |
| sky130_fd_sc_hd__and4_4 138 |
| sky130_fd_sc_hd__buf_2 8254 |
| sky130_fd_sc_hd__conb_1 14 |
| sky130_fd_sc_hd__dfbbn_2 18 |
| sky130_fd_sc_hd__dfrtp_4 268 |
| sky130_fd_sc_hd__dfstp_4 70 |
| sky130_fd_sc_hd__dfxtp_4 3510 |
| sky130_fd_sc_hd__inv_2 4040 |
| sky130_fd_sc_hd__nand2_4 323 |
| sky130_fd_sc_hd__nor2_4 986 |
| sky130_fd_sc_hd__o21a_4 918 |
| sky130_fd_sc_hd__o21ai_4 149 |
| sky130_fd_sc_hd__o22a_4 1814 |
| sky130_fd_sc_hd__o32a_4 60 |
| sky130_fd_sc_hd__o41a_4 5 |
| sky130_fd_sc_hd__or2_4 4373 |
| sky130_fd_sc_hd__or3_4 849 |
| sky130_fd_sc_hd__or4_4 672 |
| |
| Area for cell type \DFFRAM is unknown! |
| Area for cell type \digital_pll is unknown! |
| |
| Chip area for module '\mgmt_core': 403450.691200 |
| |
| 27. Executing Verilog backend. |
| Dumping module `\mgmt_core'. |
| |
| Warnings: 594 unique messages, 610 total |
| End of script. Logfile hash: e9e2a310b3, CPU: user 45.83s system 0.22s, MEM: 224.50 MB peak |
| Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) |
| Time spent: 42% 2x abc (33 sec), 14% 44x opt_expr (11 sec), ... |
