| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[0].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B0.BIT[0].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[0].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[0].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[10].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B1.BIT[2].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[10].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[10].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[11].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B1.BIT[3].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[11].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[11].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[12].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B1.BIT[4].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[12].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[12].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[13].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B1.BIT[5].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[13].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[13].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[14].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B1.BIT[6].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[14].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[14].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[15].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B1.BIT[7].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[15].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[15].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[16].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B2.BIT[0].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[16].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[16].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[17].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B2.BIT[1].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[17].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[17].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[18].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B2.BIT[2].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[18].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[18].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[19].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B2.BIT[3].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[19].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[19].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[1].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B0.BIT[1].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[1].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[1].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[20].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B2.BIT[4].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[20].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[20].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[21].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B2.BIT[5].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[21].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[21].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[22].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B2.BIT[6].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[22].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[22].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[23].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B2.BIT[7].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[23].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[23].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[24].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B3.BIT[0].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[24].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[24].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[25].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B3.BIT[1].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[25].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[25].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[26].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B3.BIT[2].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[26].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[26].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[27].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B3.BIT[3].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[27].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[27].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[28].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B3.BIT[4].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[28].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[28].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[29].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B3.BIT[5].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[29].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[29].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[2].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B0.BIT[2].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[2].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[2].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[30].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B3.BIT[6].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[30].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[30].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[31].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B3.BIT[7].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[31].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[31].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[3].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B0.BIT[3].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[3].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[3].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[4].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B0.BIT[4].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[4].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[4].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[5].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B0.BIT[5].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[5].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[5].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[6].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B0.BIT[6].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[6].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[6].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[7].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B0.BIT[7].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[7].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[7].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[8].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B1.BIT[0].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[8].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[8].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[9].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.54 12.09 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 2.61 14.69 ^ B_0_0.WORD[0].W.B1.BIT[1].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 14.69 ^ B_0_0.OUT[9].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 14.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[9].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.88 9.12 library setup time |
| 9.12 data required time |
| --------------------------------------------------------- |
| 9.12 data required time |
| -14.69 data arrival time |
| --------------------------------------------------------- |
| -5.57 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[0].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.97 ^ B_0_0.WORD[0].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.97 ^ B_0_0.WORD[0].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.97 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[0].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.97 data arrival time |
| --------------------------------------------------------- |
| -2.20 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[0].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.97 ^ B_0_0.WORD[0].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.97 ^ B_0_0.WORD[0].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.97 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[0].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.97 data arrival time |
| --------------------------------------------------------- |
| -2.20 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[0].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.97 ^ B_0_0.WORD[0].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.97 ^ B_0_0.WORD[0].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.97 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[0].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.97 data arrival time |
| --------------------------------------------------------- |
| -2.20 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[0].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.86 11.54 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.97 ^ B_0_0.WORD[0].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.97 ^ B_0_0.WORD[0].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.97 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[0].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.97 data arrival time |
| --------------------------------------------------------- |
| -2.20 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[16].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.73 11.27 ^ B_0_0.DEC.DEC_L1[2].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.70 ^ B_0_0.WORD[16].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.70 ^ B_0_0.WORD[16].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.70 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[16].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.70 data arrival time |
| --------------------------------------------------------- |
| -1.93 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[16].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.73 11.27 ^ B_0_0.DEC.DEC_L1[2].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.70 ^ B_0_0.WORD[16].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.70 ^ B_0_0.WORD[16].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.70 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[16].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.70 data arrival time |
| --------------------------------------------------------- |
| -1.93 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[16].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.73 11.27 ^ B_0_0.DEC.DEC_L1[2].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.70 ^ B_0_0.WORD[16].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.70 ^ B_0_0.WORD[16].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.70 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[16].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.70 data arrival time |
| --------------------------------------------------------- |
| -1.93 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[16].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.73 11.27 ^ B_0_0.DEC.DEC_L1[2].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.70 ^ B_0_0.WORD[16].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.70 ^ B_0_0.WORD[16].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.70 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[16].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.70 data arrival time |
| --------------------------------------------------------- |
| -1.93 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[32].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.73 11.27 ^ B_0_0.DEC.DEC_L1[4].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.70 ^ B_0_0.WORD[32].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.70 ^ B_0_0.WORD[32].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.70 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[32].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.70 data arrival time |
| --------------------------------------------------------- |
| -1.93 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[32].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.73 11.27 ^ B_0_0.DEC.DEC_L1[4].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.70 ^ B_0_0.WORD[32].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.70 ^ B_0_0.WORD[32].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.70 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[32].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.70 data arrival time |
| --------------------------------------------------------- |
| -1.93 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[32].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.73 11.27 ^ B_0_0.DEC.DEC_L1[4].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.70 ^ B_0_0.WORD[32].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.70 ^ B_0_0.WORD[32].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.70 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[32].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.70 data arrival time |
| --------------------------------------------------------- |
| -1.93 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[32].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.73 11.27 ^ B_0_0.DEC.DEC_L1[4].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.70 ^ B_0_0.WORD[32].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.70 ^ B_0_0.WORD[32].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.70 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[32].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.70 data arrival time |
| --------------------------------------------------------- |
| -1.93 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[8].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.73 11.27 ^ B_0_0.DEC.DEC_L1[1].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.70 ^ B_0_0.WORD[8].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.70 ^ B_0_0.WORD[8].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.70 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[8].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.70 data arrival time |
| --------------------------------------------------------- |
| -1.93 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[8].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.73 11.27 ^ B_0_0.DEC.DEC_L1[1].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.70 ^ B_0_0.WORD[8].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.70 ^ B_0_0.WORD[8].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.70 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[8].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.70 data arrival time |
| --------------------------------------------------------- |
| -1.93 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[8].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.73 11.27 ^ B_0_0.DEC.DEC_L1[1].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.70 ^ B_0_0.WORD[8].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.70 ^ B_0_0.WORD[8].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.70 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[8].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.70 data arrival time |
| --------------------------------------------------------- |
| -1.93 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[8].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.73 11.27 ^ B_0_0.DEC.DEC_L1[1].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.70 ^ B_0_0.WORD[8].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.70 ^ B_0_0.WORD[8].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.70 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[8].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.70 data arrival time |
| --------------------------------------------------------- |
| -1.93 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[2].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.69 ^ B_0_0.WORD[2].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.69 ^ B_0_0.WORD[2].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[2].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.69 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[2].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.69 ^ B_0_0.WORD[2].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.69 ^ B_0_0.WORD[2].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[2].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.69 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[2].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.69 ^ B_0_0.WORD[2].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.69 ^ B_0_0.WORD[2].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[2].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.69 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[2].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.69 ^ B_0_0.WORD[2].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.69 ^ B_0_0.WORD[2].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[2].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.69 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[1].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.69 ^ B_0_0.WORD[1].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.69 ^ B_0_0.WORD[1].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[1].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.69 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[1].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.69 ^ B_0_0.WORD[1].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.69 ^ B_0_0.WORD[1].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[1].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.69 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[1].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.69 ^ B_0_0.WORD[1].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.69 ^ B_0_0.WORD[1].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[1].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.69 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[1].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.69 ^ B_0_0.WORD[1].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.69 ^ B_0_0.WORD[1].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[1].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.69 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[4].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.69 ^ B_0_0.WORD[4].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.69 ^ B_0_0.WORD[4].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[4].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.69 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[4].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.69 ^ B_0_0.WORD[4].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.69 ^ B_0_0.WORD[4].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[4].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.69 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[4].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.69 ^ B_0_0.WORD[4].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.69 ^ B_0_0.WORD[4].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[4].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.69 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[4].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.69 ^ B_0_0.WORD[4].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.69 ^ B_0_0.WORD[4].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.69 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[4].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.69 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[3].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 0.26 11.68 ^ B_0_0.WORD[3].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[3].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[3].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[3].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 0.26 11.68 ^ B_0_0.WORD[3].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[3].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[3].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[3].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 0.26 11.68 ^ B_0_0.WORD[3].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[3].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[3].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[3].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 0.26 11.68 ^ B_0_0.WORD[3].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[3].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[3].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[6].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 0.26 11.68 ^ B_0_0.WORD[6].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[6].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[6].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[6].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 0.26 11.68 ^ B_0_0.WORD[6].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[6].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[6].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[6].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 0.26 11.68 ^ B_0_0.WORD[6].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[6].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[6].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[6].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 0.26 11.68 ^ B_0_0.WORD[6].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[6].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[6].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[5].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 0.26 11.68 ^ B_0_0.WORD[5].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[5].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[5].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[5].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 0.26 11.68 ^ B_0_0.WORD[5].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[5].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[5].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[5].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 0.26 11.68 ^ B_0_0.WORD[5].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[5].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[5].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[5].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.75 11.43 ^ B_0_0.DEC.DEC_L1[0].U.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 0.26 11.68 ^ B_0_0.WORD[5].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[5].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[5].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.92 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[7].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.74 11.42 ^ B_0_0.DEC.DEC_L1[0].U.AND7/X (sky130_fd_sc_hd__and4_2) |
| 0.26 11.68 ^ B_0_0.WORD[7].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[7].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[7].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[7].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.74 11.42 ^ B_0_0.DEC.DEC_L1[0].U.AND7/X (sky130_fd_sc_hd__and4_2) |
| 0.26 11.68 ^ B_0_0.WORD[7].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[7].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[7].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[7].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.74 11.42 ^ B_0_0.DEC.DEC_L1[0].U.AND7/X (sky130_fd_sc_hd__and4_2) |
| 0.26 11.68 ^ B_0_0.WORD[7].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[7].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[7].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[7].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.13 10.68 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.74 11.42 ^ B_0_0.DEC.DEC_L1[0].U.AND7/X (sky130_fd_sc_hd__and4_2) |
| 0.26 11.68 ^ B_0_0.WORD[7].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[7].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[7].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[24].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.97 10.52 ^ B_0_0.DEC.DEC_L0.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 0.73 11.25 ^ B_0_0.DEC.DEC_L1[3].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.68 ^ B_0_0.WORD[24].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[24].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[24].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[24].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.97 10.52 ^ B_0_0.DEC.DEC_L0.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 0.73 11.25 ^ B_0_0.DEC.DEC_L1[3].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.68 ^ B_0_0.WORD[24].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[24].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[24].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[24].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.97 10.52 ^ B_0_0.DEC.DEC_L0.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 0.73 11.25 ^ B_0_0.DEC.DEC_L1[3].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.68 ^ B_0_0.WORD[24].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[24].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[24].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[24].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.97 10.52 ^ B_0_0.DEC.DEC_L0.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 0.73 11.25 ^ B_0_0.DEC.DEC_L1[3].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.68 ^ B_0_0.WORD[24].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[24].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[24].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[40].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.97 10.52 ^ B_0_0.DEC.DEC_L0.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 0.73 11.25 ^ B_0_0.DEC.DEC_L1[5].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.68 ^ B_0_0.WORD[40].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[40].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[40].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[40].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.97 10.52 ^ B_0_0.DEC.DEC_L0.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 0.73 11.25 ^ B_0_0.DEC.DEC_L1[5].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.68 ^ B_0_0.WORD[40].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[40].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[40].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[40].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.97 10.52 ^ B_0_0.DEC.DEC_L0.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 0.73 11.25 ^ B_0_0.DEC.DEC_L1[5].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.68 ^ B_0_0.WORD[40].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[40].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[40].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[40].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.97 10.52 ^ B_0_0.DEC.DEC_L0.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 0.73 11.25 ^ B_0_0.DEC.DEC_L1[5].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.68 ^ B_0_0.WORD[40].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[40].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[40].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[48].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.97 10.52 ^ B_0_0.DEC.DEC_L0.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 0.73 11.25 ^ B_0_0.DEC.DEC_L1[6].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.68 ^ B_0_0.WORD[48].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[48].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[48].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[48].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.97 10.52 ^ B_0_0.DEC.DEC_L0.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 0.73 11.25 ^ B_0_0.DEC.DEC_L1[6].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.68 ^ B_0_0.WORD[48].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[48].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[48].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[48].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.97 10.52 ^ B_0_0.DEC.DEC_L0.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 0.73 11.25 ^ B_0_0.DEC.DEC_L1[6].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.68 ^ B_0_0.WORD[48].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[48].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[48].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[48].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.97 10.52 ^ B_0_0.DEC.DEC_L0.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 0.73 11.25 ^ B_0_0.DEC.DEC_L1[6].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.68 ^ B_0_0.WORD[48].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.68 ^ B_0_0.WORD[48].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.68 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[48].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.68 data arrival time |
| --------------------------------------------------------- |
| -1.91 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[56].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.96 10.52 ^ B_0_0.DEC.DEC_L0.AND7/X (sky130_fd_sc_hd__and4_2) |
| 0.73 11.24 ^ B_0_0.DEC.DEC_L1[7].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.67 ^ B_0_0.WORD[56].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.67 ^ B_0_0.WORD[56].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.67 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[56].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.67 data arrival time |
| --------------------------------------------------------- |
| -1.90 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[56].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.96 10.52 ^ B_0_0.DEC.DEC_L0.AND7/X (sky130_fd_sc_hd__and4_2) |
| 0.73 11.24 ^ B_0_0.DEC.DEC_L1[7].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.67 ^ B_0_0.WORD[56].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.67 ^ B_0_0.WORD[56].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.67 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[56].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.67 data arrival time |
| --------------------------------------------------------- |
| -1.90 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[56].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.96 10.52 ^ B_0_0.DEC.DEC_L0.AND7/X (sky130_fd_sc_hd__and4_2) |
| 0.73 11.24 ^ B_0_0.DEC.DEC_L1[7].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.67 ^ B_0_0.WORD[56].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.67 ^ B_0_0.WORD[56].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.67 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[56].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.67 data arrival time |
| --------------------------------------------------------- |
| -1.90 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[56].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.96 10.52 ^ B_0_0.DEC.DEC_L0.AND7/X (sky130_fd_sc_hd__and4_2) |
| 0.73 11.24 ^ B_0_0.DEC.DEC_L1[7].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.43 11.67 ^ B_0_0.WORD[56].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.67 ^ B_0_0.WORD[56].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.67 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[56].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.67 data arrival time |
| --------------------------------------------------------- |
| -1.90 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[10].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.65 11.19 ^ B_0_0.DEC.DEC_L1[1].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.45 ^ B_0_0.WORD[10].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.45 ^ B_0_0.WORD[10].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.45 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[10].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.45 data arrival time |
| --------------------------------------------------------- |
| -1.68 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[10].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.65 11.19 ^ B_0_0.DEC.DEC_L1[1].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.45 ^ B_0_0.WORD[10].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.45 ^ B_0_0.WORD[10].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.45 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[10].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.45 data arrival time |
| --------------------------------------------------------- |
| -1.68 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[10].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.65 11.19 ^ B_0_0.DEC.DEC_L1[1].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.45 ^ B_0_0.WORD[10].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.45 ^ B_0_0.WORD[10].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.45 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[10].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.45 data arrival time |
| --------------------------------------------------------- |
| -1.68 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[10].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.65 11.19 ^ B_0_0.DEC.DEC_L1[1].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.45 ^ B_0_0.WORD[10].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.45 ^ B_0_0.WORD[10].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.45 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[10].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.45 data arrival time |
| --------------------------------------------------------- |
| -1.68 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[18].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.65 11.19 ^ B_0_0.DEC.DEC_L1[2].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.45 ^ B_0_0.WORD[18].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.45 ^ B_0_0.WORD[18].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.45 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[18].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.45 data arrival time |
| --------------------------------------------------------- |
| -1.68 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[18].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.65 11.19 ^ B_0_0.DEC.DEC_L1[2].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.45 ^ B_0_0.WORD[18].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.45 ^ B_0_0.WORD[18].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.45 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[18].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.45 data arrival time |
| --------------------------------------------------------- |
| -1.68 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[18].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.65 11.19 ^ B_0_0.DEC.DEC_L1[2].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.45 ^ B_0_0.WORD[18].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.45 ^ B_0_0.WORD[18].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.45 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[18].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.45 data arrival time |
| --------------------------------------------------------- |
| -1.68 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[18].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 6.46 8.56 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 1.98 10.54 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.65 11.19 ^ B_0_0.DEC.DEC_L1[2].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.26 11.45 ^ B_0_0.WORD[18].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 11.45 ^ B_0_0.WORD[18].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 11.45 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[18].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -11.45 data arrival time |
| --------------------------------------------------------- |
| -1.68 slack (VIOLATED) |
| |
| |
