| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[11].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.42 15.39 v B_0_0.WORD[0].W.B1.BIT[3].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.02 15.41 v B_0_0.OUT[11].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.41 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[11].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.41 data arrival time |
| --------------------------------------------------------- |
| -5.66 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[10].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.42 15.39 v B_0_0.WORD[0].W.B1.BIT[2].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.01 15.40 v B_0_0.OUT[10].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.40 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[10].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.40 data arrival time |
| --------------------------------------------------------- |
| -5.66 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[9].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.42 15.39 v B_0_0.WORD[0].W.B1.BIT[1].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.01 15.40 v B_0_0.OUT[9].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.40 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[9].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.40 data arrival time |
| --------------------------------------------------------- |
| -5.66 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[14].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.42 15.39 v B_0_0.WORD[0].W.B1.BIT[6].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.01 15.40 v B_0_0.OUT[14].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.40 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[14].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.40 data arrival time |
| --------------------------------------------------------- |
| -5.66 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[1].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.08 14.97 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.35 v B_0_0.WORD[0].W.B0.BIT[1].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.04 15.39 v B_0_0.OUT[1].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.39 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[1].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.39 data arrival time |
| --------------------------------------------------------- |
| -5.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[13].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.42 15.39 v B_0_0.WORD[0].W.B1.BIT[5].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.01 15.39 v B_0_0.OUT[13].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.39 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[13].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.39 data arrival time |
| --------------------------------------------------------- |
| -5.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[15].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.42 15.39 v B_0_0.WORD[0].W.B1.BIT[7].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.01 15.39 v B_0_0.OUT[15].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.39 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[15].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.39 data arrival time |
| --------------------------------------------------------- |
| -5.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[12].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.42 15.39 v B_0_0.WORD[0].W.B1.BIT[4].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.01 15.39 v B_0_0.OUT[12].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.39 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[12].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.39 data arrival time |
| --------------------------------------------------------- |
| -5.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[21].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.36 v B_0_0.WORD[0].W.B2.BIT[5].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.03 15.39 v B_0_0.OUT[21].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.39 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[21].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.39 data arrival time |
| --------------------------------------------------------- |
| -5.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[8].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B1.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.42 15.39 v B_0_0.WORD[0].W.B1.BIT[0].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 15.39 v B_0_0.OUT[8].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.39 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[8].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.39 data arrival time |
| --------------------------------------------------------- |
| -5.64 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[22].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.36 v B_0_0.WORD[0].W.B2.BIT[6].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.02 15.38 v B_0_0.OUT[22].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.38 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[22].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.38 data arrival time |
| --------------------------------------------------------- |
| -5.64 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[23].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.36 v B_0_0.WORD[0].W.B2.BIT[7].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.02 15.37 v B_0_0.OUT[23].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.37 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[23].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.37 data arrival time |
| --------------------------------------------------------- |
| -5.63 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[19].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.36 v B_0_0.WORD[0].W.B2.BIT[3].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.01 15.37 v B_0_0.OUT[19].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.37 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[19].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.37 data arrival time |
| --------------------------------------------------------- |
| -5.63 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[6].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.08 14.97 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.35 v B_0_0.WORD[0].W.B0.BIT[6].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.01 15.36 v B_0_0.OUT[6].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[6].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.36 data arrival time |
| --------------------------------------------------------- |
| -5.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[17].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.36 v B_0_0.WORD[0].W.B2.BIT[1].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.01 15.36 v B_0_0.OUT[17].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[17].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.36 data arrival time |
| --------------------------------------------------------- |
| -5.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[28].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.07 14.95 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.38 15.34 v B_0_0.WORD[0].W.B3.BIT[4].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.02 15.36 v B_0_0.OUT[28].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[28].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.36 data arrival time |
| --------------------------------------------------------- |
| -5.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[20].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.36 v B_0_0.WORD[0].W.B2.BIT[4].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 15.36 v B_0_0.OUT[20].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[20].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.36 data arrival time |
| --------------------------------------------------------- |
| -5.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[16].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.36 v B_0_0.WORD[0].W.B2.BIT[0].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 15.36 v B_0_0.OUT[16].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[16].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.36 data arrival time |
| --------------------------------------------------------- |
| -5.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[29].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.07 14.95 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.38 15.34 v B_0_0.WORD[0].W.B3.BIT[5].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.02 15.36 v B_0_0.OUT[29].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[29].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.36 data arrival time |
| --------------------------------------------------------- |
| -5.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[0].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.08 14.97 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.35 v B_0_0.WORD[0].W.B0.BIT[0].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 15.36 v B_0_0.OUT[0].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[0].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.36 data arrival time |
| --------------------------------------------------------- |
| -5.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[18].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.09 14.97 v B_0_0.WORD[0].W.B2.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.36 v B_0_0.WORD[0].W.B2.BIT[2].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 15.36 v B_0_0.OUT[18].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[18].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.36 data arrival time |
| --------------------------------------------------------- |
| -5.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[4].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.08 14.97 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.35 v B_0_0.WORD[0].W.B0.BIT[4].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 15.36 v B_0_0.OUT[4].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[4].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.36 data arrival time |
| --------------------------------------------------------- |
| -5.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[27].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.07 14.95 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.38 15.34 v B_0_0.WORD[0].W.B3.BIT[3].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.02 15.36 v B_0_0.OUT[27].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[27].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.36 data arrival time |
| --------------------------------------------------------- |
| -5.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[5].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.08 14.97 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.35 v B_0_0.WORD[0].W.B0.BIT[5].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 15.36 v B_0_0.OUT[5].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[5].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.36 data arrival time |
| --------------------------------------------------------- |
| -5.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[24].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.07 14.95 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.38 15.34 v B_0_0.WORD[0].W.B3.BIT[0].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.02 15.36 v B_0_0.OUT[24].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[24].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.36 data arrival time |
| --------------------------------------------------------- |
| -5.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[7].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.08 14.97 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.35 v B_0_0.WORD[0].W.B0.BIT[7].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 15.36 v B_0_0.OUT[7].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[7].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.36 data arrival time |
| --------------------------------------------------------- |
| -5.61 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[2].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.08 14.97 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.35 v B_0_0.WORD[0].W.B0.BIT[2].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 15.35 v B_0_0.OUT[2].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.35 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[2].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.35 data arrival time |
| --------------------------------------------------------- |
| -5.61 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[3].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.08 14.97 v B_0_0.WORD[0].W.B0.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.39 15.35 v B_0_0.WORD[0].W.B0.BIT[3].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.00 15.35 v B_0_0.OUT[3].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.35 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[3].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.35 data arrival time |
| --------------------------------------------------------- |
| -5.61 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[25].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.07 14.95 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.38 15.34 v B_0_0.WORD[0].W.B3.BIT[1].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.01 15.35 v B_0_0.OUT[25].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.35 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[25].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.35 data arrival time |
| --------------------------------------------------------- |
| -5.61 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[30].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.07 14.95 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.38 15.34 v B_0_0.WORD[0].W.B3.BIT[6].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.01 15.35 v B_0_0.OUT[30].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.35 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[30].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.35 data arrival time |
| --------------------------------------------------------- |
| -5.61 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[26].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.07 14.95 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.38 15.34 v B_0_0.WORD[0].W.B3.BIT[2].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.01 15.35 v B_0_0.OUT[26].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.35 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[26].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.35 data arrival time |
| --------------------------------------------------------- |
| -5.61 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.OUT[31].FF (rising edge-triggered flip-flop clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.07 14.95 v B_0_0.WORD[0].W.B3.INV/Y (sky130_fd_sc_hd__inv_1) |
| 0.38 15.34 v B_0_0.WORD[0].W.B3.BIT[7].OBUF/Z (sky130_fd_sc_hd__ebufn_2) |
| 0.01 15.35 v B_0_0.OUT[31].FF/D (sky130_fd_sc_hd__dfxtp_1) |
| 15.35 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.OUT[31].FF/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.26 9.74 library setup time |
| 9.74 data required time |
| --------------------------------------------------------- |
| 9.74 data required time |
| -15.35 data arrival time |
| --------------------------------------------------------- |
| -5.61 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[0].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.70 14.59 ^ B_0_0.WORD[0].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.59 ^ B_0_0.WORD[0].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.59 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[0].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.59 data arrival time |
| --------------------------------------------------------- |
| -4.83 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[0].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.70 14.59 ^ B_0_0.WORD[0].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.59 ^ B_0_0.WORD[0].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.59 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[0].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.59 data arrival time |
| --------------------------------------------------------- |
| -4.83 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[0].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.70 14.58 ^ B_0_0.WORD[0].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.58 ^ B_0_0.WORD[0].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.58 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[0].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.58 data arrival time |
| --------------------------------------------------------- |
| -4.83 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[0].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.85 13.88 ^ B_0_0.DEC.DEC_L1[0].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.70 14.58 ^ B_0_0.WORD[0].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.58 ^ B_0_0.WORD[0].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.58 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[0].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.58 data arrival time |
| --------------------------------------------------------- |
| -4.83 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[24].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.48 11.84 ^ B_0_0.DEC.DEC_L0.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 1.90 13.74 ^ B_0_0.DEC.DEC_L1[3].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.73 14.47 ^ B_0_0.WORD[24].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.47 ^ B_0_0.WORD[24].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.47 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[24].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.25 9.75 library setup time |
| 9.75 data required time |
| --------------------------------------------------------- |
| 9.75 data required time |
| -14.47 data arrival time |
| --------------------------------------------------------- |
| -4.72 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[24].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.48 11.84 ^ B_0_0.DEC.DEC_L0.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 1.90 13.74 ^ B_0_0.DEC.DEC_L1[3].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.73 14.47 ^ B_0_0.WORD[24].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.47 ^ B_0_0.WORD[24].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.47 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[24].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.25 9.75 library setup time |
| 9.75 data required time |
| --------------------------------------------------------- |
| 9.75 data required time |
| -14.47 data arrival time |
| --------------------------------------------------------- |
| -4.72 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[24].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.48 11.84 ^ B_0_0.DEC.DEC_L0.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 1.90 13.74 ^ B_0_0.DEC.DEC_L1[3].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.73 14.47 ^ B_0_0.WORD[24].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.47 ^ B_0_0.WORD[24].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.47 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[24].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.25 9.75 library setup time |
| 9.75 data required time |
| --------------------------------------------------------- |
| 9.75 data required time |
| -14.47 data arrival time |
| --------------------------------------------------------- |
| -4.72 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[24].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.48 11.84 ^ B_0_0.DEC.DEC_L0.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 1.90 13.74 ^ B_0_0.DEC.DEC_L1[3].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.73 14.47 ^ B_0_0.WORD[24].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.47 ^ B_0_0.WORD[24].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.47 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[24].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.25 9.75 library setup time |
| 9.75 data required time |
| --------------------------------------------------------- |
| 9.75 data required time |
| -14.47 data arrival time |
| --------------------------------------------------------- |
| -4.72 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[16].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.50 11.86 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 1.82 13.69 ^ B_0_0.DEC.DEC_L1[2].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.72 14.41 ^ B_0_0.WORD[16].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.41 ^ B_0_0.WORD[16].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.41 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[16].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.25 9.75 library setup time |
| 9.75 data required time |
| --------------------------------------------------------- |
| 9.75 data required time |
| -14.41 data arrival time |
| --------------------------------------------------------- |
| -4.66 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[16].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.50 11.86 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 1.82 13.69 ^ B_0_0.DEC.DEC_L1[2].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.72 14.41 ^ B_0_0.WORD[16].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.41 ^ B_0_0.WORD[16].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.41 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[16].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.25 9.75 library setup time |
| 9.75 data required time |
| --------------------------------------------------------- |
| 9.75 data required time |
| -14.41 data arrival time |
| --------------------------------------------------------- |
| -4.66 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[16].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.50 11.86 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 1.82 13.69 ^ B_0_0.DEC.DEC_L1[2].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.72 14.41 ^ B_0_0.WORD[16].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.41 ^ B_0_0.WORD[16].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.41 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[16].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.25 9.75 library setup time |
| 9.75 data required time |
| --------------------------------------------------------- |
| 9.75 data required time |
| -14.41 data arrival time |
| --------------------------------------------------------- |
| -4.66 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[16].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.50 11.86 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 1.82 13.69 ^ B_0_0.DEC.DEC_L1[2].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.72 14.41 ^ B_0_0.WORD[16].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.41 ^ B_0_0.WORD[16].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.41 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[16].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.25 9.75 library setup time |
| 9.75 data required time |
| --------------------------------------------------------- |
| 9.75 data required time |
| -14.41 data arrival time |
| --------------------------------------------------------- |
| -4.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[8].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.49 11.86 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 1.79 13.65 ^ B_0_0.DEC.DEC_L1[1].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.71 14.36 ^ B_0_0.WORD[8].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.36 ^ B_0_0.WORD[8].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[8].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.25 9.75 library setup time |
| 9.75 data required time |
| --------------------------------------------------------- |
| 9.75 data required time |
| -14.36 data arrival time |
| --------------------------------------------------------- |
| -4.61 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[8].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.49 11.86 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 1.79 13.65 ^ B_0_0.DEC.DEC_L1[1].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.71 14.36 ^ B_0_0.WORD[8].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.36 ^ B_0_0.WORD[8].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[8].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.36 data arrival time |
| --------------------------------------------------------- |
| -4.61 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[8].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.49 11.86 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 1.79 13.65 ^ B_0_0.DEC.DEC_L1[1].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.71 14.36 ^ B_0_0.WORD[8].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.36 ^ B_0_0.WORD[8].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[8].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.36 data arrival time |
| --------------------------------------------------------- |
| -4.60 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[8].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.49 11.86 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 1.79 13.65 ^ B_0_0.DEC.DEC_L1[1].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.71 14.36 ^ B_0_0.WORD[8].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.36 ^ B_0_0.WORD[8].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[8].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.36 data arrival time |
| --------------------------------------------------------- |
| -4.60 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[56].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.47 11.83 ^ B_0_0.DEC.DEC_L0.AND7/X (sky130_fd_sc_hd__and4_2) |
| 1.80 13.64 ^ B_0_0.DEC.DEC_L1[7].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.72 14.36 ^ B_0_0.WORD[56].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.36 ^ B_0_0.WORD[56].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.36 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[56].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.25 9.75 library setup time |
| 9.75 data required time |
| --------------------------------------------------------- |
| 9.75 data required time |
| -14.36 data arrival time |
| --------------------------------------------------------- |
| -4.60 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[56].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.47 11.83 ^ B_0_0.DEC.DEC_L0.AND7/X (sky130_fd_sc_hd__and4_2) |
| 1.80 13.64 ^ B_0_0.DEC.DEC_L1[7].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.72 14.35 ^ B_0_0.WORD[56].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.35 ^ B_0_0.WORD[56].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.35 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[56].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.35 data arrival time |
| --------------------------------------------------------- |
| -4.60 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[56].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.47 11.83 ^ B_0_0.DEC.DEC_L0.AND7/X (sky130_fd_sc_hd__and4_2) |
| 1.80 13.64 ^ B_0_0.DEC.DEC_L1[7].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.72 14.35 ^ B_0_0.WORD[56].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.35 ^ B_0_0.WORD[56].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.35 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[56].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.25 9.75 library setup time |
| 9.75 data required time |
| --------------------------------------------------------- |
| 9.75 data required time |
| -14.35 data arrival time |
| --------------------------------------------------------- |
| -4.60 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[56].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.47 11.83 ^ B_0_0.DEC.DEC_L0.AND7/X (sky130_fd_sc_hd__and4_2) |
| 1.80 13.64 ^ B_0_0.DEC.DEC_L1[7].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.71 14.35 ^ B_0_0.WORD[56].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.35 ^ B_0_0.WORD[56].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.35 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[56].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.35 data arrival time |
| --------------------------------------------------------- |
| -4.60 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[32].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.49 11.85 ^ B_0_0.DEC.DEC_L0.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 1.74 13.60 ^ B_0_0.DEC.DEC_L1[4].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.71 14.30 ^ B_0_0.WORD[32].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.30 ^ B_0_0.WORD[32].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.30 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[32].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.30 data arrival time |
| --------------------------------------------------------- |
| -4.55 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[32].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.49 11.85 ^ B_0_0.DEC.DEC_L0.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 1.74 13.60 ^ B_0_0.DEC.DEC_L1[4].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.71 14.30 ^ B_0_0.WORD[32].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.30 ^ B_0_0.WORD[32].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.30 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[32].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.30 data arrival time |
| --------------------------------------------------------- |
| -4.55 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[32].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.49 11.85 ^ B_0_0.DEC.DEC_L0.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 1.74 13.60 ^ B_0_0.DEC.DEC_L1[4].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.71 14.30 ^ B_0_0.WORD[32].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.30 ^ B_0_0.WORD[32].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.30 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[32].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.30 data arrival time |
| --------------------------------------------------------- |
| -4.55 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[32].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.49 11.85 ^ B_0_0.DEC.DEC_L0.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 1.74 13.60 ^ B_0_0.DEC.DEC_L1[4].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.71 14.30 ^ B_0_0.WORD[32].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.30 ^ B_0_0.WORD[32].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.30 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[32].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.30 data arrival time |
| --------------------------------------------------------- |
| -4.55 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[40].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.47 11.84 ^ B_0_0.DEC.DEC_L0.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 1.68 13.52 ^ B_0_0.DEC.DEC_L1[5].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.70 14.21 ^ B_0_0.WORD[40].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.21 ^ B_0_0.WORD[40].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.21 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[40].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.21 data arrival time |
| --------------------------------------------------------- |
| -4.46 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[40].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.47 11.84 ^ B_0_0.DEC.DEC_L0.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 1.68 13.52 ^ B_0_0.DEC.DEC_L1[5].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.70 14.21 ^ B_0_0.WORD[40].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.21 ^ B_0_0.WORD[40].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.21 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[40].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.21 data arrival time |
| --------------------------------------------------------- |
| -4.46 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[40].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.47 11.84 ^ B_0_0.DEC.DEC_L0.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 1.68 13.52 ^ B_0_0.DEC.DEC_L1[5].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.70 14.21 ^ B_0_0.WORD[40].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.21 ^ B_0_0.WORD[40].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.21 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[40].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.21 data arrival time |
| --------------------------------------------------------- |
| -4.46 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[40].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.47 11.84 ^ B_0_0.DEC.DEC_L0.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 1.68 13.52 ^ B_0_0.DEC.DEC_L1[5].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.69 14.21 ^ B_0_0.WORD[40].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.21 ^ B_0_0.WORD[40].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.21 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[40].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.21 data arrival time |
| --------------------------------------------------------- |
| -4.45 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[48].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.47 11.83 ^ B_0_0.DEC.DEC_L0.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 1.66 13.49 ^ B_0_0.DEC.DEC_L1[6].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.70 14.19 ^ B_0_0.WORD[48].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.19 ^ B_0_0.WORD[48].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.19 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[48].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.19 data arrival time |
| --------------------------------------------------------- |
| -4.43 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[48].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.47 11.83 ^ B_0_0.DEC.DEC_L0.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 1.66 13.49 ^ B_0_0.DEC.DEC_L1[6].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.69 14.19 ^ B_0_0.WORD[48].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.19 ^ B_0_0.WORD[48].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.19 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[48].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.19 data arrival time |
| --------------------------------------------------------- |
| -4.43 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[48].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.47 11.83 ^ B_0_0.DEC.DEC_L0.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 1.66 13.49 ^ B_0_0.DEC.DEC_L1[6].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.69 14.19 ^ B_0_0.WORD[48].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.19 ^ B_0_0.WORD[48].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.19 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[48].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.19 data arrival time |
| --------------------------------------------------------- |
| -4.43 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[48].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.47 11.83 ^ B_0_0.DEC.DEC_L0.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 1.66 13.49 ^ B_0_0.DEC.DEC_L1[6].U.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.69 14.18 ^ B_0_0.WORD[48].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 14.18 ^ B_0_0.WORD[48].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 14.18 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[48].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.24 9.76 library setup time |
| 9.76 data required time |
| --------------------------------------------------------- |
| 9.76 data required time |
| -14.18 data arrival time |
| --------------------------------------------------------- |
| -4.43 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[4].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.02 13.05 ^ B_0_0.DEC.DEC_L1[0].U.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.40 13.45 ^ B_0_0.WORD[4].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.45 ^ B_0_0.WORD[4].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.45 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[4].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.45 data arrival time |
| --------------------------------------------------------- |
| -3.68 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[4].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.02 13.05 ^ B_0_0.DEC.DEC_L1[0].U.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.40 13.45 ^ B_0_0.WORD[4].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.45 ^ B_0_0.WORD[4].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.45 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[4].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.45 data arrival time |
| --------------------------------------------------------- |
| -3.68 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[4].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.02 13.05 ^ B_0_0.DEC.DEC_L1[0].U.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.39 13.45 ^ B_0_0.WORD[4].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.45 ^ B_0_0.WORD[4].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.45 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[4].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.45 data arrival time |
| --------------------------------------------------------- |
| -3.68 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[4].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.02 13.05 ^ B_0_0.DEC.DEC_L1[0].U.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.39 13.45 ^ B_0_0.WORD[4].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.45 ^ B_0_0.WORD[4].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.45 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[4].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.45 data arrival time |
| --------------------------------------------------------- |
| -3.68 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[2].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.02 13.05 ^ B_0_0.DEC.DEC_L1[0].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.39 13.44 ^ B_0_0.WORD[2].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.44 ^ B_0_0.WORD[2].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.44 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[2].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.44 data arrival time |
| --------------------------------------------------------- |
| -3.68 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[2].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.02 13.05 ^ B_0_0.DEC.DEC_L1[0].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.39 13.44 ^ B_0_0.WORD[2].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.44 ^ B_0_0.WORD[2].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.44 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[2].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.44 data arrival time |
| --------------------------------------------------------- |
| -3.68 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[2].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.02 13.05 ^ B_0_0.DEC.DEC_L1[0].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.39 13.44 ^ B_0_0.WORD[2].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.44 ^ B_0_0.WORD[2].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.44 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[2].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.44 data arrival time |
| --------------------------------------------------------- |
| -3.68 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[2].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.02 13.05 ^ B_0_0.DEC.DEC_L1[0].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.39 13.44 ^ B_0_0.WORD[2].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.44 ^ B_0_0.WORD[2].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.44 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[2].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.44 data arrival time |
| --------------------------------------------------------- |
| -3.67 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[5].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.01 13.04 ^ B_0_0.DEC.DEC_L1[0].U.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 0.39 13.43 ^ B_0_0.WORD[5].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.43 ^ B_0_0.WORD[5].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.43 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[5].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.43 data arrival time |
| --------------------------------------------------------- |
| -3.67 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[5].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.01 13.04 ^ B_0_0.DEC.DEC_L1[0].U.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 0.39 13.43 ^ B_0_0.WORD[5].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.43 ^ B_0_0.WORD[5].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.43 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[5].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.43 data arrival time |
| --------------------------------------------------------- |
| -3.67 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[5].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.01 13.04 ^ B_0_0.DEC.DEC_L1[0].U.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 0.39 13.43 ^ B_0_0.WORD[5].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.43 ^ B_0_0.WORD[5].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.43 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[5].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.43 data arrival time |
| --------------------------------------------------------- |
| -3.66 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[5].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.01 13.04 ^ B_0_0.DEC.DEC_L1[0].U.AND5/X (sky130_fd_sc_hd__and4b_2) |
| 0.39 13.43 ^ B_0_0.WORD[5].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.43 ^ B_0_0.WORD[5].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.43 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[5].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.43 data arrival time |
| --------------------------------------------------------- |
| -3.66 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[6].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.00 13.04 ^ B_0_0.DEC.DEC_L1[0].U.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 0.39 13.42 ^ B_0_0.WORD[6].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.42 ^ B_0_0.WORD[6].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.42 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[6].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.42 data arrival time |
| --------------------------------------------------------- |
| -3.66 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[6].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.00 13.04 ^ B_0_0.DEC.DEC_L1[0].U.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 0.39 13.42 ^ B_0_0.WORD[6].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.42 ^ B_0_0.WORD[6].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.42 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[6].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.42 data arrival time |
| --------------------------------------------------------- |
| -3.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[6].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.00 13.04 ^ B_0_0.DEC.DEC_L1[0].U.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 0.38 13.42 ^ B_0_0.WORD[6].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.42 ^ B_0_0.WORD[6].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.42 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[6].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.42 data arrival time |
| --------------------------------------------------------- |
| -3.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[6].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.00 13.04 ^ B_0_0.DEC.DEC_L1[0].U.AND6/X (sky130_fd_sc_hd__and4b_2) |
| 0.38 13.42 ^ B_0_0.WORD[6].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.42 ^ B_0_0.WORD[6].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.42 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[6].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.42 data arrival time |
| --------------------------------------------------------- |
| -3.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[1].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.00 13.03 ^ B_0_0.DEC.DEC_L1[0].U.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.38 13.42 ^ B_0_0.WORD[1].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.42 ^ B_0_0.WORD[1].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.42 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[1].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.42 data arrival time |
| --------------------------------------------------------- |
| -3.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[1].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.00 13.03 ^ B_0_0.DEC.DEC_L1[0].U.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.38 13.42 ^ B_0_0.WORD[1].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.42 ^ B_0_0.WORD[1].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.42 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[1].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.42 data arrival time |
| --------------------------------------------------------- |
| -3.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[7].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.00 13.03 ^ B_0_0.DEC.DEC_L1[0].U.AND7/X (sky130_fd_sc_hd__and4_2) |
| 0.38 13.41 ^ B_0_0.WORD[7].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.41 ^ B_0_0.WORD[7].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.41 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[7].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.41 data arrival time |
| --------------------------------------------------------- |
| -3.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[1].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.00 13.03 ^ B_0_0.DEC.DEC_L1[0].U.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.38 13.42 ^ B_0_0.WORD[1].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.42 ^ B_0_0.WORD[1].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.42 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[1].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.42 data arrival time |
| --------------------------------------------------------- |
| -3.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[1].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.00 13.03 ^ B_0_0.DEC.DEC_L1[0].U.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.38 13.42 ^ B_0_0.WORD[1].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.42 ^ B_0_0.WORD[1].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.42 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[1].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.42 data arrival time |
| --------------------------------------------------------- |
| -3.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[7].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.00 13.03 ^ B_0_0.DEC.DEC_L1[0].U.AND7/X (sky130_fd_sc_hd__and4_2) |
| 0.38 13.41 ^ B_0_0.WORD[7].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.41 ^ B_0_0.WORD[7].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.41 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[7].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.41 data arrival time |
| --------------------------------------------------------- |
| -3.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[7].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.00 13.03 ^ B_0_0.DEC.DEC_L1[0].U.AND7/X (sky130_fd_sc_hd__and4_2) |
| 0.38 13.41 ^ B_0_0.WORD[7].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.41 ^ B_0_0.WORD[7].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.41 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[7].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.41 data arrival time |
| --------------------------------------------------------- |
| -3.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[7].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 1.00 13.03 ^ B_0_0.DEC.DEC_L1[0].U.AND7/X (sky130_fd_sc_hd__and4_2) |
| 0.38 13.41 ^ B_0_0.WORD[7].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.41 ^ B_0_0.WORD[7].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.41 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[7].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.41 data arrival time |
| --------------------------------------------------------- |
| -3.65 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[3].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.98 13.02 ^ B_0_0.DEC.DEC_L1[0].U.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 0.38 13.39 ^ B_0_0.WORD[3].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.39 ^ B_0_0.WORD[3].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.39 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[3].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.39 data arrival time |
| --------------------------------------------------------- |
| -3.63 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[3].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.98 13.02 ^ B_0_0.DEC.DEC_L1[0].U.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 0.37 13.39 ^ B_0_0.WORD[3].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.39 ^ B_0_0.WORD[3].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.39 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[3].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.39 data arrival time |
| --------------------------------------------------------- |
| -3.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[3].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.98 13.02 ^ B_0_0.DEC.DEC_L1[0].U.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 0.37 13.39 ^ B_0_0.WORD[3].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.39 ^ B_0_0.WORD[3].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.39 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[3].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.39 data arrival time |
| --------------------------------------------------------- |
| -3.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[3].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.67 12.03 ^ B_0_0.DEC.DEC_L0.AND0/Y (sky130_fd_sc_hd__nor4b_2) |
| 0.98 13.02 ^ B_0_0.DEC.DEC_L1[0].U.AND3/X (sky130_fd_sc_hd__and4b_2) |
| 0.37 13.39 ^ B_0_0.WORD[3].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.39 ^ B_0_0.WORD[3].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.39 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[3].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.39 data arrival time |
| --------------------------------------------------------- |
| -3.62 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[20].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.50 11.86 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.94 12.81 ^ B_0_0.DEC.DEC_L1[2].U.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.41 13.22 ^ B_0_0.WORD[20].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.22 ^ B_0_0.WORD[20].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.22 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[20].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.22 data arrival time |
| --------------------------------------------------------- |
| -3.45 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[20].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.50 11.86 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.94 12.81 ^ B_0_0.DEC.DEC_L1[2].U.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.41 13.22 ^ B_0_0.WORD[20].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.22 ^ B_0_0.WORD[20].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.22 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[20].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.22 data arrival time |
| --------------------------------------------------------- |
| -3.45 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[20].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.50 11.86 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.94 12.81 ^ B_0_0.DEC.DEC_L1[2].U.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.41 13.22 ^ B_0_0.WORD[20].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.22 ^ B_0_0.WORD[20].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.22 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[20].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.22 data arrival time |
| --------------------------------------------------------- |
| -3.45 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[20].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.50 11.86 ^ B_0_0.DEC.DEC_L0.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.94 12.81 ^ B_0_0.DEC.DEC_L1[2].U.AND4/X (sky130_fd_sc_hd__and4bb_2) |
| 0.41 13.21 ^ B_0_0.WORD[20].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.21 ^ B_0_0.WORD[20].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.21 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[20].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.21 data arrival time |
| --------------------------------------------------------- |
| -3.45 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[10].W.B1.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.49 11.86 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.94 12.80 ^ B_0_0.DEC.DEC_L1[1].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.41 13.21 ^ B_0_0.WORD[10].W.B1.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.21 ^ B_0_0.WORD[10].W.B1.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.21 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[10].W.B1.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.21 data arrival time |
| --------------------------------------------------------- |
| -3.44 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[10].W.B0.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.49 11.86 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.94 12.80 ^ B_0_0.DEC.DEC_L1[1].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.41 13.21 ^ B_0_0.WORD[10].W.B0.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.21 ^ B_0_0.WORD[10].W.B0.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.21 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[10].W.B0.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.21 data arrival time |
| --------------------------------------------------------- |
| -3.44 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[10].W.B3.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.49 11.86 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.94 12.80 ^ B_0_0.DEC.DEC_L1[1].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.40 13.21 ^ B_0_0.WORD[10].W.B3.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.21 ^ B_0_0.WORD[10].W.B3.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.21 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[10].W.B3.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.21 data arrival time |
| --------------------------------------------------------- |
| -3.44 slack (VIOLATED) |
| |
| |
| Startpoint: A[6] (input port clocked by CLK) |
| Endpoint: B_0_0.WORD[10].W.B2.CG |
| (rising clock gating-check end-point clocked by CLK) |
| Path Group: CLK |
| Path Type: max |
| |
| Delay Time Description |
| --------------------------------------------------------- |
| 0.00 0.00 clock CLK (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 2.00 2.00 v input external delay |
| 0.10 2.10 v A[6] (in) |
| 7.27 9.36 ^ DEC.AND0/Y (sky130_fd_sc_hd__nor3b_2) |
| 2.49 11.86 ^ B_0_0.DEC.DEC_L0.AND1/X (sky130_fd_sc_hd__and4bb_2) |
| 0.94 12.80 ^ B_0_0.DEC.DEC_L1[1].U.AND2/X (sky130_fd_sc_hd__and4bb_2) |
| 0.40 13.21 ^ B_0_0.WORD[10].W.B2.CGAND/X (sky130_fd_sc_hd__and2_1) |
| 0.00 13.21 ^ B_0_0.WORD[10].W.B2.CG/GATE (sky130_fd_sc_hd__dlclkp_1) |
| 13.21 data arrival time |
| |
| 10.00 10.00 clock CLK (rise edge) |
| 0.00 10.00 clock network delay (ideal) |
| 0.00 10.00 clock reconvergence pessimism |
| 10.00 ^ B_0_0.WORD[10].W.B2.CG/CLK (sky130_fd_sc_hd__dlclkp_1) |
| -0.23 9.77 library setup time |
| 9.77 data required time |
| --------------------------------------------------------- |
| 9.77 data required time |
| -13.21 data arrival time |
| --------------------------------------------------------- |
| -3.44 slack (VIOLATED) |
| |
| |
