Downgrade IP to Verilog 2005 to work with Icraus and Yosys

Signed-off-by: Matthew Ballance <matt.ballance@gmail.com>
9 files changed
tree: 57862414011bc674f3facfd4ca19537f30ec6b93
  1. .settings/
  2. doc/
  3. dv/
  4. etc/
  5. verilog/
  6. .cproject
  7. .gitignore
  8. .project
  9. .pydevproject
  10. bootstrap.sh
  11. LICENSE
  12. README.md
  13. requirements.txt
README.md

open_mpw_user_project

Test project for the Open MPW shuttle