commit	c964d535084f80b538002738a75b81ab355600a6	[log] [tgz]
author	Matthew Ballance <matt.ballance@gmail.com>	Wed Nov 25 09:30:53 2020 -0800
committer	Matthew Ballance <matt.ballance@gmail.com>	Wed Nov 25 09:30:53 2020 -0800
tree	62bdf429fb5592a44115ca16fd45d612dbccf74b
parent	482675d5c137e8e9a8a1b31e1348e80cf7376a3c [diff]

Moving toward a slightly larger system...

Signed-off-by: Matthew Ballance <matt.ballance@gmail.com>

.pydevproject[diff]
dv/bringup/Makefile[diff]
dv/bringup/bringup_tb.sv[diff]
dv/bringup/python/__pycache__/bringup_tb.cpython-36.pyc[Deleted - diff]
dv/bringup/python/bringup_tb.py[diff]
dv/bringup/python/bringup_tests/__init__.py[Added - diff]
dv/bringup/python/bringup_tests/__pycache__/__init__.cpython-36.pyc[Added - diff]
dv/bringup/python/bringup_tests/__pycache__/mgmt_mem_access.cpython-36.pyc[Added - diff]
dv/bringup/python/bringup_tests/la_reset_dut.py[Added - diff]
dv/bringup/python/bringup_tests/la_utils.py[Added - diff]
dv/bringup/python/bringup_tests/mgmt_mem_access.py[Added - diff]
dv/common/icarus.mk[Added - diff]
dv/common/questa.mk[Added - diff]
dv/common/vlsim.mk[diff]
etc/packages.mf[diff]
requirements.txt[diff]
rtl/spram.v[Deleted - diff]
verilog/rtl/fwpayload.v[Renamed from rtl/fwpayload.v - diff]
verilog/rtl/simple_spi_master.v[Added - diff]
verilog/rtl/simpleuart.v[Added - diff]
verilog/rtl/spram.v[Added - diff]
verilog/rtl/spram_32x256.sv[Added - diff]
verilog/rtl/user_project_wrapper.v[Renamed from rtl/user_project_wrapper.v - diff]
verilog/rtl/wb_interconnect_NxN.sv[Added - diff]

24 files changed

tree: 62bdf429fb5592a44115ca16fd45d612dbccf74b

README.md

open_mpw_user_project

Test project for the Open MPW shuttle