verilog/rtl/fwpayload/fwrisc/ve/fwrisc_rv32e/tests/fwrisc_tests.mk

FWRISC_TESTS_DIR := $(dir $(lastword $(MAKEFILE_LIST)))

ifneq (1,$(RULES))

SRC_DIRS += $(FWRISC_TESTS_DIR)/unit
SRC_DIRS += $(FWRISC_TESTS_DIR)/cpp
SRC_DIRS += $(FWRISC_TESTS_DIR)/riscv-compliance/riscv-target/spike
SRC_DIRS += $(FWRISC_TESTS_DIR)/riscv-compliance/riscv-test-env/p
SRC_DIRS += $(FWRISC_TESTS_DIR)/riscv-compliance/riscv-test-env
SRC_DIRS += $(FWRISC_TESTS_DIR)/riscv-compliance/riscv-test-suite/rv32i/src

FWRISC_TESTS_SRC := $(notdir $(wildcard $(FWRISC_TESTS_DIR)/cpp/*.cpp))

else # Rules

# $(FWRISC_TESTS_SRC:.cpp=.o) : vl_translate.d

libfwrisc_tests.o : $(FWRISC_TESTS_SRC:.cpp=.o)
	$(Q)$(LD) -r -o $@ $(FWRISC_TESTS_SRC:.cpp=.o)
	

endif