verilog/rtl/fwpayload/fwrisc/doc/imgs/exception.json

{signal: [
  {name: 'clock', wave: 'p......'},
  {name: 'state', wave: 'x=====x.', data: ['dec', 'exec', 'exception_1', 'exception_2', 'fetch']},
  {name: 'exception', wave: '0.10...'},
  {name: 'ra_addr', wave: 'x====x.', data: ['rs1','csr','csr_tmp']},
  {name: 'ra_data', wave: 'x.===x', data: ['rs1','csr','csr_tmp']},
  {name: 'rb_addr', wave: 'x====x.', data: ['zero','zero','zero']},
  {name: 'rb_data', wave: 'x.===x', data: ['zero','zero','zero']},
  {name: 'alu_op_a', wave: 'x.===x', data: ['ra_data (rs1)','ra_data (csr)','ra_data(csr_tmp)']},
  {name: 'alu_op_b', wave: 'x.===x', data: ['rb_data (zero)','rb_data (zero)','rb_data(zero)']},
  {name: 'alu_op', wave: 'x.===x', data: ['OR','OR','OR']},
  
  {name: 'rd_addr', wave: 'x.===x', data: ['badaddr','mepc','mcause']},
  {name: 'rd_data', wave: 'x.===x', data: ['addr','pc','cause']},
  {name: 'rd_wen', wave: '0.1..0'},
  
],
  config: {hscale: 4},
  head: {
  	text: "Exception"
  }
}