| {signal: [ |
| {name: 'clock', wave: 'p.....'}, |
| {name: 'state', wave: 'x====x.', data: ['dec', 'csr_1', 'exec']}, |
| {name: 'ra_addr', wave: 'x====x.', data: ['csr','rs1','X']}, |
| {name: 'ra_data', wave: 'x.===x', data: ['csr','rs1','X']}, |
| {name: 'rb_addr', wave: 'x====x.', data: ['zero','csr','X']}, |
| {name: 'rb_data', wave: 'x.===x', data: ['zero','csr','X']}, |
| {name: 'alu_op_a', wave: 'x.===x', data: ['ra_data (csr)','ra_data (rs1)','X']}, |
| {name: 'alu_op_b', wave: 'x.===x', data: ['rb_data (zero)','rb_data (csr)','X']}, |
| {name: 'alu_op', wave: 'x.===x', data: ['OR','OR']}, |
| |
| {name: 'rd_addr', wave: 'x.===x', data: ['rd','csr']}, |
| {name: 'rd_data', wave: 'x.===x', data: ['alu_out (csr)','alu_out (csr|rs1)']}, |
| {name: 'rd_wen', wave: '0.1.0'}, |
| |
| ], |
| config: {hscale: 4}, |
| head: { |
| text: "CSRRS" |
| } |
| } |