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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-019 / 706c31202f3b1c86ff2dbfe49bb0cca6dae2e331 / . / verilog / rtl / pads.v
blob: 9ce690a49107a395fce0cc03c7dc1e9dd5d5bac8 [file] [log] [blame]
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]1`ifndef TOP_ROUTING
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]2 `define USER1_ABUTMENT_PINS \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]3 .AMUXBUS_A(analog_a),\
4 .AMUXBUS_B(analog_b),\
5 .VSSA(vssa1),\
6 .VDDA(vdda1),\
7 .VSWITCH(vddio),\
8 .VDDIO_Q(vddio_q),\
9 .VCCHIB(vccd),\
10 .VDDIO(vddio),\
11 .VCCD(vccd1),\
12 .VSSIO(vssio),\
13 .VSSD(vssd1),\
14 .VSSIO_Q(vssio_q),
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]15
16 `define USER2_ABUTMENT_PINS \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]17 .AMUXBUS_A(analog_a),\
18 .AMUXBUS_B(analog_b),\
19 .VSSA(vssa2),\
20 .VDDA(vdda2),\
21 .VSWITCH(vddio),\
22 .VDDIO_Q(vddio_q),\
23 .VCCHIB(vccd),\
24 .VDDIO(vddio),\
25 .VCCD(vccd2),\
26 .VSSIO(vssio),\
27 .VSSD(vssd2),\
28 .VSSIO_Q(vssio_q),
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]29
30 `define MGMT_ABUTMENT_PINS \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]31 .AMUXBUS_A(analog_a),\
32 .AMUXBUS_B(analog_b),\
33 .VSSA(vssa),\
34 .VDDA(vdda),\
35 .VSWITCH(vddio),\
36 .VDDIO_Q(vddio_q),\
37 .VCCHIB(vccd),\
38 .VDDIO(vddio),\
39 .VCCD(vccd),\
40 .VSSIO(vssio),\
Tim Edwards21a9aac2020-10-12 22:05:18 -0400[diff] [blame]41 .VSSD(vssd),\
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]42 .VSSIO_Q(vssio_q),
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]43`else
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]44 `define USER1_ABUTMENT_PINS
45 `define USER2_ABUTMENT_PINS
46 `define MGMT_ABUTMENT_PINS
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]47`endif
48
Tim Edwardsf645a842020-10-10 21:36:49 -0400[diff] [blame]49`define HVCLAMP_PINS(H,L) \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]50 .DRN_HVC(H), \
51 .SRC_BDY_HVC(L)
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]52
Tim Edwardsf645a842020-10-10 21:36:49 -0400[diff] [blame]53`define LVCLAMP_PINS(H1,L1,H2,L2,L3) \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]54 .BDY2_B2B(L3), \
55 .DRN_LVC1(H1), \
56 .DRN_LVC2(H2), \
57 .SRC_BDY_LVC1(L1), \
58 .SRC_BDY_LVC2(L2)
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]59
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]60`define INPUT_PAD(X,Y) \
61 wire loop_``X; \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]62 sky130_ef_io__gpiov2_pad X``_pad ( \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]63 `MGMT_ABUTMENT_PINS \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]64 `ifndef TOP_ROUTING \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]65 .PAD(X), \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]66 `endif \
Tim Edwards21a9aac2020-10-12 22:05:18 -0400[diff] [blame]67 .OUT(vssd), \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]68 .OE_N(vccd), \
Tim Edwards21a9aac2020-10-12 22:05:18 -0400[diff] [blame]69 .HLD_H_N(vddio), \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]70 .ENABLE_H(porb_h), \
71 .ENABLE_INP_H(loop_``X), \
72 .ENABLE_VDDA_H(porb_h), \
73 .ENABLE_VSWITCH_H(vssa), \
74 .ENABLE_VDDIO(vccd), \
75 .INP_DIS(por), \
Tim Edwards21a9aac2020-10-12 22:05:18 -0400[diff] [blame]76 .IB_MODE_SEL(vssd), \
77 .VTRIP_SEL(vssd), \
78 .SLOW(vssd), \
79 .HLD_OVR(vssd), \
80 .ANALOG_EN(vssd), \
81 .ANALOG_SEL(vssd), \
82 .ANALOG_POL(vssd), \
83 .DM({vssd, vssd, vccd}), \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]84 .PAD_A_NOESD_H(), \
85 .PAD_A_ESD_0_H(), \
86 .PAD_A_ESD_1_H(), \
87 .IN(Y), \
88 .IN_H(), \
89 .TIE_HI_ESD(), \
Tim Edwards21a9aac2020-10-12 22:05:18 -0400[diff] [blame]90 .TIE_LO_ESD(loop_``X) )
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]91
Tim Edwardse2ef6732020-10-12 17:25:12 -0400[diff] [blame]92`define OUTPUT_PAD(X,Y,INPUT_DIS,OUT_EN_N) \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]93 wire loop_``X; \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]94 sky130_ef_io__gpiov2_pad X``_pad ( \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]95 `MGMT_ABUTMENT_PINS \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]96 `ifndef TOP_ROUTING \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]97 .PAD(X), \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]98 `endif \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]99 .OUT(Y), \
100 .OE_N(OUT_EN_N), \
101 .HLD_H_N(vddio), \
102 .ENABLE_H(porb_h), \
103 .ENABLE_INP_H(loop_``X), \
104 .ENABLE_VDDA_H(porb_h), \
105 .ENABLE_VSWITCH_H(vssa), \
106 .ENABLE_VDDIO(vccd), \
Tim Edwardse2ef6732020-10-12 17:25:12 -0400[diff] [blame]107 .INP_DIS(INPUT_DIS), \
Tim Edwards21a9aac2020-10-12 22:05:18 -0400[diff] [blame]108 .IB_MODE_SEL(vssd), \
109 .VTRIP_SEL(vssd), \
110 .SLOW(vssd), \
111 .HLD_OVR(vssd), \
112 .ANALOG_EN(vssd), \
113 .ANALOG_SEL(vssd), \
114 .ANALOG_POL(vssd), \
115 .DM({vccd, vccd, vssd}), \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]116 .PAD_A_NOESD_H(), \
117 .PAD_A_ESD_0_H(), \
118 .PAD_A_ESD_1_H(), \
119 .IN(), \
120 .IN_H(), \
121 .TIE_HI_ESD(), \
122 .TIE_LO_ESD(loop_``X))
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]123
Tim Edwardse2ef6732020-10-12 17:25:12 -0400[diff] [blame]124`define INOUT_PAD(X,Y,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]125 sky130_ef_io__gpiov2_pad X``_pad ( \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]126 `MGMT_ABUTMENT_PINS \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]127 `ifndef TOP_ROUTING \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]128 .PAD(X),\
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]129 `endif \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]130 .OUT(Y_OUT), \
131 .OE_N(OUT_EN_N), \
132 .HLD_H_N(vddio), \
133 .ENABLE_H(porb_h), \
134 .ENABLE_INP_H(loop_``X), \
135 .ENABLE_VDDA_H(porb_h), \
136 .ENABLE_VSWITCH_H(vssa), \
137 .ENABLE_VDDIO(vccd), \
Tim Edwardse2ef6732020-10-12 17:25:12 -0400[diff] [blame]138 .INP_DIS(INPUT_DIS), \
Tim Edwards21a9aac2020-10-12 22:05:18 -0400[diff] [blame]139 .IB_MODE_SEL(vssd), \
140 .VTRIP_SEL(vssd), \
141 .SLOW(vssd), \
142 .HLD_OVR(vssd), \
143 .ANALOG_EN(vssd), \
144 .ANALOG_SEL(vssd), \
145 .ANALOG_POL(vssd), \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]146 .DM(MODE), \
147 .PAD_A_NOESD_H(), \
148 .PAD_A_ESD_0_H(), \
149 .PAD_A_ESD_1_H(), \
150 .IN(Y), \
151 .IN_H(), \
152 .TIE_HI_ESD(), \
153 .TIE_LO_ESD(loop_``X) )
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]154