blob: 05ae7a19961403ffd2c2c01e98d7371961b06556 [file] [log] [blame]
Ahmed Ghazy72e52c62020-10-26 16:44:41 +02001package require openlane
2set script_dir [file dirname [file normalize [info script]]]
3
4prep -design $script_dir -tag chip_io -overwrite
5set save_path $script_dir/../..
6
7verilog_elaborate
8
9init_floorplan
10
11exec -ignorestderr python3 $::env(SCRIPTS_DIR)/padringer.py\
12 --def-netlist $::env(CURRENT_DEF)\
13 --design $::env(DESIGN_NAME)\
14 --lefs $::env(TECH_LEF) {*}$::env(GPIO_PADS_LEF)\
15 -cfg $script_dir/padframe.cfg\
16 --working-dir $::env(TMP_DIR)\
17 -o $::env(RESULTS_DIR)/floorplan/padframe.def
18
19set_def $::env(RESULTS_DIR)/floorplan/padframe.def
20
21
22label_macro_pins\
23 -lef $::env(MERGED_LEF_UNPADDED)\
24 -netlist_def $::env(CURRENT_DEF)\
25 -pad_pin_name "PAD"\
26 -extra_args {-v\
27 --map mgmt_vdda_hvclamp_pad VDDA vdda INOUT\
28 --map user1_vdda_hvclamp_pad\\\[0\\] VDDA vdda1 INOUT\
29 --map user2_vdda_hvclamp_pad VDDA vdda2 INOUT\
30 --map mgmt_vssa_hvclamp_pad VSSA vssa INOUT\
31 --map user1_vssa_hvclamp_pad\\\[0\\] VSSA vssa1 INOUT\
32 --map user2_vssa_hvclamp_pad VSSA vssa2 INOUT\
33 --map mgmt_vccd_lvclamp_pad VCCD vccd INOUT\
34 --map user1_vccd_lvclamp_pad VCCD vccd1 INOUT\
35 --map user2_vccd_lvclamp_pad VCCD vccd2 INOUT\
36 --map mgmt_vssd_lvclmap_pad VSSD vssd INOUT\
37 --map user1_vssd_lvclmap_pad VSSD vssd1 INOUT\
38 --map user2_vssd_lvclmap_pad VSSD vssd2 INOUT\
39 --map mgmt_vddio_hvclamp_pad\\\[0\\] VDDIO vddio INOUT\
40 --map mgmt_vssio_hvclamp_pad\\\[0\\] VSSIO vssio INOUT}
41
42run_magic
43
44run_magic_drc
45
46save_views -lef_path $::env(magic_result_file_tag).lef \
47 -def_path $::env(CURRENT_DEF) \
48 -gds_path $::env(magic_result_file_tag).gds \
49 -mag_path $::env(magic_result_file_tag).mag \
50 -save_path $save_path \
51 -tag $::env(RUN_TAG)
52
53
54run_magic_spice_export
55run_lvs