| Ahmed Ghazy | 7215439 | 2020-11-11 14:56:52 +0200 | [diff] [blame] | 1 | set script_dir [file dirname [file normalize [info script]]] |
| 2 | # User config | ||||
| 3 | set ::env(DESIGN_NAME) user_id_programming | ||||
| 4 | |||||
| 5 | # Change if needed | ||||
| 6 | set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/user_id_programming.v | ||||
| 7 | set ::env(SYNTH_READ_BLACKBOX_LIB) 1 | ||||
| 8 | |||||
| 9 | # Fill this | ||||
| 10 | set ::env(CLOCK_TREE_SYNTH) 0 | ||||
| 11 | |||||
| 12 | set ::env(CELL_PAD) 0 | ||||
| 13 | |||||
| 14 | set ::env(FP_CORE_UTIL) 20 | ||||
| 15 | set ::env(PL_RANDOM_GLB_PLACEMENT) 1 | ||||