Tim Edwards | cd64af5 | 2020-08-07 11:11:58 -0400 | [diff] [blame] | 1 | // Digital PLL (ring oscillator + controller) |
| 2 | // Technically this is a frequency locked loop, not a phase locked loop. |
| 3 | |
| 4 | `include "digital_pll_controller.v" |
| 5 | `include "ring_osc2x13.v" |
| 6 | |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 7 | module digital_pll( |
| 8 | `ifdef LVS |
| 9 | vdd, |
| 10 | vss, |
| 11 | `endif |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 12 | resetb, extclk_sel, osc, clockc, clockp, clockd, div, sel, dco, ext_trim); |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 13 | |
| 14 | `ifdef LVS |
| 15 | input vdd; |
| 16 | input vss; |
| 17 | `endif |
Tim Edwards | cd64af5 | 2020-08-07 11:11:58 -0400 | [diff] [blame] | 18 | |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 19 | input resetb; // Sense negative reset |
Tim Edwards | cd64af5 | 2020-08-07 11:11:58 -0400 | [diff] [blame] | 20 | input extclk_sel; // External clock select (acts as 2nd reset) |
| 21 | input osc; // Input oscillator to match |
| 22 | input [4:0] div; // PLL feedback division ratio |
| 23 | input [2:0] sel; // Core clock select |
| 24 | input dco; // Run in DCO mode |
| 25 | input [25:0] ext_trim; // External trim for DCO mode |
| 26 | |
| 27 | output clockc; // Selected core clock output |
| 28 | output [1:0] clockp; // Two 90 degree clock phases |
| 29 | output [3:0] clockd; // Divided clock (2, 4, 8, 16) |
| 30 | |
| 31 | wire [25:0] itrim; // Internally generated trim bits |
| 32 | wire [25:0] otrim; // Trim bits applied to the ring oscillator |
| 33 | wire [3:0] nint; // Internal divided down clocks |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 34 | wire reset; // Internal positive sense reset |
| 35 | wire resetbb; // Internal buffered negative sense reset |
Tim Edwards | cd64af5 | 2020-08-07 11:11:58 -0400 | [diff] [blame] | 36 | wire creset; // Controller reset |
| 37 | wire ireset; // Internal reset (external reset OR extclk_sel) |
| 38 | |
| 39 | assign ireset = reset | extclk_sel; |
| 40 | |
| 41 | // In DCO mode: Hold controller in reset and apply external trim value |
| 42 | assign itrim = (dco == 1'b0) ? otrim : ext_trim; |
| 43 | assign creset = (dco == 1'b0) ? ireset : 1'b1; |
| 44 | |
| 45 | ring_osc2x13 ringosc ( |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 46 | .reset(ireset), |
| 47 | .trim(itrim), |
| 48 | .clockp(clockp) |
Tim Edwards | cd64af5 | 2020-08-07 11:11:58 -0400 | [diff] [blame] | 49 | ); |
| 50 | |
| 51 | digital_pll_controller pll_control ( |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 52 | .reset(creset), |
| 53 | .clock(clockp[0]), |
| 54 | .osc(osc), |
| 55 | .div(div), |
| 56 | .trim(otrim) |
Tim Edwards | cd64af5 | 2020-08-07 11:11:58 -0400 | [diff] [blame] | 57 | ); |
| 58 | |
| 59 | // Select core clock output |
| 60 | assign clockc = (sel == 3'b000) ? clockp[0] : |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 61 | (sel == 3'b001) ? clockd[0] : |
| 62 | (sel == 3'b010) ? clockd[1] : |
| 63 | (sel == 3'b011) ? clockd[2] : |
| 64 | clockd[3]; |
Tim Edwards | cd64af5 | 2020-08-07 11:11:58 -0400 | [diff] [blame] | 65 | |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 66 | // Derive internal negative-sense reset from the input negative-sense reset |
Tim Edwards | cd64af5 | 2020-08-07 11:11:58 -0400 | [diff] [blame] | 67 | |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 68 | sky130_fd_sc_hd__buf_8 irbb ( |
| 69 | .A(resetb), |
| 70 | .X(resetbb) |
Tim Edwards | cd64af5 | 2020-08-07 11:11:58 -0400 | [diff] [blame] | 71 | ); |
| 72 | |
| 73 | // Create divided down clocks. The inverted output only comes |
| 74 | // with digital standard cells with inverted resets, so the |
| 75 | // reset has to be inverted as well. |
| 76 | |
Tim Edwards | ef8312e | 2020-09-22 17:20:06 -0400 | [diff] [blame] | 77 | sky130_fd_sc_hd__dfrbp_1 idiv2 ( |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 78 | .CLK(clockp[1]), |
| 79 | .D(clockd[0]), |
| 80 | .Q(nint[0]), |
| 81 | .Q_N(clockd[0]), |
| 82 | .RESET_B(resetbb) |
Tim Edwards | cd64af5 | 2020-08-07 11:11:58 -0400 | [diff] [blame] | 83 | ); |
| 84 | |
Tim Edwards | ef8312e | 2020-09-22 17:20:06 -0400 | [diff] [blame] | 85 | sky130_fd_sc_hd__dfrbp_1 idiv4 ( |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 86 | .CLK(clockd[0]), |
| 87 | .D(clockd[1]), |
| 88 | .Q(nint[1]), |
| 89 | .Q_N(clockd[1]), |
| 90 | .RESET_B(resetbb) |
Tim Edwards | cd64af5 | 2020-08-07 11:11:58 -0400 | [diff] [blame] | 91 | ); |
| 92 | |
Tim Edwards | ef8312e | 2020-09-22 17:20:06 -0400 | [diff] [blame] | 93 | sky130_fd_sc_hd__dfrbp_1 idiv8 ( |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 94 | .CLK(clockd[1]), |
| 95 | .D(clockd[2]), |
| 96 | .Q(nint[2]), |
| 97 | .Q_N(clockd[2]), |
| 98 | .RESET_B(resetbb) |
Tim Edwards | cd64af5 | 2020-08-07 11:11:58 -0400 | [diff] [blame] | 99 | ); |
| 100 | |
Tim Edwards | ef8312e | 2020-09-22 17:20:06 -0400 | [diff] [blame] | 101 | sky130_fd_sc_hd__dfrbp_1 idiv16 ( |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 102 | .CLK(clockd[2]), |
| 103 | .D(clockd[3]), |
| 104 | .Q(nint[3]), |
| 105 | .Q_N(clockd[3]), |
| 106 | .RESET_B(resetbb) |
Tim Edwards | cd64af5 | 2020-08-07 11:11:58 -0400 | [diff] [blame] | 107 | ); |
| 108 | endmodule |