blob: 4dcf1117306599dbe3fe8755b91f8844f3bbbf39 [file] [log] [blame]
Tim Edwards53d92182020-10-11 21:47:40 -04001/*----------------------------------------------------------------------*/
2/* Buffers protecting the management region from the user region. */
3/* This mainly consists of tristate buffers that are enabled by a */
4/* "logic 1" output connected to the user's VCCD domain. This ensures */
5/* that the buffer is disabled and the output high-impedence when the */
6/* user 1.8V supply is absent. */
7/*----------------------------------------------------------------------*/
8/* Because there is no tristate buffer with a non-inverted enable, a */
9/* tristate inverter with non-inverted enable is used in series with */
10/* another (normal) inverter. */
11/*----------------------------------------------------------------------*/
12/* For the sake of placement/routing, one conb (logic 1) cell is used */
13/* for every buffer. */
14/*----------------------------------------------------------------------*/
15
16module mgmt_protect (
Tim Edwards53d92182020-10-11 21:47:40 -040017 inout vccd,
18 inout vssd,
19 inout vccd1,
20 inout vssd1,
Tim Edwards32d05422020-10-19 19:43:52 -040021 inout vccd2,
22 inout vssd2,
Tim Edwards05ad4fc2020-10-19 22:12:33 -040023 inout vdda1,
24 inout vssa1,
25 inout vdda2,
26 inout vssa2,
Tim Edwards53d92182020-10-11 21:47:40 -040027
28 input caravel_clk,
Tim Edwards7a8cbb12020-10-12 11:32:11 -040029 input caravel_clk2,
Tim Edwards53d92182020-10-11 21:47:40 -040030 input caravel_rstn,
31 input mprj_cyc_o_core,
32 input mprj_stb_o_core,
33 input mprj_we_o_core,
34 input [3:0] mprj_sel_o_core,
35 input [31:0] mprj_adr_o_core,
36 input [31:0] mprj_dat_o_core,
37 input [127:0] la_output_core,
38 input [127:0] la_oen,
39
40 output user_clock,
Tim Edwards7a8cbb12020-10-12 11:32:11 -040041 output user_clock2,
Tim Edwards53d92182020-10-11 21:47:40 -040042 output user_resetn,
43 output mprj_cyc_o_user,
44 output mprj_stb_o_user,
45 output mprj_we_o_user,
46 output [3:0] mprj_sel_o_user,
47 output [31:0] mprj_adr_o_user,
48 output [31:0] mprj_dat_o_user,
Tim Edwards32d05422020-10-19 19:43:52 -040049 output [127:0] la_data_in_mprj,
Tim Edwards05ad4fc2020-10-19 22:12:33 -040050 output user1_vcc_powergood,
51 output user2_vcc_powergood,
52 output user1_vdd_powergood,
53 output user2_vdd_powergood
Tim Edwards53d92182020-10-11 21:47:40 -040054);
55
Tim Edwards32d05422020-10-19 19:43:52 -040056 wire [74:0] mprj_logic1;
57 wire mprj2_logic1;
Tim Edwards05ad4fc2020-10-19 22:12:33 -040058
59 wire mprj_vdd_logic1_h;
60 wire mprj2_vdd_logic1_h;
61 wire mprj_vdd_logic1;
62 wire mprj2_vdd_logic1;
63
64 wire user1_vcc_powergood;
65 wire user2_vcc_powergood;
66 wire user1_vdd_powergood;
67 wire user2_vdd_powergood;
Tim Edwards53d92182020-10-11 21:47:40 -040068
Tim Edwards32d05422020-10-19 19:43:52 -040069 sky130_fd_sc_hd__conb_1 mprj_logic_high [74:0] (
Tim Edwards53d92182020-10-11 21:47:40 -040070 .VPWR(vccd1),
71 .VGND(vssd1),
72 .VPB(vccd1),
73 .VNB(vssd1),
Tim Edwards53d92182020-10-11 21:47:40 -040074 .HI(mprj_logic1),
75 .LO()
76 );
77
Tim Edwards32d05422020-10-19 19:43:52 -040078 sky130_fd_sc_hd__conb_1 mprj2_logic_high (
79 .VPWR(vccd2),
80 .VGND(vssd2),
81 .VPB(vccd2),
82 .VNB(vssd2),
83 .HI(mprj2_logic1),
84 .LO()
85 );
86
Tim Edwards05ad4fc2020-10-19 22:12:33 -040087 // Logic high in the VDDA (3.3V) domains
88
89 sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl (
90 .VPWR(vdda1),
91 .VGND(vssa1),
92 .VPB(vdda1),
93 .VNB(vssa1),
94 .HI(mprj_vdd_logic1_h),
95 .LO()
96 );
97
98 sky130_fd_sc_hvl__conb_1 mprj2_logic_high_hvl (
99 .VPWR(vdda2),
100 .VGND(vssa2),
101 .VPB(vdda2),
102 .VNB(vssa2),
103 .HI(mprj2_vdd_logic1_h),
104 .LO()
105 );
106
107 // Level shift the logic high signals into the 1.8V domain
108
109 sky130_fd_sc_hvl__lsbufhv2lv mprj_logic_high_lv (
110 .VPWR(vdda1),
111 .VGND(vssd),
112 .LVPWR(vccd),
113 .VPB(vdda1),
114 .VNB(vssd),
115 .X(mprj_vdd_logic1),
116 .A(mprj_vdd_logic1_h)
117 );
118
119 sky130_fd_sc_hvl__lsbufhv2lv mprj2_logic_high_lv (
120 .VPWR(vdda2),
121 .VGND(vssd),
122 .LVPWR(vccd),
123 .VPB(vdda2),
124 .VNB(vssd),
125 .X(mprj2_vdd_logic1),
126 .A(mprj2_vdd_logic1_h)
127 );
Tim Edwards32d05422020-10-19 19:43:52 -0400128
Tim Edwards53d92182020-10-11 21:47:40 -0400129 sky130_fd_sc_hd__einvp_8 mprj_rstn_buf (
Tim Edwards53d92182020-10-11 21:47:40 -0400130 .VPWR(vccd),
131 .VGND(vssd),
132 .VPB(vccd),
133 .VNB(vssd),
Tim Edwards53d92182020-10-11 21:47:40 -0400134 .Z(user_resetn),
135 .A(~caravel_rstn),
136 .TE(mprj_logic1[0])
137 );
138
139 sky130_fd_sc_hd__einvp_8 mprj_clk_buf (
Tim Edwards53d92182020-10-11 21:47:40 -0400140 .VPWR(vccd),
141 .VGND(vssd),
142 .VPB(vccd),
143 .VNB(vssd),
Tim Edwards53d92182020-10-11 21:47:40 -0400144 .Z(user_clock),
145 .A(~caravel_clk),
146 .TE(mprj_logic1[1])
147 );
148
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400149 sky130_fd_sc_hd__einvp_8 mprj_clk2_buf (
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400150 .VPWR(vccd),
151 .VGND(vssd),
152 .VPB(vccd),
153 .VNB(vssd),
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400154 .Z(user_clock2),
155 .A(~caravel_clk2),
156 .TE(mprj_logic1[2])
157 );
158
Tim Edwards53d92182020-10-11 21:47:40 -0400159 sky130_fd_sc_hd__einvp_8 mprj_cyc_buf (
Tim Edwards53d92182020-10-11 21:47:40 -0400160 .VPWR(vccd),
161 .VGND(vssd),
162 .VPB(vccd),
163 .VNB(vssd),
Tim Edwards53d92182020-10-11 21:47:40 -0400164 .Z(mprj_cyc_o_user),
165 .A(~mprj_cyc_o_core),
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400166 .TE(mprj_logic1[3])
Tim Edwards53d92182020-10-11 21:47:40 -0400167 );
168
169 sky130_fd_sc_hd__einvp_8 mprj_stb_buf (
Tim Edwards53d92182020-10-11 21:47:40 -0400170 .VPWR(vccd),
171 .VGND(vssd),
172 .VPB(vccd),
173 .VNB(vssd),
Tim Edwards53d92182020-10-11 21:47:40 -0400174 .Z(mprj_stb_o_user),
175 .A(~mprj_stb_o_core),
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400176 .TE(mprj_logic1[4])
Tim Edwards53d92182020-10-11 21:47:40 -0400177 );
178
179 sky130_fd_sc_hd__einvp_8 mprj_we_buf (
Tim Edwards53d92182020-10-11 21:47:40 -0400180 .VPWR(vccd),
181 .VGND(vssd),
182 .VPB(vccd),
183 .VNB(vssd),
Tim Edwards53d92182020-10-11 21:47:40 -0400184 .Z(mprj_we_o_user),
185 .A(~mprj_we_o_core),
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400186 .TE(mprj_logic1[5])
Tim Edwards53d92182020-10-11 21:47:40 -0400187 );
188
189 sky130_fd_sc_hd__einvp_8 mprj_sel_buf [3:0] (
Tim Edwards53d92182020-10-11 21:47:40 -0400190 .VPWR(vccd),
191 .VGND(vssd),
192 .VPB(vccd),
193 .VNB(vssd),
Tim Edwards53d92182020-10-11 21:47:40 -0400194 .Z(mprj_sel_o_user),
195 .A(~mprj_sel_o_core),
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400196 .TE(mprj_logic1[9:6])
Tim Edwards53d92182020-10-11 21:47:40 -0400197 );
198
199 sky130_fd_sc_hd__einvp_8 mprj_adr_buf [31:0] (
Tim Edwards53d92182020-10-11 21:47:40 -0400200 .VPWR(vccd),
201 .VGND(vssd),
202 .VPB(vccd),
203 .VNB(vssd),
Tim Edwards53d92182020-10-11 21:47:40 -0400204 .Z(mprj_adr_o_user),
205 .A(~mprj_adr_o_core),
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400206 .TE(mprj_logic1[41:10])
Tim Edwards53d92182020-10-11 21:47:40 -0400207 );
208
209 sky130_fd_sc_hd__einvp_8 mprj_dat_buf [31:0] (
Tim Edwards53d92182020-10-11 21:47:40 -0400210 .VPWR(vccd),
211 .VGND(vssd),
212 .VPB(vccd),
213 .VNB(vssd),
Tim Edwards53d92182020-10-11 21:47:40 -0400214 .Z(mprj_dat_o_user),
215 .A(~mprj_dat_o_core),
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400216 .TE(mprj_logic1[73:42])
Tim Edwards53d92182020-10-11 21:47:40 -0400217 );
218
219 /* The LA buffers are controlled from the user side, so */
220 /* it is only necessary to make sure that the function */
221 /* is inverting the OEB signal and using positive-sense */
222 /* enable, so that the buffer is disabled on user-side */
223 /* power-down of vccd1. */
224
225 sky130_fd_sc_hd__einvp_8 la_buf [127:0] (
Tim Edwards53d92182020-10-11 21:47:40 -0400226 .VPWR(vccd),
227 .VGND(vssd),
228 .VPB(vccd),
229 .VNB(vssd),
Tim Edwards53d92182020-10-11 21:47:40 -0400230 .Z(la_data_in_mprj),
231 .A(~la_output_core),
232 .TE(~la_oen)
233 );
234
Tim Edwards32d05422020-10-19 19:43:52 -0400235 /* The conb cell output is a resistive connection directly to */
236 /* the power supply, so when returning the user1_powergood */
237 /* signal, make sure that it is buffered properly. */
238
239 sky130_fd_sc_hd__buf_8 mprj_pwrgood (
240 .VPWR(vccd),
241 .VGND(vssd),
242 .VPB(vccd),
243 .VNB(vssd),
244 .A(mprj_logic1[74]),
Tim Edwards05ad4fc2020-10-19 22:12:33 -0400245 .X(user1_vcc_powergood)
Tim Edwards32d05422020-10-19 19:43:52 -0400246 );
247
248 sky130_fd_sc_hd__buf_8 mprj2_pwrgood (
249 .VPWR(vccd),
250 .VGND(vssd),
251 .VPB(vccd),
252 .VNB(vssd),
Tim Edwards05ad4fc2020-10-19 22:12:33 -0400253 .A(mprj2_logic1),
254 .X(user2_vcc_powergood)
Tim Edwards32d05422020-10-19 19:43:52 -0400255 );
256
Tim Edwards05ad4fc2020-10-19 22:12:33 -0400257 sky130_fd_sc_hd__buf_8 mprj_vdd_pwrgood (
258 .VPWR(vccd),
259 .VGND(vssd),
260 .VPB(vccd),
261 .VNB(vssd),
262 .A(mprj_vdd_logic1),
263 .X(user_vdd_powergood)
264 );
265
266 sky130_fd_sc_hd__buf_8 mprj2_vdd_pwrgood (
267 .VPWR(vccd),
268 .VGND(vssd),
269 .VPB(vccd),
270 .VNB(vssd),
271 .A(mprj2_vdd_logic1),
272 .X(user2_vdd_powergood)
273 );
Tim Edwards53d92182020-10-11 21:47:40 -0400274endmodule