Caravel 2nd phase (branch phase2): First pass at removing the analog
signals left over from Raven/Ravenna but not used on StriVe. Reduced
the GPIO for the management area to 2 bits. Removed additional unused
signals, removed the controls to the deleted analog signals, and
reduced the remaining controls. Renamed the digital libraries for
the sky130 Google/SkyWater naming conventions. Work in progress; much
more left to do.
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index af27f99..ab1ff53 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -53,12 +53,12 @@
input resetn,
// Memory mapped I/O signals
- output [15:0] gpio_out_pad, // Connect to out on gpio pad
- input [15:0] gpio_in_pad, // Connect to in on gpio pad
- output [15:0] gpio_mode0_pad, // Connect to dm[0] on gpio pad
- output [15:0] gpio_mode1_pad, // Connect to dm[2] on gpio pad
- output [15:0] gpio_outenb_pad, // Connect to oe_n on gpio pad
- output [15:0] gpio_inenb_pad, // Connect to inp_dis on gpio pad
+ output [1:0] gpio_out_pad, // Connect to out on gpio pad
+ input [1:0] gpio_in_pad, // Connect to in on gpio pad
+ output [1:0] gpio_mode0_pad, // Connect to dm[0] on gpio pad
+ output [1:0] gpio_mode1_pad, // Connect to dm[2] on gpio pad
+ output [1:0] gpio_outenb_pad, // Connect to oe_n on gpio pad
+ output [1:0] gpio_inenb_pad, // Connect to inp_dis on gpio pad
// LA signals
input [127:0] la_input, // From Mega-Project to cpu
@@ -76,43 +76,8 @@
output [MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
output [MPRJ_IO_PADS*3-1:0] mprj_io_dm,
- output adc0_ena,
- output adc0_convert,
- input [9:0] adc0_data,
- input adc0_done,
- output adc0_clk,
- output [1:0] adc0_inputsrc,
- output adc1_ena,
- output adc1_convert,
- output adc1_clk,
- output [1:0] adc1_inputsrc,
- input [9:0] adc1_data,
- input adc1_done,
-
- output dac_ena,
- output [9:0] dac_value,
-
- output analog_out_sel, // Analog output select (DAC or bandgap)
- output opamp_ena, // Op-amp enable for analog output
- output opamp_bias_ena, // Op-amp bias enable for analog output
- output bg_ena, // Bandgap enable
-
- output comp_ena,
- output [1:0] comp_ninputsrc,
- output [1:0] comp_pinputsrc,
- output rcosc_ena,
-
- output overtemp_ena,
- input overtemp,
- input rcosc_in, // RC oscillator output
- input xtal_in, // crystal oscillator output
- input comp_in, // comparator output
- input spi_sck,
-
input [7:0] spi_ro_config,
- input spi_ro_xtal_ena,
- input spi_ro_reg_ena,
- input spi_ro_pll_dco_ena,
+ input spi_ro_pll_dco_ena,
input [4:0] spi_ro_pll_div,
input [2:0] spi_ro_pll_sel,
input [25:0] spi_ro_pll_trim,
@@ -163,13 +128,13 @@
// WB MI A (Mega project)
input mprj_ack_i,
- input [31:0] mprj_dat_i,
+ input [31:0] mprj_dat_i,
output mprj_cyc_o,
- output mprj_stb_o,
- output mprj_we_o,
- output [3:0] mprj_sel_o,
- output [31:0] mprj_adr_o,
- output [31:0] mprj_dat_o,
+ output mprj_stb_o,
+ output mprj_we_o,
+ output [3:0] mprj_sel_o,
+ output [31:0] mprj_adr_o,
+ output [31:0] mprj_dat_o,
// WB MI B (xbar)
input [31:0] xbar_dat_i,
@@ -279,129 +244,36 @@
};
// memory-mapped I/O control registers
- wire [15:0] gpio_pullup; // Intermediate GPIO pullup
- wire [15:0] gpio_pulldown; // Intermediate GPIO pulldown
- wire [15:0] gpio_outenb; // Intermediate GPIO out enable (bar)
- wire [15:0] gpio_out; // Intermediate GPIO output
+ wire [1:0] gpio_pullup; // Intermediate GPIO pullup
+ wire [1:0] gpio_pulldown; // Intermediate GPIO pulldown
+ wire [1:0] gpio_outenb; // Intermediate GPIO out enable (bar)
+ wire [1:0] gpio_out; // Intermediate GPIO output
- wire [15:0] gpio; // GPIO output data
- wire [15:0] gpio_pu; // GPIO pull-up enable
- wire [15:0] gpio_pd; // GPIO pull-down enable
- wire [15:0] gpio_oeb; // GPIO output enable (sense negative)
+ wire [1:0] gpio; // GPIO output data
+ wire [1:0] gpio_pu; // GPIO pull-up enable
+ wire [1:0] gpio_pd; // GPIO pull-down enable
+ wire [1:0] gpio_oeb; // GPIO output enable (sense negative)
- wire [1:0] rcosc_output_dest; // RC oscillator output destination
- wire [1:0] overtemp_dest; // Over-temperature alarm destination
- wire [1:0] pll_output_dest; // PLL clock output destination
- wire [1:0] xtal_output_dest; // Crystal oscillator output destination
- wire [1:0] trap_output_dest; // Trap signal output destination
- wire [1:0] irq_7_inputsrc; // IRQ 5 source
- wire [1:0] irq_8_inputsrc; // IRQ 6 source
-
- // Analgo registers (not-used)
- reg adc0_ena; // ADC0 enable
- reg adc0_convert; // ADC0 convert
- reg [1:0] adc0_clksrc; // ADC0 clock source
- reg [1:0] adc0_inputsrc; // ADC0 input source
- reg adc1_ena; // ADC1 enable
- reg adc1_convert; // ADC1 convert
- reg [1:0] adc1_clksrc; // ADC1 clock source
- reg [1:0] adc1_inputsrc; // ADC1 input source
- reg dac_ena; // DAC enable
- reg [9:0] dac_value; // DAC output value
- reg comp_ena; // Comparator enable
- reg [1:0] comp_ninputsrc; // Comparator negative input source
- reg [1:0] comp_pinputsrc; // Comparator positive input source
- reg [1:0] comp_output_dest; // Comparator output destination
-
- reg analog_out_sel; // Analog output select
- reg opamp_ena; // Analog output op-amp enable
- reg opamp_bias_ena; // Analog output op-amp bias enable
- reg bg_ena; // Bandgap enable
- wire adc0_clk; // ADC0 clock (multiplexed)
- wire adc1_clk; // ADC1 clock (multiplexed)
-
- // ADC clock assignments
- assign adc0_clk = (adc0_clksrc == 2'b00) ? rcosc_in :
- (adc0_clksrc == 2'b01) ? spi_sck :
- (adc0_clksrc == 2'b10) ? xtal_in :
- ext_clk;
-
- assign adc1_clk = (adc1_clksrc == 2'b00) ? rcosc_in :
- (adc1_clksrc == 2'b01) ? spi_sck :
- (adc1_clksrc == 2'b10) ? xtal_in :
- ext_clk;
+ wire pll_output_dest; // PLL clock output destination
+ wire trap_output_dest; // Trap signal output destination
+ wire irq_7_inputsrc; // IRQ 7 source
+ wire irq_8_inputsrc; // IRQ 8 source
// GPIO assignments
- assign gpio_out[0] = (comp_output_dest == 2'b01) ? comp_in : gpio[0];
- assign gpio_out[1] = (comp_output_dest == 2'b10) ? comp_in : gpio[1];
- assign gpio_out[2] = (rcosc_output_dest == 2'b01) ? rcosc_in : gpio[2];
- assign gpio_out[3] = (rcosc_output_dest == 2'b10) ? rcosc_in : gpio[3];
- assign gpio_out[4] = (rcosc_output_dest == 2'b11) ? rcosc_in : gpio[4];
- assign gpio_out[5] = (xtal_output_dest == 2'b01) ? xtal_in : gpio[5];
- assign gpio_out[6] = (xtal_output_dest == 2'b10) ? xtal_in : gpio[6];
- assign gpio_out[7] = (xtal_output_dest == 2'b11) ? xtal_in : gpio[7];
- assign gpio_out[8] = (pll_output_dest == 2'b01) ? pll_clk : gpio[8];
- assign gpio_out[9] = (pll_output_dest == 2'b10) ? pll_clk : gpio[9];
- assign gpio_out[10] = (pll_output_dest == 2'b11) ? clk : gpio[10];
- assign gpio_out[11] = (trap_output_dest == 2'b01) ? trap : gpio[11];
- assign gpio_out[12] = (trap_output_dest == 2'b10) ? trap : gpio[12];
- assign gpio_out[13] = (trap_output_dest == 2'b11) ? trap : gpio[13];
- assign gpio_out[14] = (overtemp_dest == 2'b01) ? overtemp : gpio[14];
- assign gpio_out[15] = (overtemp_dest == 2'b10) ? overtemp : gpio[15];
+ assign gpio_out[0] = (pll_output_dest == 1'b1) ? pll_clk : gpio[0];
+ assign gpio_out[1] = (trap_output_dest == 1'b1) ? trap : gpio[1];
- assign gpio_outenb[0] = (comp_output_dest == 2'b00) ? gpio_oeb[0] : 1'b0;
- assign gpio_outenb[1] = (comp_output_dest == 2'b00) ? gpio_oeb[1] : 1'b0;
- assign gpio_outenb[2] = (rcosc_output_dest == 2'b00) ? gpio_oeb[2] : 1'b0;
- assign gpio_outenb[3] = (rcosc_output_dest == 2'b00) ? gpio_oeb[3] : 1'b0;
- assign gpio_outenb[4] = (rcosc_output_dest == 2'b00) ? gpio_oeb[4] : 1'b0;
- assign gpio_outenb[5] = (xtal_output_dest == 2'b00) ? gpio_oeb[5] : 1'b0;
- assign gpio_outenb[6] = (xtal_output_dest == 2'b00) ? gpio_oeb[6] : 1'b0;
- assign gpio_outenb[7] = (xtal_output_dest == 2'b00) ? gpio_oeb[7] : 1'b0;
- assign gpio_outenb[8] = (pll_output_dest == 2'b00) ? gpio_oeb[8] : 1'b0;
- assign gpio_outenb[9] = (pll_output_dest == 2'b00) ? gpio_oeb[9] : 1'b0;
- assign gpio_outenb[10] = (pll_output_dest == 2'b00) ? gpio_oeb[10] : 1'b0;
- assign gpio_outenb[11] = (trap_output_dest == 2'b00) ? gpio_oeb[11] : 1'b0;
- assign gpio_outenb[12] = (trap_output_dest == 2'b00) ? gpio_oeb[12] : 1'b0;
- assign gpio_outenb[13] = (trap_output_dest == 2'b00) ? gpio_oeb[13] : 1'b0;
- assign gpio_outenb[14] = (overtemp_dest == 2'b00) ? gpio_oeb[14] : 1'b0;
- assign gpio_outenb[15] = (overtemp_dest == 2'b00) ? gpio_oeb[15] : 1'b0;
+ assign gpio_outenb[0] = (pll_output_dest == 1'b0) ? gpio_oeb[0] : 1'b0;
+ assign gpio_outenb[1] = (trap_output_dest == 1'b0) ? gpio_oeb[1] : 1'b0;
- assign gpio_pullup[0] = (comp_output_dest == 2'b00) ? gpio_pu[0] : 1'b0;
- assign gpio_pullup[1] = (comp_output_dest == 2'b00) ? gpio_pu[1] : 1'b0;
- assign gpio_pullup[2] = (rcosc_output_dest == 2'b00) ? gpio_pu[2] : 1'b0;
- assign gpio_pullup[3] = (rcosc_output_dest == 2'b00) ? gpio_pu[3] : 1'b0;
- assign gpio_pullup[4] = (rcosc_output_dest == 2'b00) ? gpio_pu[4] : 1'b0;
- assign gpio_pullup[5] = (xtal_output_dest == 2'b00) ? gpio_pu[5] : 1'b0;
- assign gpio_pullup[6] = (xtal_output_dest == 2'b00) ? gpio_pu[6] : 1'b0;
- assign gpio_pullup[7] = (xtal_output_dest == 2'b00) ? gpio_pu[7] : 1'b0;
- assign gpio_pullup[8] = (pll_output_dest == 2'b00) ? gpio_pu[8] : 1'b0;
- assign gpio_pullup[9] = (pll_output_dest == 2'b00) ? gpio_pu[9] : 1'b0;
- assign gpio_pullup[10] = (pll_output_dest == 2'b00) ? gpio_pu[10] : 1'b0;
- assign gpio_pullup[11] = (trap_output_dest == 2'b00) ? gpio_pu[11] : 1'b0;
- assign gpio_pullup[12] = (trap_output_dest == 2'b00) ? gpio_pu[12] : 1'b0;
- assign gpio_pullup[13] = (trap_output_dest == 2'b00) ? gpio_pu[13] : 1'b0;
- assign gpio_pullup[14] = (overtemp_dest == 2'b00) ? gpio_pu[14] : 1'b0;
- assign gpio_pullup[15] = (overtemp_dest == 2'b00) ? gpio_pu[15] : 1'b0;
+ assign gpio_pullup[0] = (pll_output_dest == 1'b0) ? gpio_pu[0] : 1'b0;
+ assign gpio_pullup[1] = (trap_output_dest == 1'b0) ? gpio_pu[1] : 1'b0;
- assign gpio_pulldown[0] = (comp_output_dest == 2'b00) ? gpio_pd[0] : 1'b0;
- assign gpio_pulldown[1] = (comp_output_dest == 2'b00) ? gpio_pd[1] : 1'b0;
- assign gpio_pulldown[2] = (rcosc_output_dest == 2'b00) ? gpio_pd[2] : 1'b0;
- assign gpio_pulldown[3] = (rcosc_output_dest == 2'b00) ? gpio_pd[3] : 1'b0;
- assign gpio_pulldown[4] = (rcosc_output_dest == 2'b00) ? gpio_pd[4] : 1'b0;
- assign gpio_pulldown[5] = (xtal_output_dest == 2'b00) ? gpio_pd[5] : 1'b0;
- assign gpio_pulldown[6] = (xtal_output_dest == 2'b00) ? gpio_pd[6] : 1'b0;
- assign gpio_pulldown[7] = (xtal_output_dest == 2'b00) ? gpio_pd[7] : 1'b0;
- assign gpio_pulldown[8] = (pll_output_dest == 2'b00) ? gpio_pd[8] : 1'b0;
- assign gpio_pulldown[9] = (pll_output_dest == 2'b00) ? gpio_pd[9] : 1'b0;
- assign gpio_pulldown[10] = (pll_output_dest == 2'b00) ? gpio_pd[10] : 1'b0;
- assign gpio_pulldown[11] = (trap_output_dest == 2'b00) ? gpio_pd[11] : 1'b0;
- assign gpio_pulldown[12] = (trap_output_dest == 2'b00) ? gpio_pd[12] : 1'b0;
- assign gpio_pulldown[13] = (trap_output_dest == 2'b00) ? gpio_pd[13] : 1'b0;
- assign gpio_pulldown[14] = (overtemp_dest == 2'b00) ? gpio_pd[14] : 1'b0;
- assign gpio_pulldown[15] = (overtemp_dest == 2'b00) ? gpio_pd[15] : 1'b0;
+ assign gpio_pulldown[0] = (pll_output_dest == 1'b0) ? gpio_pd[0] : 1'b0;
+ assign gpio_pulldown[1] = (trap_output_dest == 1'b0) ? gpio_pd[1] : 1'b0;
- // Convert GPIO signals to s8 pad signals
- convert_gpio_sigs convert_gpio_bit [15:0] (
+ // Convert GPIO signals to sky130_fd_io pad signals
+ convert_gpio_sigs convert_gpio_bit [1:0] (
.gpio_out(gpio_out),
.gpio_outenb(gpio_outenb),
.gpio_pu(gpio_pullup),
@@ -432,15 +304,10 @@
wire irq_stall;
wire irq_uart;
- assign irq_7 = (irq_7_inputsrc == 2'b01) ? gpio_in_pad[0] :
- (irq_7_inputsrc == 2'b10) ? gpio_in_pad[1] :
- (irq_7_inputsrc == 2'b11) ? gpio_in_pad[2] : 1'b0;
- assign irq_8 = (irq_8_inputsrc == 2'b01) ? gpio_in_pad[3] :
- (irq_8_inputsrc == 2'b10) ? gpio_in_pad[4] :
- (irq_8_inputsrc == 2'b11) ? gpio_in_pad[5] : 1'b0;
-
assign irq_uart = 0;
assign irq_stall = 0;
+ assign irq_7 = (irq_7_inputsrc == 1'b1) ? gpio_in_pad[0] : 1'b0;
+ assign irq_8 = (irq_8_inputsrc == 1'b1) ? gpio_in_pad[1] : 1'b0;
always @* begin
irq = 0;
@@ -450,51 +317,8 @@
irq[6] = irq_spi;
irq[7] = irq_7;
irq[8] = irq_8;
- irq[9] = comp_output_dest[0] & comp_output_dest[1] & comp_in;
- irq[10] = overtemp_dest[0] & overtemp_dest[1] & overtemp;
end
- // wire mem_valid;
- // wire mem_instr;
- // wire mem_ready;
- // wire [31:0] mem_addr;
- // wire [31:0] mem_wdata;
- // wire [3:0] mem_wstrb;
- // wire [31:0] mem_rdata;
-
- // wire spimem_ready;
- // wire [31:0] spimem_rdata;
-
- // reg ram_ready;
- // wire [31:0] ram_rdata;
-
- // assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
- // assign iomem_wstrb = mem_wstrb;
- // assign iomem_addr = mem_addr;
- // assign iomem_wdata = mem_wdata;
-
- // wire spimemio_cfgreg_sel = mem_valid && (mem_addr == 32'h 0200_0000);
- // wire [31:0] spimemio_cfgreg_do;
-
- // wire simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004);
- // wire [31:0] simpleuart_reg_div_do;
-
- // wire simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008);
- // wire [31:0] simpleuart_reg_dat_do;
- // wire simpleuart_reg_dat_wait;
-
- // Akin to the slave ack ?
- // assign mem_ready = (iomem_valid && iomem_ready) || spimem_ready || ram_ready || spimemio_cfgreg_sel ||
- // simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait);
-
- // Akin to wb_intercon -- mem_rdata like cpu_dat_i
- // assign mem_rdata = (iomem_valid && iomem_ready) ? iomem_rdata : spimem_ready ? spimem_rdata : ram_ready ? ram_rdata :
- // spimemio_cfgreg_sel ? spimemio_cfgreg_do : simpleuart_reg_div_sel ? simpleuart_reg_div_do :
- // simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000;
-
- wire wb_clk_i;
- wire wb_rst_i;
-
// Assumption : no syscon module and wb_clk is the clock coming from the chip pin ?
assign wb_clk_i = clk;
assign wb_rst_i = ~resetn; // Redundant
@@ -707,16 +531,10 @@
sysctrl_wb #(
.BASE_ADR(SYS_BASE_ADR),
- .OSC_ENA(OSC_ENA),
- .OSC_OUT(OSC_OUT),
- .XTAL_OUT(XTAL_OUT),
.PLL_OUT(PLL_OUT),
.TRAP_OUT(TRAP_OUT),
.IRQ7_SRC(IRQ7_SRC),
- .IRQ8_SRC(IRQ8_SRC),
- .OVERTEMP_ENA(OVERTEMP_ENA),
- .OVERTEMP_DATA(OVERTEMP_DATA),
- .OVERTEMP_OUT(OVERTEMP_OUT)
+ .IRQ8_SRC(IRQ8_SRC)
) sysctrl (
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
@@ -731,16 +549,10 @@
.wb_ack_o(sys_ack_o),
.wb_dat_o(sys_dat_o),
- .overtemp(overtemp),
- .rcosc_ena(rcosc_ena),
- .rcosc_output_dest(rcosc_output_dest),
- .xtal_output_dest(xtal_output_dest),
.pll_output_dest(pll_output_dest),
.trap_output_dest(trap_output_dest),
.irq_7_inputsrc(irq_7_inputsrc),
- .irq_8_inputsrc(irq_8_inputsrc),
- .overtemp_ena(overtemp_ena),
- .overtemp_dest(overtemp_dest)
+ .irq_8_inputsrc(irq_8_inputsrc)
);
// Logic Analyzer
@@ -851,50 +663,6 @@
.wbs_ack_i({ xbar_ack_i, sys_ack_o, spi_sys_ack_o, spimemio_cfg_ack_o, mprj_ack_i, mprj_ctrl_ack_o, la_ack_o, gpio_ack_o, uart_ack_o, spimemio_flash_ack_o, mem_ack_o })
);
- // Akin to ram ack
- // always @(posedge clk)
- // ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
-
- always @(posedge clk) begin
- if (!resetn) begin
- adc0_ena <= 0;
- adc0_convert <= 0;
- adc0_clksrc <= 0;
- adc0_inputsrc <= 0;
- adc1_ena <= 0;
- adc1_convert <= 0;
- adc1_clksrc <= 0;
- adc1_inputsrc <= 0;
- dac_ena <= 0;
- dac_value <= 0;
- comp_ena <= 0;
- comp_ninputsrc <= 0;
- comp_pinputsrc <= 0;
- comp_output_dest <= 0;
- analog_out_sel <= 0;
- opamp_ena <= 0;
- opamp_bias_ena <= 0;
- bg_ena <= 0;
- end else begin
- // iomem_ready <= 0;
- // if (iomem_valid && !iomem_ready && iomem_addr[31:8] == 24'h030000) begin
- // iomem_ready <= 1;
- // end else if (iomem_addr[7:0] == 8'hc0) begin
- // iomem_rdata <= {31'd0, analog_out_sel};
- // if (iomem_wstrb[0]) analog_out_sel <= iomem_wdata[0];
- // end else if (iomem_addr[7:0] == 8'hc4) begin
- // iomem_rdata <= {31'd0, opamp_bias_ena};
- // if (iomem_wstrb[0]) opamp_bias_ena <= iomem_wdata[0];
- // end else if (iomem_addr[7:0] == 8'hc8) begin
- // iomem_rdata <= {31'd0, opamp_ena};
- // if (iomem_wstrb[0]) opamp_ena <= iomem_wdata[0];
- // end else if (iomem_addr[7:0] == 8'hd0) begin
- // iomem_rdata <= {31'd0, bg_ena};
- // if (iomem_wstrb[0]) bg_ena <= iomem_wdata[0];
- // end
- end
- end
-
endmodule
@@ -934,6 +702,7 @@
// Implementation note:
// Replace the following two modules with wrappers for your SRAM cells.
+
module openstriVe_soc_regs (
input clk, wen,
input [5:0] waddr,
