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foss-eda-tools/third_party/shuttle/sky130/mpw-001/slot-019/dae92165733550e4b37367b571fd1358f355f5e7^!/.
commit
dae92165733550e4b37367b571fd1358f355f5e7
[log]
author
Diego Hernando <djhernando96@gmail.com>
Thu Dec 17 16:31:34 2020 -0300
committer
Diego Hernando <djhernando96@gmail.com>
Thu Dec 17 16:31:34 2020 -0300
tree
17a4b66ea93b67ddf07e6e9285963324d3e33f09
parent
c6dd265f254272168d7d9c2326711ec4a13741e3 [diff]
Ring OSC done. 21 Stages. Need to check output buffer

diff --git a/xschem/ring_vco/not.sch b/xschem/ring_vco/not.sch
index ab0740c..674e041 100644
--- a/xschem/ring_vco/not.sch
+++ b/xschem/ring_vco/not.sch

@@ -11,9 +11,7 @@
 N 80 90 130 90 { lab=in}
 N 210 90 300 90 { lab=out}
 N 210 200 210 240 { lab=vss}
-N 210 170 280 170 { lab=vss}
-N 280 170 280 240 { lab=vss}
-N 210 240 280 240 { lab=vss}
+N 210 170 280 170 { lab=vbulk}
 N 80 240 210 240 { lab=vss}
 N 210 -50 210 -10 { lab=vdd}
 N 80 -50 210 -50 { lab=vdd}
@@ -48,3 +46,4 @@
 C {ipin.sym} 80 240 0 0 {name=p3 lab=vss}
 C {opin.sym} 300 90 0 0 {name=p4 lab=out
 }
+C {ipin.sym} 280 170 2 0 {name=p5 lab=vbulk}

diff --git a/xschem/ring_vco/not.sym b/xschem/ring_vco/not.sym
index 09e1378..a5e69e5 100644
--- a/xschem/ring_vco/not.sym
+++ b/xschem/ring_vco/not.sym

@@ -14,10 +14,12 @@
 L 4 -20 20 20 0 {}
 L 4 -20 -20 20 0 {}
 L 4 -20 -20 -20 20 {}
+L 4 -40 10 -20 10 {}
 B 5 -2.5 -32.5 2.5 -27.5 {name=vdd dir=in name=p1 }
 B 5 -42.5 -2.5 -37.5 2.5 {name=in dir=in name=p2 }
 B 5 47.5 -2.5 52.5 2.5 {name=out dir=out name=p4 }
 B 5 -2.5 27.5 2.5 32.5 {name=vss dir=in name=p3 }
+B 5 -42.5 7.5 -37.5 12.5 {name=vbulk dir=in name=p3 }
 A 4 25 -0.4000000000000057 5.015974481593782 355.4260787400991 360 {}
 T {@symname} 16 4 0 0 0.3 0.3 {}
 T {@name} 15 -22 0 0 0.2 0.2 {}
@@ -25,3 +27,4 @@
 T {in} -35 -14 0 0 0.2 0.2 {}
 T {out} 55 -14 0 1 0.2 0.2 {}
 T {vss} 14 15 1 0 0.2 0.2 {}
+T {vbulk} -25 24 2 0 0.2 0.2 {}

diff --git a/xschem/ring_vco/ring_vco.sch b/xschem/ring_vco/ring_vco.sch
index e2ab5e0..27a8ddf 100644
--- a/xschem/ring_vco/ring_vco.sch
+++ b/xschem/ring_vco/ring_vco.sch

@@ -27,7 +27,7 @@
 N 330 -80 330 -30 { lab=10}
 N 440 -80 440 -30 { lab=10}
 N 550 -80 550 -30 { lab=10}
-N 920 0 1020 0 { lab=out}
+N 2520 0 2620 0 { lab=out}
 N -0 -80 550 -80 { lab=10}
 N 550 -80 640 -80 { lab=10}
 N 290 -200 290 -80 { lab=10}
@@ -54,18 +54,18 @@
 N -280 250 -200 250 { lab=vss}
 N -200 -140 -120 -140 { lab=5}
 N -120 -230 -120 -140 { lab=5}
-N 760 -30 760 30 { lab=out_ring}
-N 760 0 820 0 { lab=out_ring}
-N 690 60 720 60 { lab=o6}
-N 690 -60 690 60 { lab=o6}
-N 690 -60 720 -60 { lab=o6}
-N 760 -120 760 -90 { lab=10}
-N 690 -120 760 -120 { lab=10}
-N 690 -120 690 -80 { lab=10}
+N 2360 -30 2360 30 { lab=out_ring}
+N 2360 0 2420 0 { lab=out_ring}
+N 2290 60 2320 60 { lab=#net1}
+N 2290 -60 2290 60 { lab=#net1}
+N 2290 -60 2320 -60 { lab=#net1}
+N 2360 -120 2360 -90 { lab=10}
+N 2290 -120 2360 -120 { lab=10}
+N 2290 -120 2290 -80 { lab=10}
 N 640 -80 690 -80 { lab=10}
-N 760 90 760 120 { lab=9}
-N 690 120 760 120 { lab=9}
-N 690 80 690 120 { lab=9}
+N 2360 90 2360 120 { lab=9}
+N 2290 120 2360 120 { lab=9}
+N 2290 80 2290 120 { lab=9}
 N 290 80 690 80 { lab=9}
 N 290 80 290 150 { lab=9}
 N 330 60 330 80 { lab=9}
@@ -75,28 +75,131 @@
 N -0 60 0 80 { lab=9}
 N 110 60 110 80 { lab=9}
 N 220 60 220 80 { lab=9}
-N 600 0 690 -0 { lab=o6}
-N 920 -30 920 30 { lab=out}
-N 920 90 920 120 { lab=vss}
-N 920 120 1010 120 { lab=vss}
-N 1010 60 1010 120 { lab=vss}
-N 920 60 1010 60 { lab=vss}
-N 850 60 880 60 { lab=out_ring}
-N 850 -60 850 60 { lab=out_ring}
-N 850 -60 880 -60 { lab=out_ring}
-N 820 -0 850 -0 { lab=out_ring}
-N 920 -120 920 -90 { lab=vdd}
-N 920 -120 1000 -120 { lab=vdd}
-N 1000 -120 1000 -60 { lab=vdd}
-N 920 -60 1000 -60 { lab=vdd}
+N 2520 -30 2520 30 { lab=out}
+N 2520 90 2520 120 { lab=vss}
+N 2520 120 2610 120 { lab=vss}
+N 2610 60 2610 120 { lab=vss}
+N 2520 60 2610 60 { lab=vss}
+N 2450 60 2480 60 { lab=out_ring}
+N 2450 -60 2450 60 { lab=out_ring}
+N 2450 -60 2480 -60 { lab=out_ring}
+N 2420 0 2450 0 { lab=out_ring}
+N 2520 -120 2520 -90 { lab=vdd}
+N 2520 -120 2600 -120 { lab=vdd}
+N 2600 -120 2600 -60 { lab=vdd}
+N 2520 -60 2600 -60 { lab=vdd}
 N 670 -300 670 -270 { lab=vss}
 N 670 -390 670 -360 { lab=in}
-N 760 -60 820 -60 { lab=10}
-N 820 -120 820 -60 { lab=10}
-N 760 -120 820 -120 { lab=10}
-N 760 60 840 60 { lab=9}
-N 840 60 840 120 { lab=9}
-N 760 120 840 120 { lab=9}
+N 2360 -60 2420 -60 { lab=10}
+N 2420 -120 2420 -60 { lab=10}
+N 2360 -120 2420 -120 { lab=10}
+N 2360 60 2440 60 { lab=vss}
+N 2440 60 2440 120 { lab=vss}
+N 600 -0 620 -0 { lab=o6}
+N 710 -0 730 -0 { lab=o7}
+N 690 80 910 80 { lab=9}
+N 690 -80 910 -80 { lab=10}
+N 660 -80 660 -30 { lab=10}
+N 770 -80 770 -30 { lab=10}
+N 770 30 770 80 { lab=9}
+N 660 30 660 80 { lab=9}
+N 910 80 1180 80 { lab=9}
+N 910 -80 1180 -80 { lab=10}
+N -60 10 -40 10 { lab=vss}
+N -60 10 -60 50 { lab=vss}
+N -60 50 720 50 { lab=vss}
+N 720 10 730 10 { lab=vss}
+N 720 10 720 50 { lab=vss}
+N 610 10 620 10 { lab=vss}
+N 610 10 610 50 { lab=vss}
+N 500 10 510 10 { lab=vss}
+N 500 10 500 50 { lab=vss}
+N 390 10 400 10 { lab=vss}
+N 390 10 390 50 { lab=vss}
+N 60 10 70 10 { lab=vss}
+N 60 10 60 50 { lab=vss}
+N 280 10 290 10 { lab=vss}
+N 280 10 280 50 { lab=vss}
+N 170 10 180 10 { lab=vss}
+N 170 10 170 50 { lab=vss}
+N 820 -0 840 -0 { lab=o8}
+N 930 -0 950 -0 { lab=#net2}
+N 1040 -0 1060 0 { lab=#net3}
+N 1150 -0 1180 -0 { lab=#net4}
+N 720 50 1160 50 { lab=vss}
+N 1160 10 1160 50 { lab=vss}
+N 1160 10 1180 10 { lab=vss}
+N 1050 10 1060 10 { lab=vss}
+N 1050 10 1050 50 { lab=vss}
+N 940 10 950 10 { lab=vss}
+N 940 10 940 50 { lab=vss}
+N 830 10 840 10 { lab=vss}
+N 830 10 830 50 { lab=vss}
+N 880 30 880 80 { lab=9}
+N 880 -80 880 -30 { lab=10}
+N 990 -80 990 -30 { lab=10}
+N 990 30 990 80 { lab=9}
+N 1100 30 1100 80 { lab=9}
+N 1100 -80 1100 -30 { lab=10}
+N 1220 30 1220 80 { lab=9}
+N 1180 80 1220 80 { lab=9}
+N 1220 -80 1220 -30 { lab=10}
+N 1180 -80 1220 -80 { lab=10}
+N 1220 80 1820 80 { lab=9}
+N 1220 -80 1820 -80 { lab=10}
+N 1340 30 1340 80 { lab=9}
+N 1340 -80 1340 -30 { lab=10}
+N 1460 30 1460 80 { lab=9}
+N 1460 -80 1460 -30 { lab=10}
+N 1580 -80 1580 -30 { lab=10}
+N 1580 30 1580 80 { lab=9}
+N 1160 50 1640 50 { lab=vss}
+N 1640 10 1640 50 { lab=vss}
+N 1640 10 1660 10 { lab=vss}
+N 1520 10 1540 10 { lab=vss}
+N 1520 10 1520 50 { lab=vss}
+N 1400 10 1420 10 { lab=vss}
+N 1400 10 1400 50 { lab=vss}
+N 1280 10 1300 10 { lab=vss}
+N 1280 10 1280 50 { lab=vss}
+N 1700 30 1700 80 { lab=9}
+N 1700 -80 1700 -30 { lab=10}
+N 1630 0 1660 0 { lab=#net5}
+N 1510 0 1540 0 { lab=#net6}
+N 1390 -0 1420 0 { lab=#net7}
+N 1270 0 1300 -0 { lab=#net8}
+N 1820 80 2030 80 { lab=9}
+N 1820 -80 2030 -80 { lab=10}
+N 1750 0 1780 -0 { lab=#net9}
+N 1640 50 1760 50 { lab=vss}
+N 1760 10 1760 50 { lab=vss}
+N 1760 10 1780 10 { lab=vss}
+N 1760 50 1880 50 { lab=vss}
+N 1880 10 1880 50 { lab=vss}
+N 1880 10 1910 10 { lab=vss}
+N 1820 30 1820 80 { lab=9}
+N 1950 30 1950 80 { lab=9}
+N 2260 0 2290 0 { lab=#net1}
+N 1950 -80 1950 -30 { lab=10}
+N 1820 -80 1820 -30 { lab=10}
+N 1870 -0 1910 -0 { lab=#net10}
+N 2010 10 2010 50 { lab=vss}
+N 2010 10 2030 10 { lab=vss}
+N 2010 50 2130 50 { lab=vss}
+N 2130 10 2130 50 { lab=vss}
+N 2130 10 2160 10 { lab=vss}
+N 2120 0 2160 0 { lab=#net11}
+N 2000 0 2030 -0 { lab=#net12}
+N 1880 50 2010 50 { lab=vss}
+N 2030 80 2200 80 { lab=9}
+N 2200 30 2200 80 { lab=9}
+N 2200 -80 2200 -30 { lab=10}
+N 2030 -80 2200 -80 { lab=10}
+N 2070 -80 2070 -30 { lab=10}
+N 2070 30 2070 80 { lab=9}
+N 2250 0 2260 -0 { lab=#net1}
+N 2200 80 2290 80 { lab=9}
+N 2200 -80 2290 -80 { lab=10}
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 0 0 0 0 {name=x1}
 C {vsource.sym} 480 -330 0 0 {name=V1 value=DC\{Vss\}}
 C {vsource.sym} 570 -330 0 0 {name=V2 value=DC\{Vdd\}}
@@ -113,7 +216,7 @@
 * Circuit Parameters
 .param vdd  = 1.8
 .param vss  = 0.0
-.param vin  = 0.6
+.param vin  = 1
 .param iref = 200u
 .options TEMP = 65.0
 
@@ -124,13 +227,22 @@
 .save all
 + @M.X2.XM1.msky130_fd_pr__nfet_01v8[id] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vth] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vgs] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vds] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vdsat] @M.X2.XM1.msky130_fd_pr__nfet_01v8[gm] @M.X2.XM1.msky130_fd_pr__nfet_01v8[gds] @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgs] @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgd]
 + @M.X2.XM2.msky130_fd_pr__pfet_01v8[id] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vds] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X2.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X2.XM2.msky130_fd_pr__pfet_01v8[gds] @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgs] @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgd]
++ @M.XM6.msky130_fd_pr__nfet_01v8[id] @M.XM6.msky130_fd_pr__nfet_01v8[vth] @M.XM6.msky130_fd_pr__nfet_01v8[vgs] @M.XM6.msky130_fd_pr__nfet_01v8[vds] @M.XM6.msky130_fd_pr__nfet_01v8[vdsat] @M.XM6.msky130_fd_pr__nfet_01v8[gm] @M.XM6.msky130_fd_pr__nfet_01v8[gds] @M.XM6.msky130_fd_pr__nfet_01v8[cgs] @M.XM6.msky130_fd_pr__nfet_01v8[cgd]
++ @M.XM5.msky130_fd_pr__pfet_01v8[id] @M.XM5.msky130_fd_pr__pfet_01v8[vth] @M.XM5.msky130_fd_pr__pfet_01v8[vgs] @M.XM5.msky130_fd_pr__pfet_01v8[vds] @M.XM5.msky130_fd_pr__pfet_01v8[vdsat] @M.XM5.msky130_fd_pr__pfet_01v8[gm] @M.XM5.msky130_fd_pr__pfet_01v8[gds] @M.XM5.msky130_fd_pr__nfet_01v8[cgs] @M.XM5.msky130_fd_pr__nfet_01v8[cgd]
+
+
 
 *Simulations
 .control
   *reset
-  tran 0.1n 0.5u
+  tran 0.05n 1u
   setplot tran1
   plot v(out) v(in)
+  linearize
+  set specwindow="blackman"
+  fft v(out)
+  spec 10 1000000 1000 v(out)
+  plot mag(v(out))
   *write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_closeloop_tran1.raw
   
   
@@ -152,9 +264,9 @@
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 440 0 0 0 {name=x5}
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 550 0 0 0 {name=x6}
 C {lab_pin.sym} -80 0 0 0 {name=l5 sig_type=std_logic lab=out_ring}
-C {lab_wire.sym} 970 -120 0 0 {name=l11 sig_type=std_logic lab=vdd}
-C {lab_wire.sym} 970 120 0 0 {name=l14 sig_type=std_logic lab=vss}
-C {sky130_fd_pr/nfet_01v8.sym} 740 60 0 0 {name=M1
+C {lab_wire.sym} 2570 -120 0 0 {name=l11 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 2570 120 0 0 {name=l14 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} 2340 60 0 0 {name=M1
 L=0.15
 W=1.2
 ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
@@ -165,7 +277,7 @@
 model=nfet_01v8
 spiceprefix=X
 }
-C {sky130_fd_pr/pfet_01v8.sym} 740 -60 0 0 {name=M2
+C {sky130_fd_pr/pfet_01v8.sym} 2340 -60 0 0 {name=M2
 L=0.15
 W=1.5
 ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
@@ -176,7 +288,7 @@
 model=pfet_01v8
 spiceprefix=X
 }
-C {sky130_fd_pr/nfet_01v8.sym} 900 60 0 0 {name=M3
+C {sky130_fd_pr/nfet_01v8.sym} 2500 60 0 0 {name=M3
 L=0.15
 W=0.6
 ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
@@ -187,9 +299,9 @@
 model=nfet_01v8
 spiceprefix=X
 }
-C {sky130_fd_pr/pfet_01v8.sym} 900 -60 0 0 {name=M4
+C {sky130_fd_pr/pfet_01v8.sym} 2500 -60 0 0 {name=M4
 L=0.15
-W=1.05
+W=1.5
 ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
 as="'W * 0.29'" ps="'2 * (W + 0.29)'"
 nrd="'0.29 / W'" nrs="'0.29 / W'"
@@ -198,11 +310,11 @@
 model=pfet_01v8
 spiceprefix=X
 }
-C {lab_wire.sym} 820 0 0 0 {name=l4 sig_type=std_logic lab=out_ring}
-C {lab_pin.sym} 1020 0 2 0 {name=l6 sig_type=std_logic lab=out}
+C {lab_wire.sym} 2420 0 0 0 {name=l4 sig_type=std_logic lab=out_ring}
+C {lab_pin.sym} 2620 0 2 0 {name=l6 sig_type=std_logic lab=out}
 C {sky130_fd_pr/pfet_01v8.sym} 270 -230 0 0 {name=M5
 L=0.15
-W=1.05
+W=1.5
 ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
 as="'W * 0.29'" ps="'2 * (W + 0.29)'"
 nrd="'0.29 / W'" nrs="'0.29 / W'"
@@ -213,7 +325,7 @@
 }
 C {sky130_fd_pr/nfet_01v8.sym} 270 180 0 0 {name=M6
 L=0.15
-W=1.05
+W=1.5
 ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
 as="'W * 0.29'" ps="'2 * (W + 0.29)'"
 nrd="'0.29 / W'" nrs="'0.29 / W'"
@@ -255,7 +367,25 @@
 C {lab_wire.sym} 280 0 0 0 {name=l18 sig_type=std_logic lab=o3}
 C {lab_wire.sym} 390 0 0 0 {name=l19 sig_type=std_logic lab=o4}
 C {lab_wire.sym} 500 0 0 0 {name=l20 sig_type=std_logic lab=o5}
-C {lab_wire.sym} 630 0 0 0 {name=l21 sig_type=std_logic lab=o6}
+C {lab_wire.sym} 610 0 0 0 {name=l21 sig_type=std_logic lab=o6}
 C {vsource.sym} 670 -330 0 0 {name=V3 value=DC\{Vin\}}
 C {lab_pin.sym} 670 -270 3 0 {name=l22 sig_type=std_logic lab=vss}
 C {lab_pin.sym} 670 -390 1 0 {name=l23 sig_type=std_logic lab=in}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 660 0 0 0 {name=x7}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 770 0 0 0 {name=x8}
+C {lab_wire.sym} 720 0 0 0 {name=l24 sig_type=std_logic lab=o7}
+C {lab_wire.sym} 830 0 0 0 {name=l25 sig_type=std_logic lab=o8}
+C {lab_wire.sym} -30 50 0 0 {name=l26 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 2440 120 3 0 {name=l27 sig_type=std_logic lab=vss}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 880 0 0 0 {name=x9}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 990 0 0 0 {name=x10}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1100 0 0 0 {name=x11}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1220 0 0 0 {name=x12}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1340 0 0 0 {name=x13}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1460 0 0 0 {name=x14}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1580 0 0 0 {name=x15}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1700 0 0 0 {name=x16}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1820 0 0 0 {name=x17}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1950 0 0 0 {name=x18}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 2070 0 0 0 {name=x19}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 2200 0 0 0 {name=x20}