(1) Added a wrapper interface between the top level verilog and the user project
example.
(2) Corrected broken directory references in README.md
(3) Added the caravel.pdf document (first draft, mostly just figures and no text).
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 433dd91..b5fcff9 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -40,6 +40,7 @@
`include "mprj_io.v"
`include "chip_io.v"
`include "user_id_programming.v"
+`include "user_project_wrapper.v"
`include "gpio_control_block.v"
`include "clock_div.v"
`include "simple_por.v"
@@ -420,11 +421,11 @@
);
- /*--------------------------------------*/
- /* User project is instantiated here */
- /*--------------------------------------*/
+ /*----------------------------------------------*/
+ /* Wrapper module around the user project */
+ /*----------------------------------------------*/
- user_proj_example #(
+ user_project_wrapper #(
.IO_PADS(`MPRJ_IO_PADS),
.PWR_PADS(`MPRJ_PWR_PADS)
) mprj (
@@ -455,7 +456,9 @@
// IO Pads
.io_in (user_io_in),
.io_out(user_io_out),
- .io_oeb(user_io_oeb)
+ .io_oeb(user_io_oeb),
+ // Independent clock
+ .user_clock2(mprj_clock2)
);
/*--------------------------------------*/
