(1) Added a wrapper interface between the top level verilog and the user project
example.
(2) Corrected broken directory references in README.md
(3) Added the caravel.pdf document (first draft, mostly just figures and no text).
diff --git a/verilog/rtl/README b/verilog/rtl/README
index 1ac0025..5c05935 100644
--- a/verilog/rtl/README
+++ b/verilog/rtl/README
@@ -4,17 +4,30 @@
Caravel pinout:
---------------
- vdd3v3
- vdd1v8
- vss
- gpio 1 bit, mainly used for external LDO control of user power supply
+ vddio 3.3V supply for all I/O and ESD
+ vssio Ground for all I/O and ESD
+ vdda 3.3V supply for management area
+ vssa Ground for management area
+ vccd 1.8V supply for management area
+ vssd Digital ground for management area
+
+ vdda1 3.3V supply for user area 1
+ vdda2 3.3V supply for user area 2
+ vssa1 Ground for user area 1
+ vssa2 Ground for user area 2
+ vccd1 1.8 supply for user area 1
+ vccd2 1.8 supply for user area 2
+ vssd1 Digital ground for user area 1
+ vssd2 Digital ground for user area 2
+
clock Master clock input
+ gpio 1 bit, mainly used for external LDO control of user power supply
+ mprj_io 32 bits general purpose programmable digital or analog I/O
resetb Master reset (sense inverted) input
flash_csb SPI flash controller chip select (sense inverted)
flash_clk SPI flash controller clock
flash_io0 SPI flash controller data out
flash_io1 SPI flash controller data in
- mprj_io 32 bits general purpose programmable digital or analog I/O
Special-use pins for the management SoC:
----------------------------------------
@@ -80,38 +93,40 @@
UART: Clock divider: 2000 0000
Data: 2000 0004
+ Enable 2000 0008
GPIO: Data: 2100 0000
Output enable: 2100 0004
Pullup 2100 0008
Pulldown 2100 000c
- Counter 1: Config: 2110 0000
- Value: 2110 0004
- Data: 2110 0008
+ Counter 1: Config: 2200 0000
+ Value: 2200 0004
+ Data: 2200 0008
- Counter 2: Config: 2120 0000
- Value: 2120 0004
- Data: 2120 0008
+ Counter 2: Config: 2300 0000
+ Value: 2300 0004
+ Data: 2300 0008
- SPI master: Config: 2130 0000
- Data: 2130 0004
+ SPI master: Config: 2400 0000
+ Data: 2400 0004
- Logic analyzer: Data 0: 2200 0000
- Data 1: 2200 0004
- Data 2: 2200 0008
- Data 3: 2200 000c
- Enable 0: 2200 0010
- Enable 1: 2200 0014
- Enable 2: 2200 0018
- Enable 3: 2200 001c
+ Logic analyzer: Data 0: 2500 0000
+ Data 1: 2500 0004
+ Data 2: 2500 0008
+ Data 3: 2500 000c
+ Enable 0: 2500 0010
+ Enable 1: 2500 0014
+ Enable 2: 2500 0018
+ Enable 3: 2500 001c
- Project ctrl: Data: 2300 0000
- Transfer: 2300 0004
- I/O Config: 2300 0008
- to 2300 0084
- Power Config: 2300 0088
- to 2300 0104
+ Project ctrl: Data (L): 2600 0000
+ Data (H): 2600 0004
+ Transfer: 2600 0008
+ I/O Config: 2600 000c
+ to 2600 009c
+ Power Config: 2600 00a0
+ to 2600 0130
Flash ctrl: Config: 2D00 0000
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 433dd91..b5fcff9 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -40,6 +40,7 @@
`include "mprj_io.v"
`include "chip_io.v"
`include "user_id_programming.v"
+`include "user_project_wrapper.v"
`include "gpio_control_block.v"
`include "clock_div.v"
`include "simple_por.v"
@@ -420,11 +421,11 @@
);
- /*--------------------------------------*/
- /* User project is instantiated here */
- /*--------------------------------------*/
+ /*----------------------------------------------*/
+ /* Wrapper module around the user project */
+ /*----------------------------------------------*/
- user_proj_example #(
+ user_project_wrapper #(
.IO_PADS(`MPRJ_IO_PADS),
.PWR_PADS(`MPRJ_PWR_PADS)
) mprj (
@@ -455,7 +456,9 @@
// IO Pads
.io_in (user_io_in),
.io_out(user_io_out),
- .io_oeb(user_io_oeb)
+ .io_oeb(user_io_oeb),
+ // Independent clock
+ .user_clock2(mprj_clock2)
);
/*--------------------------------------*/
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
new file mode 100644
index 0000000..8b143db
--- /dev/null
+++ b/verilog/rtl/user_project_wrapper.v
@@ -0,0 +1,102 @@
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ * An example user project is provided in this wrapper. The
+ * example should be removed and replaced with the actual
+ * user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper #(
+ parameter IO_PADS = 37,
+ parameter PWR_PADS = 4,
+ parameter BITS = 32
+)(
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oen,
+
+ // IOs
+ input [IO_PADS-1:0] io_in,
+ output [IO_PADS-1:0] io_out,
+ output [IO_PADS-1:0] io_oeb,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2
+);
+
+ /*--------------------------------------*/
+ /* User project is instantiated here */
+ /*--------------------------------------*/
+
+ user_proj_example #(
+ .IO_PADS(`MPRJ_IO_PADS),
+ .PWR_PADS(`MPRJ_PWR_PADS)
+ ) mprj (
+ .vdda1(vdda1), // User area 1 3.3V power
+ .vdda2(vdda2), // User area 2 3.3V power
+ .vssa1(vssa1), // User area 1 analog ground
+ .vssa2(vssa2), // User area 2 analog ground
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vccd2(vccd2), // User area 2 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+ .vssd2(vssd2), // User area 2 digital ground
+
+ // MGMT core clock and reset
+
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ // MGMT SoC Wishbone Slave
+
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_sel_i(wbs_sel_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+
+ // Logic Analyzer
+
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oen (la_oen),
+
+ // IO Pads
+
+ .io_in (io_in),
+ .io_out(io_out),
+ .io_oeb(io_oeb)
+ );
+
+endmodule // user_project_wrapper
