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foss-eda-tools/third_party/shuttle/sky130/mpw-001/slot-019/8388185303e724fcb0f817cfa20aba218010e233^!/.
commit
8388185303e724fcb0f817cfa20aba218010e233
[log]
author
Diego Hernando <djhernando96@gmail.com>
Fri Dec 18 15:16:24 2020 -0300
committer
Diego Hernando <djhernando96@gmail.com>
Fri Dec 18 15:16:24 2020 -0300
tree
491baa9cbc11e153b9f376ba32645bdc3fc08290
parent
dae92165733550e4b37367b571fd1358f355f5e7 [diff]
Ring OSC & Frequency Divider working in all corners

diff --git a/xschem/ring_vco/FD.sch b/xschem/ring_vco/FD.sch
new file mode 100644
index 0000000..02f9c22
--- /dev/null
+++ b/xschem/ring_vco/FD.sch

@@ -0,0 +1,99 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 70 -250 70 -220 { lab=GND}
+N 160 -250 160 -220 { lab=vss}
+N 160 -340 160 -310 { lab=vdd}
+N 70 -340 70 -310 { lab=vss}
+N 340 -260 340 -230 { lab=vss}
+N 340 -350 340 -320 { lab=in}
+N -90 -0 -60 -0 { lab=in}
+N 10 70 10 100 { lab=vss}
+N 10 -100 10 -70 { lab=vdd}
+N 290 0 330 -0 { lab=outx4}
+N 220 70 220 90 { lab=vss}
+N 220 -100 220 -70 { lab=vdd}
+N 470 0 510 0 { lab=outx8}
+N 400 70 400 90 { lab=vss}
+N 400 -100 400 -70 { lab=vdd}
+N 650 0 690 0 { lab=outx16}
+N 580 70 580 90 { lab=vss}
+N 580 -100 580 -70 { lab=vdd}
+N 830 0 870 0 { lab=outx32}
+N 760 70 760 90 { lab=vss}
+N 760 -100 760 -70 { lab=vdd}
+N 870 90 870 110 { lab=vss}
+N 870 0 870 30 { lab=outx32}
+N 80 -0 150 -0 { lab=outx2}
+C {vsource.sym} 70 -280 0 0 {name=V1 value=DC\{Vss\}}
+C {vsource.sym} 160 -280 0 0 {name=V2 value=DC\{Vdd\}}
+C {gnd.sym} 70 -220 0 0 {name=l5 lab=GND}
+C {lab_pin.sym} 70 -340 1 0 {name=l6 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 160 -220 3 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 160 -340 1 0 {name=l9 sig_type=std_logic lab=vdd
+}
+C {vsource.sym} 340 -290 0 0 {name=V3 value="PULSE(0 \{Vin\} 1ns 1ps 1ps 1ns 2ns)"}
+C {lab_pin.sym} 340 -230 3 0 {name=l22 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 340 -350 1 0 {name=l23 sig_type=std_logic lab=in}
+C {netlist_not_shown.sym} 630 -300 0 0 {name=SIMULATION only_toplevel=false 
+
+value="
+
+
+* Circuit Parameters
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vin  = 1.8
+.options TEMP = 27.0
+
+* Include Models
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib SS
+
+* OP Parameters & Singals to save
+
+*Simulations
+.control
+  tran 0.1ns 500ns
+  setplot tran1
+  plot v(outx32) v(outx16)+2 v(outx8)+4 v(outx4)+6 v(outx2)+8 v(in)+10 
+  *write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_closeloop_tran1.raw
+
+.endc
+
+.end
+"}
+C {lab_pin.sym} -90 0 0 0 {name=l3 sig_type=std_logic lab=in}
+C {lab_pin.sym} 10 100 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 10 -100 1 0 {name=l4 sig_type=std_logic lab=vdd
+}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 10 0 0 0 {name=x1}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 220 0 0 0 {name=x2}
+C {lab_pin.sym} 220 -100 1 0 {name=l10 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 220 90 3 0 {name=l11 sig_type=std_logic lab=vss}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 400 0 0 0 {name=x3}
+C {lab_pin.sym} 400 -100 1 0 {name=l13 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 400 90 3 0 {name=l14 sig_type=std_logic lab=vss}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 580 0 0 0 {name=x4}
+C {lab_pin.sym} 580 -100 1 0 {name=l15 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 580 90 3 0 {name=l16 sig_type=std_logic lab=vss}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 760 0 0 0 {name=x5}
+C {lab_pin.sym} 760 -100 1 0 {name=l17 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 760 90 3 0 {name=l18 sig_type=std_logic lab=vss}
+C {capa.sym} 870 60 0 0 {name=C2
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 870 110 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 870 0 2 0 {name=l20 sig_type=std_logic lab=outx32}
+C {lab_wire.sym} 120 0 0 0 {name=l1 sig_type=std_logic lab=outx2}
+C {lab_wire.sym} 320 0 0 0 {name=l21 sig_type=std_logic lab=outx4}
+C {lab_wire.sym} 500 0 0 0 {name=l24 sig_type=std_logic lab=outx8}
+C {lab_wire.sym} 680 0 0 0 {name=l25 sig_type=std_logic lab=outx16}

diff --git a/xschem/ring_vco/FD.spice b/xschem/ring_vco/FD.spice
new file mode 100644
index 0000000..9df0b12
--- /dev/null
+++ b/xschem/ring_vco/FD.spice

@@ -0,0 +1,79 @@
+**.subckt FD
+V1 vss GND DC{Vss} 
+V2 vdd vss DC{Vdd} 
+V3 in vss PULSE(0 {Vin} 1ps 1ps 1ps 5ns 10ns) 
+x1 in vss out vdd FD_v2
+C1 out vss 10f m=1
+**** begin user architecture code
+
+
+
+
+* Circuit Parameters
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vin  = 1.8
+.param iref = 200u
+.options TEMP = 27.0
+
+* Include Models
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
+
+* OP Parameters & Singals to save
+.save all  @M.X1.XM1.msky130_fd_pr__nfet_01v8[id] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vth]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vdsat]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM1.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gds]
+
+*Simulations
+.control
+  tran 0.1ns 200ns
+  setplot tran1
+  plot v(in) v(out)
+  *write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_closeloop_tran1.raw
+
+
+.endc
+
+.end
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  /home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym # of pins=4
+
+.subckt FD_v2  clk vss out vdd
+*.opin out
+*.ipin vdd
+*.ipin clk
+*.ipin vss
+XM1 1 4 vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM2 1 4 vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM3 1 clk 2 vdd sky130_fd_pr__pfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM4 1 clk_b 2 vss sky130_fd_pr__nfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM5 3 2 vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM6 3 2 vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM7 3 clk out vdd sky130_fd_pr__pfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM8 3 clk_b out vss sky130_fd_pr__nfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM9 4 out vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM10 4 out vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM11 clk_b clk vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM12 clk_b clk vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+.ends
+
+.GLOBAL GND
+.end

diff --git a/xschem/ring_vco/FD_v2 b/xschem/ring_vco/FD_v2
new file mode 100644
index 0000000..ee956bc
--- /dev/null
+++ b/xschem/ring_vco/FD_v2

@@ -0,0 +1,10 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {}
+
+T {@symname} -22.5 -6 0 0 0.3 0.3 {}
+T {@name} 135 -22 0 0 0.2 0.2 {}
+L 4 -130 -10 130 -10 {}
+L 4 -130 10 130 10 {}
+L 4 -130 -10 -130 10 {}
+L 4 130 -10 130 10 {}

diff --git a/xschem/ring_vco/FD_v2.sch b/xschem/ring_vco/FD_v2.sch
new file mode 100644
index 0000000..8294268
--- /dev/null
+++ b/xschem/ring_vco/FD_v2.sch

@@ -0,0 +1,254 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N -330 -40 -330 40 { lab=1}
+N -330 100 -330 150 { lab=vss}
+N -330 70 -260 70 { lab=vss}
+N -260 70 -260 150 { lab=vss}
+N -330 -170 -330 -100 { lab=vdd}
+N -330 -70 -260 -70 { lab=vdd}
+N -260 -160 -260 -70 { lab=vdd}
+N -260 -170 -260 -160 { lab=vdd}
+N -330 -170 -260 -170 { lab=vdd}
+N -330 150 -260 150 { lab=vss}
+N -410 70 -370 70 { lab=4}
+N -410 -70 -410 70 { lab=4}
+N -410 -70 -370 -70 { lab=4}
+N -470 0 -410 0 { lab=4}
+N -330 0 -200 0 { lab=1}
+N -160 70 -140 70 { lab=1}
+N -160 0 -160 70 { lab=1}
+N -200 0 -160 0 { lab=1}
+N -160 -70 -160 0 { lab=1}
+N -160 -70 -140 -70 { lab=1}
+N -80 -70 -60 -70 { lab=2}
+N -60 -70 -60 0 { lab=2}
+N -60 0 -60 70 { lab=2}
+N -80 70 -60 70 { lab=2}
+N -110 110 -110 140 { lab=clk_b}
+N -110 50 -110 70 { lab=vss}
+N -110 -70 -110 -50 { lab=vdd}
+N -110 -150 -110 -110 { lab=clk}
+N 110 -40 110 40 { lab=3}
+N 110 100 110 150 { lab=vss}
+N 110 70 180 70 { lab=vss}
+N 180 70 180 150 { lab=vss}
+N 110 -170 110 -100 { lab=vdd}
+N 110 -70 180 -70 { lab=vdd}
+N 180 -160 180 -70 { lab=vdd}
+N 180 -170 180 -160 { lab=vdd}
+N 110 -170 180 -170 { lab=vdd}
+N 110 150 180 150 { lab=vss}
+N 30 70 70 70 { lab=2}
+N 30 -70 30 70 { lab=2}
+N 30 -70 70 -70 { lab=2}
+N 110 0 240 0 { lab=3}
+N 280 70 300 70 { lab=3}
+N 280 0 280 70 { lab=3}
+N 240 0 280 0 { lab=3}
+N 280 -70 280 0 { lab=3}
+N 280 -70 300 -70 { lab=3}
+N 360 -70 380 -70 { lab=out}
+N 380 -70 380 0 { lab=out}
+N 380 0 380 70 { lab=out}
+N 360 70 380 70 { lab=out}
+N 330 110 330 140 { lab=clk}
+N 330 50 330 70 { lab=vss}
+N 330 -70 330 -50 { lab=vdd}
+N 330 -150 330 -110 { lab=clk_b}
+N 570 -40 570 40 { lab=4}
+N 570 100 570 150 { lab=vss}
+N 570 70 640 70 { lab=vss}
+N 640 70 640 150 { lab=vss}
+N 570 -170 570 -100 { lab=vdd}
+N 570 -70 640 -70 { lab=vdd}
+N 640 -160 640 -70 { lab=vdd}
+N 640 -170 640 -160 { lab=vdd}
+N 570 -170 640 -170 { lab=vdd}
+N 570 150 640 150 { lab=vss}
+N 490 70 530 70 { lab=out}
+N 490 -70 490 70 { lab=out}
+N 490 -70 530 -70 { lab=out}
+N 380 -0 490 -0 { lab=out}
+N -60 -0 30 -0 { lab=2}
+N -330 -400 -330 -320 { lab=clk_b}
+N -330 -260 -330 -210 { lab=vss}
+N -330 -290 -260 -290 { lab=vss}
+N -260 -290 -260 -210 { lab=vss}
+N -330 -530 -330 -460 { lab=vdd}
+N -330 -430 -260 -430 { lab=vdd}
+N -260 -520 -260 -430 { lab=vdd}
+N -260 -530 -260 -520 { lab=vdd}
+N -330 -530 -260 -530 { lab=vdd}
+N -330 -210 -260 -210 { lab=vss}
+N -410 -290 -370 -290 { lab=clk}
+N -410 -430 -410 -290 { lab=clk}
+N -410 -430 -370 -430 { lab=clk}
+N -330 -360 -200 -360 { lab=clk_b}
+N -470 -360 -410 -360 { lab=clk}
+N -460 -210 -330 -210 { lab=vss}
+N -470 -530 -330 -530 { lab=vdd}
+N 570 0 680 -0 { lab=4}
+N 420 -140 440 -140 { lab=out}
+N 420 -140 420 0 { lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} -350 70 0 0 {name=M1
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} -350 -70 0 0 {name=M2
+L=0.15
+W=0.9
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} -110 -90 1 0 {name=M3
+L=0.15
+W=0.9
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} -110 90 3 0 {name=M4
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} -290 -170 0 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} -290 150 0 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -110 50 1 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -470 0 0 0 {name=l4 sig_type=std_logic lab=4}
+C {lab_pin.sym} -110 140 3 0 {name=l6 sig_type=std_logic lab=clk_b}
+C {sky130_fd_pr/nfet_01v8.sym} 90 70 0 0 {name=M5
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 90 -70 0 0 {name=M6
+L=0.15
+W=0.9
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 330 -90 1 0 {name=M7
+L=0.15
+W=0.9
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 330 90 3 0 {name=M8
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 150 -170 0 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 150 150 0 0 {name=l8 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 330 50 1 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 330 140 3 0 {name=l11 sig_type=std_logic lab=clk}
+C {sky130_fd_pr/nfet_01v8.sym} 550 70 0 0 {name=M9
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 550 -70 0 0 {name=M10
+L=0.15
+W=0.9
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 610 -170 0 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 610 150 0 0 {name=l13 sig_type=std_logic lab=vss}
+C {opin.sym} 440 -140 0 0 {name=p1 lab=out}
+C {lab_wire.sym} -10 0 0 0 {name=l14 sig_type=std_logic lab=2}
+C {lab_wire.sym} 190 0 0 0 {name=l15 sig_type=std_logic lab=3}
+C {lab_wire.sym} -230 0 0 0 {name=l17 sig_type=std_logic lab=1}
+C {sky130_fd_pr/nfet_01v8.sym} -350 -290 0 0 {name=M11
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} -350 -430 0 0 {name=M12
+L=0.15
+W=0.9
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} -290 -530 0 0 {name=l18 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} -290 -210 0 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -110 -150 1 0 {name=l5 sig_type=std_logic lab=clk}
+C {lab_pin.sym} -200 -360 2 0 {name=l20 sig_type=std_logic lab=clk_b}
+C {lab_pin.sym} 330 -150 1 0 {name=l10 sig_type=std_logic lab=clk_b}
+C {ipin.sym} -470 -530 0 0 {name=p2 lab=vdd}
+C {ipin.sym} -470 -360 0 0 {name=p3 lab=clk}
+C {ipin.sym} -460 -210 0 0 {name=p4 lab=vss}
+C {lab_pin.sym} 680 0 2 0 {name=l16 sig_type=std_logic lab=4}
+C {lab_pin.sym} 330 -50 3 0 {name=l21 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -110 -50 3 0 {name=l22 sig_type=std_logic lab=vdd}

diff --git a/xschem/ring_vco/FD_v2.sym b/xschem/ring_vco/FD_v2.sym
new file mode 100644
index 0000000..7920f7d
--- /dev/null
+++ b/xschem/ring_vco/FD_v2.sym

@@ -0,0 +1,31 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -30 -50 30 {}
+L 4 50 -30 50 30 {}
+L 4 -70 0 -50 0 {}
+L 4 0 50 0 70 {}
+L 4 50 0 70 0 {}
+L 4 0 -70 0 -50 {}
+L 4 -50 30 -50 50 {}
+L 4 -50 50 50 50 {}
+L 4 50 30 50 50 {}
+L 4 50 -50 50 -30 {}
+L 4 -50 -50 50 -50 {}
+L 4 -50 -50 -50 -30 {}
+B 5 -72.5 -2.5 -67.5 2.5 {name=clk dir=in name=p3 }
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=in name=p4 }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out name=p1 }
+B 5 -2.5 -72.5 2.5 -67.5 {name=vdd dir=in name=p2 }
+T {@symname} -40.5 4 0 0 0.3 0.3 {}
+T {@name} -15 -22 0 0 0.2 0.2 {}
+T {clk} -45 -14 0 0 0.2 0.2 {}
+T {vss} -4 45 3 0 0.2 0.2 {}
+T {out} 45 -14 0 1 0.2 0.2 {}
+T {vdd} 4 -45 1 0 0.2 0.2 {}

diff --git a/xschem/ring_vco/FFD.sch b/xschem/ring_vco/FFD.sch
new file mode 100644
index 0000000..28d6927
--- /dev/null
+++ b/xschem/ring_vco/FFD.sch

@@ -0,0 +1,64 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1860 -140 1890 -140 { lab=OUT}
+N 1610 -80 1610 -50 { lab=vss}
+N 1610 80 1610 100 { lab=vdd}
+N 1520 140 1560 140 { lab=OUT}
+N 1520 60 1520 140 { lab=OUT}
+N 1690 -140 1760 -140 { lab=OUT}
+N 1760 -140 1860 -140 { lab=OUT}
+N 1520 -120 1560 -120 { lab=nOUT}
+N 1690 160 1760 160 { lab=nOUT}
+N 1760 100 1760 160 { lab=nOUT}
+N 1760 60 1760 100 { lab=nOUT}
+N 1760 -100 1760 -40 { lab=OUT}
+N 1760 -140 1760 -100 { lab=OUT}
+N 1520 -120 1520 -40 { lab=nOUT}
+N 1520 -40 1760 60 { lab=nOUT}
+N 1520 60 1760 -40 { lab=OUT}
+N 1610 -230 1610 -200 { lab=vdd}
+N 1610 220 1610 250 { lab=vss}
+N 1610 70 1610 80 { lab=vdd}
+N 1150 -190 1220 -190 { lab=T}
+N 1460 -160 1560 -160 { lab=#net1}
+N 1460 180 1560 180 { lab=#net2}
+N 1260 -160 1320 -160 { lab=CLK}
+N 1260 -160 1260 180 { lab=CLK}
+N 1260 180 1320 180 { lab=CLK}
+N 1220 -190 1320 -190 { lab=T}
+N 1220 150 1320 150 { lab=T}
+N 1220 -190 1220 150 { lab=T}
+N 1150 -0 1260 0 { lab=CLK}
+N 1290 -130 1320 -130 { lab=nOUT}
+N 1290 -130 1290 -40 { lab=nOUT}
+N 1290 -40 1520 -40 { lab=nOUT}
+N 1290 60 1520 60 { lab=OUT}
+N 1290 60 1290 210 { lab=OUT}
+N 1290 210 1320 210 { lab=OUT}
+N 1370 90 1370 110 { lab=vdd}
+N 1370 -260 1370 -230 { lab=vdd}
+N 1370 -90 1370 -70 { lab=vss}
+N 1370 250 1370 280 { lab=vss}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nand.sym} 1620 -140 0 0 {name=x1}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nand.sym} 1620 160 0 0 {name=x2}
+C {lab_pin.sym} 1610 70 1 0 {name=l7 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 1610 -50 3 0 {name=l12 sig_type=std_logic lab=vss}
+C {ipin.sym} 1610 -230 1 0 {name=p2 lab=vdd}
+C {ipin.sym} 1610 250 3 0 {name=p6 lab=vss}
+C {opin.sym} 1890 -140 0 0 {name=p3 lab=OUT}
+C {ipin.sym} 1150 -190 0 0 {name=p4 lab=T}
+C {lab_wire.sym} 1730 160 0 0 {name=l3 sig_type=std_logic lab=nOUT}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nand3.sym} 1380 -160 0 0 {name=x3}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nand3.sym} 1380 180 0 0 {name=x4}
+C {ipin.sym} 1150 0 0 0 {name=p1 lab=CLK}
+C {lab_pin.sym} 1370 90 1 0 {name=l1 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 1370 -260 1 0 {name=l2 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 1370 -70 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1370 280 3 0 {name=l5 sig_type=std_logic lab=vss}

diff --git a/xschem/ring_vco/FFD.spice b/xschem/ring_vco/FFD.spice
new file mode 100644
index 0000000..f828127
--- /dev/null
+++ b/xschem/ring_vco/FFD.spice

@@ -0,0 +1,90 @@
+**.subckt FFD
+x1 vdd in out net1 vss nand
+V1 vss GND DC{Vss} 
+V2 vdd vss DC{Vdd} 
+V3 in vss PULSE(0 {Vin} 1ps 1ps 1ps 50ns 100ns) DC{Vin} 
+C1 out vss 1f m=1
+x2 vdd out net1 net2 vss nand
+x3 vdd in net2 vss vss not
+**** begin user architecture code
+
+
+
+
+* Circuit Parameters
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vin  = 1.8
+.param iref = 200u
+.options TEMP = 65.0
+
+* Include Models
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
+
+* OP Parameters & Singals to save
+.save all  @M.X1.XM1.msky130_fd_pr__nfet_01v8[id] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vth]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vdsat]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM1.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gds]
+
+*Simulations
+.control
+  tran 0.1n 0.5u
+  setplot tran1
+  plot v(out) v(in)
+  setplot tran2
+  plot v(in)
+  setplot tran3
+  plot v(out)
+  write ~/caravel_fulgor_opamp/xschem/ring_osc/nand_tran1.raw
+
+
+
+.endc
+
+.end
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  /home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nand.sym # of pins=5
+
+.subckt nand  vdd A OUT B vss
+*.opin OUT
+*.ipin vdd
+*.ipin A
+*.ipin B
+*.ipin vss
+XM1 net1 B vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM2 OUT A net1 vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM3 net2 A vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM4 OUT B net2 vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM5 OUT A vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM6 OUT B vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+.ends
+
+
+* expanding   symbol:  /home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym # of pins=5
+
+.subckt not  vdd in out vss vbulk
+*.ipin vdd
+*.ipin in
+*.ipin vss
+*.opin out
+*.ipin vbulk
+XM1 out in vss vbulk sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+.ends
+
+.GLOBAL GND
+.end

diff --git a/xschem/ring_vco/FFD.sym b/xschem/ring_vco/FFD.sym
new file mode 100644
index 0000000..588ebff
--- /dev/null
+++ b/xschem/ring_vco/FFD.sym

@@ -0,0 +1,34 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -40 -30 -40 30 {}
+L 4 40 -30 40 30 {}
+L 4 0 -70 0 -50 {}
+L 4 -60 -30 -40 -30 {}
+L 4 40 0 60 0 {}
+L 4 0 50 0 70 {}
+L 4 -40 -50 40 -50 {}
+L 4 -40 50 40 50 {}
+L 4 40 30 40 50 {}
+L 4 -40 30 -40 50 {}
+L 4 -40 -50 -40 -30 {}
+L 4 40 -50 40 -30 {}
+L 4 -60 0 -40 0 {}
+B 5 -2.5 -72.5 2.5 -67.5 {name=vdd dir=in name=p2 }
+B 5 -62.5 -32.5 -57.5 -27.5 {name=T dir=in name=p1 }
+B 5 57.5 -2.5 62.5 2.5 {name=OUT dir=out name=p3 }
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=in name=p6 }
+B 5 -62.5 -2.5 -57.5 2.5 {name=CLK dir=in name=p1 }
+T {@symname} -41.5 14 0 0 0.3 0.3 {}
+T {@name} -15 -22 0 0 0.2 0.2 {}
+T {vdd} -6 -75 1 0 0.2 0.2 {}
+T {T} -35 -34 0 0 0.2 0.2 {}
+T {OUT} 35 -4 0 1 0.2 0.2 {}
+T {vss} -14 75 3 0 0.2 0.2 {}
+T {CLK} -35 -4 0 0 0.2 0.2 {}

diff --git a/xschem/ring_vco/FFD_xor.sch b/xschem/ring_vco/FFD_xor.sch
new file mode 100644
index 0000000..f8a6517
--- /dev/null
+++ b/xschem/ring_vco/FFD_xor.sch

@@ -0,0 +1,72 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1860 50 1890 50 { lab=OUT}
+N 1760 50 1860 50 { lab=OUT}
+N 1190 -150 1260 -150 { lab=D}
+N 1190 450 1300 450 { lab=CLK}
+N 1540 50 1760 50 { lab=OUT}
+N 1260 -150 1440 -150 { lab=D}
+N 1370 -130 1440 -130 { lab=OUT}
+N 1370 -130 1370 -70 { lab=OUT}
+N 1370 -70 1640 -20 { lab=OUT}
+N 1640 -20 1640 50 { lab=OUT}
+N 1370 40 1440 40 { lab=#net1}
+N 1370 -20 1370 40 { lab=#net1}
+N 1370 -20 1640 -70 { lab=#net1}
+N 1640 -140 1640 -70 { lab=#net1}
+N 1540 -140 1640 -140 { lab=#net1}
+N 1480 -10 1480 0 { lab=vdd}
+N 1480 -10 1510 -10 { lab=vdd}
+N 1480 -90 1480 -80 { lab=vss}
+N 1480 -80 1510 -80 { lab=vss}
+N 1480 -200 1480 -190 { lab=vdd}
+N 1480 -200 1510 -200 { lab=vdd}
+N 1480 100 1480 110 { lab=vss}
+N 1480 110 1510 110 { lab=vss}
+N 1370 260 1440 260 { lab=#net2}
+N 1370 260 1370 320 { lab=#net2}
+N 1370 320 1640 370 { lab=#net2}
+N 1640 370 1640 440 { lab=#net2}
+N 1370 430 1440 430 { lab=#net3}
+N 1370 370 1370 430 { lab=#net3}
+N 1370 370 1640 320 { lab=#net3}
+N 1640 250 1640 320 { lab=#net3}
+N 1540 250 1640 250 { lab=#net3}
+N 1480 380 1480 390 { lab=vdd}
+N 1480 380 1510 380 { lab=vdd}
+N 1480 300 1480 310 { lab=vss}
+N 1480 310 1510 310 { lab=vss}
+N 1480 190 1480 200 { lab=vdd}
+N 1480 190 1510 190 { lab=vdd}
+N 1480 490 1480 500 { lab=#net4}
+N 1480 500 1510 500 { lab=#net4}
+N 1370 40 1370 240 { lab=#net1}
+N 1370 240 1440 240 { lab=#net1}
+N 1640 160 1640 250 { lab=#net3}
+N 1400 160 1640 160 { lab=#net3}
+N 1400 60 1400 160 { lab=#net3}
+N 1400 60 1440 60 { lab=#net3}
+N 1540 440 1640 440 { lab=#net2}
+N 1300 450 1440 450 { lab=CLK}
+C {ipin.sym} 1510 -200 2 0 {name=p2 lab=vdd}
+C {ipin.sym} 1510 500 2 0 {name=p6 lab=vss}
+C {opin.sym} 1890 50 0 0 {name=p3 lab=OUT}
+C {ipin.sym} 1190 -150 0 0 {name=p4 lab=D}
+C {ipin.sym} 1190 450 0 0 {name=p1 lab=CLK}
+C {lab_pin.sym} 1510 -80 2 0 {name=l5 sig_type=std_logic lab=vss}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nor.sym} 1480 -140 0 0 {name=x1}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nor.sym} 1480 50 0 0 {name=x2}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nor.sym} 1480 250 0 0 {name=x3}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nor.sym} 1480 440 0 0 {name=x4}
+C {lab_pin.sym} 1510 110 2 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1510 310 2 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1510 -10 2 0 {name=l7 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 1510 190 2 0 {name=l8 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 1510 380 2 0 {name=l9 sig_type=std_logic lab=vdd
+}

diff --git a/xschem/ring_vco/FFD_xor.sym b/xschem/ring_vco/FFD_xor.sym
new file mode 100644
index 0000000..91b1208
--- /dev/null
+++ b/xschem/ring_vco/FFD_xor.sym

@@ -0,0 +1,30 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -40 -40 -40 40 {}
+L 4 40 -40 40 40 {}
+L 4 0 -60 0 -40 {}
+L 4 -60 -30 -40 -30 {}
+L 4 40 0 60 0 {}
+L 4 -60 0 -40 0 {}
+L 4 0 40 0 60 {}
+L 4 -40 40 40 40 {}
+L 4 -40 -40 40 -40 {}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=in name=p2 }
+B 5 -62.5 -32.5 -57.5 -27.5 {name=D dir=in name=p4 }
+B 5 57.5 -2.5 62.5 2.5 {name=OUT dir=out name=p3 }
+B 5 -62.5 -2.5 -57.5 2.5 {name=CLK dir=in name=p1 }
+B 5 -2.5 57.5 2.5 62.5 {name=vss dir=in name=p6 }
+T {@symname} 10.5 44 0 0 0.3 0.3 {}
+T {@name} 5 -52 0 0 0.2 0.2 {}
+T {vdd} 4 -35 1 0 0.2 0.2 {}
+T {D} -35 -34 0 0 0.2 0.2 {}
+T {OUT} 45 -4 0 1 0.2 0.2 {}
+T {CLK} -35 -4 0 0 0.2 0.2 {}
+T {vss} -4 35 3 0 0.2 0.2 {}

diff --git a/xschem/ring_vco/nand.sch b/xschem/ring_vco/nand.sch
new file mode 100644
index 0000000..b4a22fa
--- /dev/null
+++ b/xschem/ring_vco/nand.sch

@@ -0,0 +1,81 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 300 -0 460 -0 { lab=OUT}
+N 360 90 360 120 { lab=#net1}
+N 360 180 360 200 { lab=vss}
+N 280 -130 280 -100 { lab=vdd}
+N 280 -130 440 -130 { lab=vdd}
+N 440 -130 440 -100 { lab=vdd}
+N 280 -70 440 -70 { lab=vdd}
+N 280 -70 360 -70 { lab=vdd}
+N 360 -130 360 -70 { lab=vdd}
+N 280 60 320 60 { lab=A}
+N 200 -70 240 -70 { lab=A}
+N 480 -70 520 -70 { lab=B}
+N 460 0 540 -0 { lab=OUT}
+N 280 150 320 150 { lab=B}
+N 280 200 360 200 { lab=vss}
+N 200 -130 280 -130 { lab=vdd}
+N 360 0 360 30 { lab=OUT}
+N 280 -40 280 0 { lab=OUT}
+N 280 0 300 -0 { lab=OUT}
+N 440 -40 440 -0 { lab=OUT}
+N 360 60 440 60 { lab=vss}
+N 440 60 440 200 { lab=vss}
+N 360 200 440 200 { lab=vss}
+N 360 150 440 150 { lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} 340 150 0 0 {name=M1
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 340 60 0 0 {name=M2
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 260 -70 0 0 {name=M5
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 460 -70 0 1 {name=M6
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {opin.sym} 540 0 0 0 {name=p1 lab=OUT}
+C {ipin.sym} 200 -130 0 0 {name=p2 lab=vdd}
+C {ipin.sym} 200 -70 0 0 {name=p3 lab=A}
+C {ipin.sym} 280 150 0 0 {name=p5 lab=B}
+C {ipin.sym} 280 200 0 0 {name=p6 lab=vss}
+C {lab_pin.sym} 280 60 0 0 {name=l1 sig_type=std_logic lab=A}
+C {lab_pin.sym} 520 -70 2 0 {name=l2 sig_type=std_logic lab=B}

diff --git a/xschem/ring_vco/nand.sym b/xschem/ring_vco/nand.sym
new file mode 100644
index 0000000..06a655f
--- /dev/null
+++ b/xschem/ring_vco/nand.sym

@@ -0,0 +1,32 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -10 -60 -10 -40 {}
+L 4 -60 -20 -40 -20 {}
+L 4 50 0 70 0 {}
+L 4 -60 20 -40 20 {}
+L 4 -10 40 -10 60 {}
+L 4 -30 -40 0 -40 {}
+L 4 -40 -40 -40 40 {}
+L 4 -40 40 0 40 {}
+L 4 -40 -40 -30 -40 {}
+B 5 -12.5 -62.5 -7.5 -57.5 {name=vdd dir=in name=p2 }
+B 5 -62.5 -22.5 -57.5 -17.5 {name=A dir=in name=p3 }
+B 5 67.5 -2.5 72.5 2.5 {name=OUT dir=out name=p1 }
+B 5 -62.5 17.5 -57.5 22.5 {name=B dir=in name=p5 }
+B 5 -12.5 57.5 -7.5 62.5 {name=vss dir=in name=p6 }
+A 4 -5 -0 40.31128874149275 277.1250163489018 165.7499673021964 {}
+A 4 43 -0.5 7.017834423809099 355.9143832200251 360 {}
+T {@symname} -36 -6 0 0 0.3 0.3 {}
+T {@name} -25 -22 0 0 0.2 0.2 {}
+T {vdd} -16 -55 1 0 0.2 0.2 {}
+T {A} -55 -34 0 0 0.2 0.2 {}
+T {OUT} 75 -14 0 1 0.2 0.2 {}
+T {B} -55 6 0 0 0.2 0.2 {}
+T {vss} -24 65 3 0 0.2 0.2 {}

diff --git a/xschem/ring_vco/nand3.sch b/xschem/ring_vco/nand3.sch
new file mode 100644
index 0000000..dcdf45f
--- /dev/null
+++ b/xschem/ring_vco/nand3.sch

@@ -0,0 +1,120 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 300 -0 460 -0 { lab=OUT}
+N 490 90 490 120 { lab=#net1}
+N 490 180 490 200 { lab=#net2}
+N 280 -130 280 -100 { lab=vdd}
+N 280 -130 440 -130 { lab=vdd}
+N 410 60 450 60 { lab=A}
+N 200 -70 240 -70 { lab=A}
+N 410 -70 450 -70 { lab=B}
+N 410 150 450 150 { lab=B}
+N 410 310 490 310 { lab=vss}
+N 200 -130 280 -130 { lab=vdd}
+N 280 -40 280 0 { lab=OUT}
+N 280 0 300 -0 { lab=OUT}
+N 490 60 570 60 { lab=vss}
+N 570 60 570 200 { lab=vss}
+N 490 310 570 310 { lab=vss}
+N 490 150 570 150 { lab=vss}
+N 590 -70 630 -70 { lab=C}
+N 670 -40 670 0 { lab=OUT}
+N 460 -0 670 0 { lab=OUT}
+N 670 -0 760 -0 { lab=OUT}
+N 670 -130 670 -100 { lab=vdd}
+N 440 -130 670 -130 { lab=vdd}
+N 490 -70 550 -70 { lab=vdd}
+N 550 -130 550 -70 { lab=vdd}
+N 490 -130 490 -100 { lab=vdd}
+N 490 -40 490 0 { lab=OUT}
+N 670 -70 730 -70 { lab=vdd}
+N 730 -130 730 -70 { lab=vdd}
+N 670 -130 730 -130 { lab=vdd}
+N 280 -70 350 -70 { lab=vdd}
+N 350 -130 350 -70 { lab=vdd}
+N 490 -0 490 30 { lab=OUT}
+N 490 200 490 220 { lab=#net2}
+N 490 280 490 310 { lab=vss}
+N 490 250 570 250 { lab=vss}
+N 570 200 570 250 { lab=vss}
+N 570 250 570 310 { lab=vss}
+N 410 250 450 250 { lab=C}
+C {sky130_fd_pr/nfet_01v8.sym} 470 150 0 0 {name=M1
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 470 60 0 0 {name=M2
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 260 -70 0 0 {name=M5
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 470 -70 0 0 {name=M6
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {opin.sym} 760 0 0 0 {name=p1 lab=OUT}
+C {ipin.sym} 200 -130 0 0 {name=p2 lab=vdd}
+C {ipin.sym} 200 -70 0 0 {name=p3 lab=A}
+C {ipin.sym} 410 150 0 0 {name=p5 lab=B}
+C {ipin.sym} 410 310 0 0 {name=p6 lab=vss}
+C {lab_pin.sym} 410 60 0 0 {name=l1 sig_type=std_logic lab=A}
+C {lab_pin.sym} 410 -70 2 1 {name=l2 sig_type=std_logic lab=B}
+C {sky130_fd_pr/pfet_01v8.sym} 650 -70 0 0 {name=M3
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 590 -70 2 1 {name=l3 sig_type=std_logic lab=C}
+C {sky130_fd_pr/nfet_01v8.sym} 470 250 0 0 {name=M4
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {ipin.sym} 410 250 0 0 {name=p4 lab=C}

diff --git a/xschem/ring_vco/nand3.sym b/xschem/ring_vco/nand3.sym
new file mode 100644
index 0000000..9bde173
--- /dev/null
+++ b/xschem/ring_vco/nand3.sym

@@ -0,0 +1,34 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -10 -70 -10 -50 {}
+L 4 -60 0 -40 0 {}
+L 4 60 0 80 0 {}
+L 4 -60 -30 -40 -30 {}
+L 4 -60 30 -40 30 {}
+L 4 -10 50 -10 70 {}
+L 4 -40 -50 -40 50 {}
+L 4 -40 50 0 50 {}
+L 4 -40 -50 0 -50 {}
+B 5 -12.5 -72.5 -7.5 -67.5 {name=vdd dir=in name=p2 }
+B 5 -62.5 -2.5 -57.5 2.5 {name=A dir=in name=p3 }
+B 5 77.5 -2.5 82.5 2.5 {name=OUT dir=out name=p1 }
+B 5 -62.5 -32.5 -57.5 -27.5 {name=B dir=in name=p5 }
+B 5 -62.5 27.5 -57.5 32.5 {name=C dir=in name=p4 }
+B 5 -12.5 67.5 -7.5 72.5 {name=vss dir=in name=p6 }
+A 4 -0 -0 50 270 180 {}
+A 4 55 -0 5 0 360 {}
+T {@symname} -40.5 4 0 0 0.3 0.3 {}
+T {@name} -15 -22 0 0 0.2 0.2 {}
+T {vdd} -6 -45 1 0 0.2 0.2 {}
+T {A} -55 -14 0 0 0.2 0.2 {}
+T {OUT} 75 -14 0 1 0.2 0.2 {}
+T {B} -55 -44 0 0 0.2 0.2 {}
+T {C} -55 16 0 0 0.2 0.2 {}
+T {vss} -14 45 3 0 0.2 0.2 {}

diff --git a/xschem/ring_vco/nor.sch b/xschem/ring_vco/nor.sch
new file mode 100644
index 0000000..5e1ff1f
--- /dev/null
+++ b/xschem/ring_vco/nor.sch

@@ -0,0 +1,85 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 140 -0 290 0 { lab=OUT}
+N 220 -140 220 -90 { lab=#net1}
+N 220 -240 220 -200 { lab=vdd}
+N 220 -60 280 -60 { lab=#net1}
+N 280 -110 280 -60 { lab=#net1}
+N 220 -110 280 -110 { lab=#net1}
+N 140 90 140 120 { lab=vss}
+N 140 120 290 120 { lab=vss}
+N 290 90 290 120 { lab=vss}
+N 140 60 290 60 { lab=vss}
+N 220 60 220 120 { lab=vss}
+N 60 60 100 60 { lab=A}
+N 330 60 370 60 { lab=B}
+N 290 0 400 -0 { lab=OUT}
+N 140 -60 180 -60 { lab=B}
+N 140 -170 180 -170 { lab=A}
+N 60 120 140 120 { lab=vss}
+N 140 -240 220 -240 { lab=vdd}
+N 290 -0 290 30 { lab=OUT}
+N 220 -30 220 0 { lab=OUT}
+N 140 0 140 30 { lab=OUT}
+N 220 -170 280 -170 { lab=vdd}
+N 280 -240 280 -170 { lab=vdd}
+N 220 -240 280 -240 { lab=vdd}
+C {sky130_fd_pr/nfet_01v8.sym} 120 60 0 0 {name=M1
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 200 -60 0 0 {name=M2
+L=0.15
+W=1.05
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 310 60 0 1 {name=M3
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 200 -170 0 0 {name=M4
+L=0.15
+W=1.05
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {ipin.sym} 140 -170 0 0 {name=p3 lab=A}
+C {opin.sym} 400 0 0 0 {name=p1 lab=OUT}
+C {ipin.sym} 140 -60 0 0 {name=p2 lab=B
+}
+C {ipin.sym} 140 -240 0 0 {name=p4 lab=vdd
+}
+C {ipin.sym} 60 120 0 0 {name=p5 lab=vss
+}
+C {lab_pin.sym} 60 60 0 0 {name=l1 sig_type=std_logic lab=A}
+C {lab_pin.sym} 370 60 2 0 {name=l3 sig_type=std_logic lab=B
+}

diff --git a/xschem/ring_vco/nor.sym b/xschem/ring_vco/nor.sym
new file mode 100644
index 0000000..daee6e6
--- /dev/null
+++ b/xschem/ring_vco/nor.sym

@@ -0,0 +1,29 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 0 -50 0 -30 {}
+L 4 -40 -10 -20 -10 {}
+L 4 -40 10 -20 10 {}
+L 4 40 0 60 0 {}
+L 4 0 30 0 50 {}
+B 5 -2.5 -52.5 2.5 -47.5 {name=vdd dir=in name=p4 }
+B 5 -42.5 -12.5 -37.5 -7.5 {name=A dir=in name=p3 }
+B 5 -42.5 7.5 -37.5 12.5 {name=B dir=in name=p2 }
+B 5 57.5 -2.5 62.5 2.5 {name=OUT dir=out name=p1 }
+B 5 -2.5 47.5 2.5 52.5 {name=vss dir=in name=p5 }
+A 4 -55 85 127.4754878398196 41.82016988013577 36.86989764584401 {}
+A 4 -55 -85 127.4754878398196 281.3099324740202 36.86989764584399 {}
+A 4 -100 0 80.62257748298549 330.2551187030577 59.48976259388451 {}
+T {@symname} -31.5 -6 0 0 0.3 0.3 {}
+T {@name} 15 -42 0 0 0.2 0.2 {}
+T {vdd} 4 -25 1 0 0.2 0.2 {}
+T {A} -35 -24 0 0 0.2 0.2 {}
+T {B} -35 -4 0 0 0.2 0.2 {}
+T {OUT} 65 -14 0 1 0.2 0.2 {}
+T {vss} -4 25 3 0 0.2 0.2 {}

diff --git a/xschem/ring_vco/ring_vco.sch b/xschem/ring_vco/ring_vco.sch
index 27a8ddf..ddaa918 100644
--- a/xschem/ring_vco/ring_vco.sch
+++ b/xschem/ring_vco/ring_vco.sch

@@ -27,7 +27,7 @@
 N 330 -80 330 -30 { lab=10}
 N 440 -80 440 -30 { lab=10}
 N 550 -80 550 -30 { lab=10}
-N 2520 0 2620 0 { lab=out}
+N 2520 0 2620 0 { lab=out_vco}
 N -0 -80 550 -80 { lab=10}
 N 550 -80 640 -80 { lab=10}
 N 290 -200 290 -80 { lab=10}
@@ -75,7 +75,7 @@
 N -0 60 0 80 { lab=9}
 N 110 60 110 80 { lab=9}
 N 220 60 220 80 { lab=9}
-N 2520 -30 2520 30 { lab=out}
+N 2520 -30 2520 30 { lab=out_vco}
 N 2520 90 2520 120 { lab=vss}
 N 2520 120 2610 120 { lab=vss}
 N 2610 60 2610 120 { lab=vss}
@@ -200,6 +200,34 @@
 N 2250 0 2260 -0 { lab=#net1}
 N 2200 80 2290 80 { lab=9}
 N 2200 -80 2290 -80 { lab=10}
+N 770 210 770 240 { lab=vdd}
+N 770 380 770 400 { lab=vss}
+N 670 310 700 310 { lab=out_vco}
+N 770 400 770 420 { lab=vss}
+N 640 310 670 310 { lab=out_vco}
+N 970 210 970 240 { lab=vdd}
+N 970 380 970 400 { lab=vss}
+N 870 310 900 310 { lab=outx2}
+N 970 400 970 420 { lab=vss}
+N 840 310 870 310 { lab=outx2}
+N 1170 210 1170 240 { lab=vdd}
+N 1170 380 1170 400 { lab=vss}
+N 1070 310 1100 310 { lab=outx4}
+N 1170 400 1170 420 { lab=vss}
+N 1040 310 1070 310 { lab=outx4}
+N 1370 210 1370 240 { lab=vdd}
+N 1370 380 1370 400 { lab=vss}
+N 1270 310 1300 310 { lab=outx8}
+N 1370 400 1370 420 { lab=vss}
+N 1240 310 1270 310 { lab=outx8}
+N 1570 210 1570 240 { lab=vdd}
+N 1570 380 1570 400 { lab=vss}
+N 1470 310 1500 310 { lab=outx16}
+N 1570 400 1570 420 { lab=vss}
+N 1440 310 1470 310 { lab=outx16}
+N 1640 310 1690 310 { lab=out}
+N 1690 310 1690 350 { lab=out}
+N 1690 410 1690 440 { lab=vss}
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 0 0 0 0 {name=x1}
 C {vsource.sym} 480 -330 0 0 {name=V1 value=DC\{Vss\}}
 C {vsource.sym} 570 -330 0 0 {name=V2 value=DC\{Vdd\}}
@@ -221,7 +249,7 @@
 .options TEMP = 65.0
 
 * Include Models
-.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib SS
 
 * OP Parameters & Singals to save
 .save all
@@ -234,26 +262,25 @@
 
 *Simulations
 .control
-  *reset
   tran 0.05n 1u
   setplot tran1
-  plot v(out) v(in)
+  plot v(out) v(outx16)+2 v(outx8)+4 v(outx4)+6 v(outx2)+8 v(out_vco)+10
   linearize
   set specwindow="blackman"
+  fft v(out_vco)
+  spec 10 1000000 1000 v(out_vco)
+  plot mag(v(out_vco))
+  
+  reset
+  tran 0.05n 1u
+  setplot tran2
+  linearize
   fft v(out)
   spec 10 1000000 1000 v(out)
   plot mag(v(out))
   *write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_closeloop_tran1.raw
   
   
-  *dc V3 0 1.8 0.01
-  *setplot dc1
-  *plot v(out1) v(out2) v(out3) v(in)
-  
-  reset
-  op
-  setplot op1
-  
 .endc
 
 .end
@@ -311,7 +338,7 @@
 spiceprefix=X
 }
 C {lab_wire.sym} 2420 0 0 0 {name=l4 sig_type=std_logic lab=out_ring}
-C {lab_pin.sym} 2620 0 2 0 {name=l6 sig_type=std_logic lab=out}
+C {lab_pin.sym} 2620 0 2 0 {name=l6 sig_type=std_logic lab=out_vco}
 C {sky130_fd_pr/pfet_01v8.sym} 270 -230 0 0 {name=M5
 L=0.15
 W=1.5
@@ -389,3 +416,35 @@
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1950 0 0 0 {name=x18}
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 2070 0 0 0 {name=x19}
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 2200 0 0 0 {name=x20}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 770 310 0 0 {name=x21}
+C {lab_pin.sym} 770 210 1 0 {name=l28 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 770 420 3 0 {name=l29 sig_type=std_logic lab=vss}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 970 310 0 0 {name=x22}
+C {lab_pin.sym} 970 210 1 0 {name=l30 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 970 420 3 0 {name=l31 sig_type=std_logic lab=vss}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 1170 310 0 0 {name=x23}
+C {lab_pin.sym} 1170 210 1 0 {name=l32 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 1170 420 3 0 {name=l33 sig_type=std_logic lab=vss}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 1370 310 0 0 {name=x24}
+C {lab_pin.sym} 1370 210 1 0 {name=l34 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 1370 420 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 1570 310 0 0 {name=x25}
+C {lab_pin.sym} 1570 210 1 0 {name=l36 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 1570 420 3 0 {name=l37 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 640 310 0 0 {name=l38 sig_type=std_logic lab=out_vco}
+C {lab_pin.sym} 1690 310 2 0 {name=l39 sig_type=std_logic lab=out}
+C {lab_wire.sym} 1090 310 0 0 {name=l41 sig_type=std_logic lab=outx4}
+C {lab_wire.sym} 890 310 0 0 {name=l40 sig_type=std_logic lab=outx2}
+C {lab_wire.sym} 1290 310 0 0 {name=l42 sig_type=std_logic lab=outx8}
+C {lab_wire.sym} 1490 310 0 0 {name=l43 sig_type=std_logic lab=outx16}
+C {capa.sym} 1690 380 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1690 440 3 0 {name=l44 sig_type=std_logic lab=vss}

diff --git a/xschem/ring_vco/untitled.sch b/xschem/ring_vco/untitled.sch
new file mode 100644
index 0000000..4b34c92
--- /dev/null
+++ b/xschem/ring_vco/untitled.sch

@@ -0,0 +1,109 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 300 -10 300 10 { lab=OUT}
+N 460 -10 460 10 { lab=OUT}
+N 300 -0 460 -0 { lab=OUT}
+N 300 70 300 100 { lab=#net1}
+N 300 160 300 180 { lab=vss}
+N 300 180 460 180 { lab=vss}
+N 460 160 460 180 { lab=vss}
+N 300 130 380 130 { lab=vss}
+N 380 130 380 180 { lab=vss}
+N 380 130 460 130 { lab=vss}
+N 460 70 460 100 { lab=#net2}
+N 300 40 460 40 { lab=vss}
+N 380 40 380 130 { lab=vss}
+N 300 -100 300 -70 { lab=vdd}
+N 300 -100 460 -100 { lab=vdd}
+N 460 -100 460 -70 { lab=vdd}
+N 300 -40 460 -40 { lab=vdd}
+N 300 -40 380 -40 { lab=vdd}
+N 380 -100 380 -40 { lab=vdd}
+N 220 40 260 40 { lab=A}
+N 220 -40 260 -40 { lab=A}
+N 500 -40 540 -40 { lab=B}
+N 460 0 540 -0 { lab=OUT}
+N 500 40 540 40 { lab=B}
+N 500 130 540 130 { lab=A}
+N 220 130 260 130 { lab=B}
+N 220 180 300 180 { lab=vss}
+N 220 -100 300 -100 { lab=vdd}
+C {sky130_fd_pr/nfet_01v8.sym} 280 130 0 0 {name=M1
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 280 40 0 0 {name=M2
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 480 130 0 1 {name=M3
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 480 40 0 1 {name=M4
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 280 -40 0 0 {name=M5
+L=0.15
+W=0.9
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 480 -40 0 1 {name=M6
+L=0.15
+W=0.9
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {opin.sym} 540 0 0 0 {name=p1 lab=OUT}
+C {ipin.sym} 220 -100 0 0 {name=p2 lab=vdd}
+C {ipin.sym} 220 -40 0 0 {name=p3 lab=A}
+C {ipin.sym} 220 130 0 0 {name=p5 lab=B}
+C {ipin.sym} 220 180 0 0 {name=p6 lab=vss}
+C {lab_pin.sym} 220 40 0 0 {name=l1 sig_type=std_logic lab=A}
+C {lab_pin.sym} 540 -40 2 0 {name=l2 sig_type=std_logic lab=B}
+C {lab_pin.sym} 540 40 2 0 {name=l3 sig_type=std_logic lab=B}
+C {lab_pin.sym} 540 130 2 0 {name=l4 sig_type=std_logic lab=A}