verilog/gl/user_project_wrapper.v

/* Generated by Yosys 0.9+2406 (git sha1 347dd01, gcc 8.3.1 -fPIC -Os) */

module user_project_wrapper(user_clock2, vccd1, vccd2, vdda1, vdda2, vssa1, vssa2, vssd1, vssd2, wb_clk_i, wb_rst_i, wbs_ack_o, wbs_cyc_i, wbs_stb_i, wbs_we_i, VPWR, VGND, io_in, io_oeb, io_out, analog_io, la_data_in, la_data_out, la_oen, wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i);
  input VGND;
  input VPWR;
  output [36:0] io_oeb;
  output [36:0] io_out;
  inout  [30:0] analog_io;
  input [127:0] la_data_in;
  output [127:0] la_data_out;
  input [127:0] la_oen;
  input user_clock2;
  inout vccd1;
  inout vccd2;
  inout vdda1;
  inout vdda2;
  inout vssa1;
  inout vssa2;
  inout vssd1;
  inout vssd2;
  input wb_clk_i;
  input wb_rst_i;
  output wbs_ack_o;
  input [31:0] wbs_adr_i;
  input wbs_cyc_i;
  input [31:0] wbs_dat_i;
  output [31:0] wbs_dat_o;
  input [3:0] wbs_sel_i;
  input wbs_stb_i;
  input wbs_we_i;
  
  opamp_v1 opamp_v1_0();

  opamp_v1 opamp_v1_1();

  opamp_v1 opamp_v1_2();

  opamp_v1 opamp_v1_3();
  
  opamp_v1 opamp_v1_4();
  
  opamp_v1 opamp_v1_5();

  opamp_v1 opamp_v1_6();

  PLL_ PLL__0(); 

endmodule