blob: 52ec1cd41095920de3ab2117d9e6114c005f2f42 [file] [log] [blame]
Matt Venn08cd6eb2020-11-16 12:01:14 +01001`default_nettype none
shalanfd13eb52020-08-21 16:48:07 +02002module dummy_slave(
3 input wb_clk_i,
4 input wb_rst_i,
5
6 input wb_stb_i,
7 input wb_cyc_i,
8 input wb_we_i,
9 input [3:0] wb_sel_i,
10 input [31:0] wb_adr_i,
11 input [31:0] wb_dat_i,
12
13 output reg [31:0] wb_dat_o,
14 output reg wb_ack_o
15);
16 reg [31:0] store;
17
18 wire valid = wb_cyc_i & wb_stb_i;
19
20 always @(posedge wb_clk_i) begin
21 if (wb_rst_i == 1'b 1) begin
22 wb_ack_o <= 1'b 0;
23 end else begin
24 if (wb_we_i == 1'b 1) begin
25 if (wb_sel_i[0]) store[7:0] <= wb_dat_i[7:0];
26 if (wb_sel_i[1]) store[15:8] <= wb_dat_i[15:8];
27 if (wb_sel_i[2]) store[23:16] <= wb_dat_i[23:16];
28 if (wb_sel_i[3]) store[31:24] <= wb_dat_i[31:24];
29 end
30 wb_dat_o <= store;
31 wb_ack_o <= valid & !wb_ack_o;
32 end
33 end
34endmodule