| Ahmed Ghazy | 72e52c6 | 2020-10-26 16:44:41 +0200 | [diff] [blame] | 1 | set script_dir [file dirname [file normalize [info script]]] |
| 2 | |
| 3 | set ::env(DESIGN_NAME) chip_io |
| 4 | |
| 5 | set ::env(VERILOG_FILES) "\ |
| Ahmed Ghazy | f744e2e | 2020-11-06 11:32:09 +0200 | [diff] [blame] | 6 | $script_dir/../../verilog/rtl/defines.v\ |
| Ahmed Ghazy | 72e52c6 | 2020-10-26 16:44:41 +0200 | [diff] [blame] | 7 | $script_dir/../../verilog/rtl/pads.v\ |
| 8 | $script_dir/../../verilog/rtl/mprj_io.v\ |
| 9 | $script_dir/../../verilog/rtl/chip_io.v" |
| 10 | |
| 11 | # The removal of this line is pending the IO verilog files being parsable by yosys... |
| 12 | set ::env(VERILOG_FILES_BLACKBOX) "$script_dir/../../verilog/stubs/sky130_fd_io__top_xres4v2.v" |
| 13 | |
| 14 | set ::env(DESIGN_IS_PADFRAME) 1 |
| 15 | set ::env(SYNTH_FLAT_TOP) 1 |
| 16 | set ::env(USE_GPIO_PADS) 1 |
| 17 | |
| Ahmed Ghazy | a997ad9 | 2020-11-25 04:02:15 +0200 | [diff] [blame] | 18 | |
| Ahmed Ghazy | 72e52c6 | 2020-10-26 16:44:41 +0200 | [diff] [blame] | 19 | set ::env(FP_SIZING) absolute |
| Ahmed Ghazy | a997ad9 | 2020-11-25 04:02:15 +0200 | [diff] [blame] | 20 | |
| 21 | set fd [open "$script_dir/../chip_dimensions.txt" "r"] |
| 22 | set ::env(DIE_AREA) [read $fd] |
| 23 | close $fd |
| Ahmed Ghazy | ec81bd2 | 2020-11-19 16:09:08 +0200 | [diff] [blame] | 24 | |
| Ahmed Ghazy | f744e2e | 2020-11-06 11:32:09 +0200 | [diff] [blame] | 25 | |
| 26 | set ::env(MAGIC_WRITE_FULL_LEF) 1 |
| Ahmed Ghazy | ec81bd2 | 2020-11-19 16:09:08 +0200 | [diff] [blame] | 27 | |
| 28 | set ::env(DIODE_INSERTION_STRATEGY) 0 |
| Ahmed Ghazy | a997ad9 | 2020-11-25 04:02:15 +0200 | [diff] [blame] | 29 | set ::env(GLB_RT_TILES) 12 |
| Ahmed Ghazy | ec81bd2 | 2020-11-19 16:09:08 +0200 | [diff] [blame] | 30 | set ::env(GLB_RT_UNIDIRECTIONAL) 0 |
| 31 | # set ::env(GLB_RT_ALLOW_CONGESTION) 1 |
| Ahmed Ghazy | a997ad9 | 2020-11-25 04:02:15 +0200 | [diff] [blame] | 32 | # set ::env(GLB_RT_OVERFLOW_ITERS) 150 |
