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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-018 / a115bddf527cad3f04f350a54d0bfbadc55a51ae / . / verilog / rtl / pads.v
blob: 0e914b62e11104aafe3c7eaa8383acb1b277783b [file] [log] [blame]
Tim Edwards581068f2020-11-19 12:45:25 -0500[diff] [blame]1// `default_nettype none
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]2`ifndef TOP_ROUTING
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]3 `define USER1_ABUTMENT_PINS \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]4 .AMUXBUS_A(analog_a),\
5 .AMUXBUS_B(analog_b),\
6 .VSSA(vssa1),\
7 .VDDA(vdda1),\
8 .VSWITCH(vddio),\
9 .VDDIO_Q(vddio_q),\
10 .VCCHIB(vccd),\
11 .VDDIO(vddio),\
12 .VCCD(vccd1),\
13 .VSSIO(vssio),\
14 .VSSD(vssd1),\
15 .VSSIO_Q(vssio_q),
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]16
17 `define USER2_ABUTMENT_PINS \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]18 .AMUXBUS_A(analog_a),\
19 .AMUXBUS_B(analog_b),\
20 .VSSA(vssa2),\
21 .VDDA(vdda2),\
22 .VSWITCH(vddio),\
23 .VDDIO_Q(vddio_q),\
24 .VCCHIB(vccd),\
25 .VDDIO(vddio),\
26 .VCCD(vccd2),\
27 .VSSIO(vssio),\
28 .VSSD(vssd2),\
29 .VSSIO_Q(vssio_q),
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]30
31 `define MGMT_ABUTMENT_PINS \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]32 .AMUXBUS_A(analog_a),\
33 .AMUXBUS_B(analog_b),\
34 .VSSA(vssa),\
35 .VDDA(vdda),\
36 .VSWITCH(vddio),\
37 .VDDIO_Q(vddio_q),\
38 .VCCHIB(vccd),\
39 .VDDIO(vddio),\
40 .VCCD(vccd),\
41 .VSSIO(vssio),\
Tim Edwards21a9aac2020-10-12 22:05:18 -0400[diff] [blame]42 .VSSD(vssd),\
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]43 .VSSIO_Q(vssio_q),
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]44`else
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]45 `define USER1_ABUTMENT_PINS
46 `define USER2_ABUTMENT_PINS
47 `define MGMT_ABUTMENT_PINS
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]48`endif
49
Tim Edwardsf645a842020-10-10 21:36:49 -0400[diff] [blame]50`define HVCLAMP_PINS(H,L) \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]51 .DRN_HVC(H), \
52 .SRC_BDY_HVC(L)
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]53
Tim Edwardsf645a842020-10-10 21:36:49 -0400[diff] [blame]54`define LVCLAMP_PINS(H1,L1,H2,L2,L3) \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]55 .BDY2_B2B(L3), \
56 .DRN_LVC1(H1), \
57 .DRN_LVC2(H2), \
58 .SRC_BDY_LVC1(L1), \
59 .SRC_BDY_LVC2(L2)
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]60
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]61`define INPUT_PAD(X,Y) \
62 wire loop_``X; \
Ahmed Ghazydf4dd882020-11-25 18:38:42 +0200[diff] [blame]63 sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]64 `MGMT_ABUTMENT_PINS \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]65 `ifndef TOP_ROUTING \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]66 .PAD(X), \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]67 `endif \
Tim Edwards21a9aac2020-10-12 22:05:18 -0400[diff] [blame]68 .OUT(vssd), \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]69 .OE_N(vccd), \
Tim Edwards21a9aac2020-10-12 22:05:18 -0400[diff] [blame]70 .HLD_H_N(vddio), \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]71 .ENABLE_H(porb_h), \
72 .ENABLE_INP_H(loop_``X), \
73 .ENABLE_VDDA_H(porb_h), \
74 .ENABLE_VSWITCH_H(vssa), \
75 .ENABLE_VDDIO(vccd), \
76 .INP_DIS(por), \
Tim Edwards21a9aac2020-10-12 22:05:18 -0400[diff] [blame]77 .IB_MODE_SEL(vssd), \
78 .VTRIP_SEL(vssd), \
79 .SLOW(vssd), \
80 .HLD_OVR(vssd), \
81 .ANALOG_EN(vssd), \
82 .ANALOG_SEL(vssd), \
83 .ANALOG_POL(vssd), \
84 .DM({vssd, vssd, vccd}), \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]85 .PAD_A_NOESD_H(), \
86 .PAD_A_ESD_0_H(), \
87 .PAD_A_ESD_1_H(), \
88 .IN(Y), \
89 .IN_H(), \
90 .TIE_HI_ESD(), \
Tim Edwards21a9aac2020-10-12 22:05:18 -0400[diff] [blame]91 .TIE_LO_ESD(loop_``X) )
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]92
Tim Edwardse2ef6732020-10-12 17:25:12 -0400[diff] [blame]93`define OUTPUT_PAD(X,Y,INPUT_DIS,OUT_EN_N) \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]94 wire loop_``X; \
Ahmed Ghazydf4dd882020-11-25 18:38:42 +0200[diff] [blame]95 sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]96 `MGMT_ABUTMENT_PINS \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]97 `ifndef TOP_ROUTING \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]98 .PAD(X), \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]99 `endif \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]100 .OUT(Y), \
101 .OE_N(OUT_EN_N), \
102 .HLD_H_N(vddio), \
103 .ENABLE_H(porb_h), \
104 .ENABLE_INP_H(loop_``X), \
105 .ENABLE_VDDA_H(porb_h), \
106 .ENABLE_VSWITCH_H(vssa), \
107 .ENABLE_VDDIO(vccd), \
Tim Edwardse2ef6732020-10-12 17:25:12 -0400[diff] [blame]108 .INP_DIS(INPUT_DIS), \
Tim Edwards21a9aac2020-10-12 22:05:18 -0400[diff] [blame]109 .IB_MODE_SEL(vssd), \
110 .VTRIP_SEL(vssd), \
111 .SLOW(vssd), \
112 .HLD_OVR(vssd), \
113 .ANALOG_EN(vssd), \
114 .ANALOG_SEL(vssd), \
115 .ANALOG_POL(vssd), \
116 .DM({vccd, vccd, vssd}), \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]117 .PAD_A_NOESD_H(), \
118 .PAD_A_ESD_0_H(), \
119 .PAD_A_ESD_1_H(), \
120 .IN(), \
121 .IN_H(), \
122 .TIE_HI_ESD(), \
123 .TIE_LO_ESD(loop_``X))
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]124
Tim Edwardse2ef6732020-10-12 17:25:12 -0400[diff] [blame]125`define INOUT_PAD(X,Y,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \
Ahmed Ghazydf4dd882020-11-25 18:38:42 +0200[diff] [blame]126 wire loop_``X; \
127 sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame]128 `MGMT_ABUTMENT_PINS \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]129 `ifndef TOP_ROUTING \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]130 .PAD(X),\
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]131 `endif \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]132 .OUT(Y_OUT), \
133 .OE_N(OUT_EN_N), \
134 .HLD_H_N(vddio), \
135 .ENABLE_H(porb_h), \
136 .ENABLE_INP_H(loop_``X), \
137 .ENABLE_VDDA_H(porb_h), \
138 .ENABLE_VSWITCH_H(vssa), \
139 .ENABLE_VDDIO(vccd), \
Tim Edwardse2ef6732020-10-12 17:25:12 -0400[diff] [blame]140 .INP_DIS(INPUT_DIS), \
Tim Edwards21a9aac2020-10-12 22:05:18 -0400[diff] [blame]141 .IB_MODE_SEL(vssd), \
142 .VTRIP_SEL(vssd), \
143 .SLOW(vssd), \
144 .HLD_OVR(vssd), \
145 .ANALOG_EN(vssd), \
146 .ANALOG_SEL(vssd), \
147 .ANALOG_POL(vssd), \
Tim Edwards4c733352020-10-12 16:32:36 -0400[diff] [blame]148 .DM(MODE), \
149 .PAD_A_NOESD_H(), \
150 .PAD_A_ESD_0_H(), \
151 .PAD_A_ESD_1_H(), \
152 .IN(Y), \
153 .IN_H(), \
154 .TIE_HI_ESD(), \
155 .TIE_LO_ESD(loop_``X) )
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]156
Tim Edwards581068f2020-11-19 12:45:25 -0500[diff] [blame]157// `default_nettype wire