| Ahmed Ghazy | f744e2e | 2020-11-06 11:32:09 +0200 | [diff] [blame] | 1 | set script_dir [file dirname [file normalize [info script]]] |
| 2 | |
| 3 | set ::env(DESIGN_NAME) gpio_control_block |
| 4 | set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg |
| 5 | |
| 6 | set ::env(VERILOG_FILES) "\ |
| 7 | $script_dir/../../verilog/rtl/defines.v\ |
| 8 | $script_dir/../../verilog/rtl/gpio_control_block.v" |
| 9 | set ::env(SYNTH_READ_BLACKBOX_LIB) 1 |
| 10 | |
| 11 | set ::env(CLOCK_PORT) "serial_clock" |
| 12 | set ::env(CLOCK_PERIOD) "10" |
| 13 | |
| 14 | set ::env(FP_SIZING) absolute |
| Ahmed Ghazy | dc1b301 | 2020-11-25 14:49:15 +0200 | [diff] [blame] | 15 | set ::env(DIE_AREA) "0 0 175 95" |
| 16 | |
| 17 | set ::env(PL_TARGET_DENSITY) 0.4 |
| 18 | set ::env(PL_BASIC_PLACEMENT) 1 |
| 19 | |
| 20 | # set ::env(FP_IO_VEXTEND) 20 |
| 21 | # set ::env(FP_IO_HEXTEND) 20 |
| 22 | set ::env(RIGHT_MARGIN_MULT) 272 |
| 23 | set ::env(FP_IO_HLENGTH) 200 |
| 24 | set ::env(GLB_RT_MAXLAYER) 4 |
