| Ahmed Ghazy | 5586f1b | 2020-11-06 21:34:43 +0200 | [diff] [blame] | 1 | set script_dir [file dirname [file normalize [info script]]] |
| 2 | # User config |
| 3 | set ::env(DESIGN_NAME) DFFRAM |
| 4 | |
| 5 | # Change if needed |
| Ahmed Ghazy | 1159d1a | 2020-11-09 22:30:16 +0200 | [diff] [blame] | 6 | set ::env(VERILOG_FILES) "\ |
| 7 | $script_dir/../../verilog/rtl/defines.v\ |
| agorararmard | 09a7237 | 2020-11-18 21:37:39 +0000 | [diff] [blame] | 8 | $script_dir/../../verilog/rtl/DFFRAM.v\ |
| 9 | $script_dir/../../verilog/rtl/DFFRAMBB.v" |
| Ahmed Ghazy | 1159d1a | 2020-11-09 22:30:16 +0200 | [diff] [blame] | 10 | |
| Ahmed Ghazy | 5586f1b | 2020-11-06 21:34:43 +0200 | [diff] [blame] | 11 | set ::env(SYNTH_TOP_LEVEL) 1 |
| 12 | set ::env(SYNTH_READ_BLACKBOX_LIB) 1 |
| 13 | # Fill this |
| 14 | set ::env(CLOCK_PERIOD) "10" |
| 15 | set ::env(CLOCK_PORT) "CLK" |
| 16 | set ::env(CLOCK_TREE_SYNTH) 0 |
| 17 | |
| 18 | set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg |
| 19 | |
| 20 | set ::env(FP_SIZING) absolute |
| Ahmed Ghazy | 2517fa8 | 2020-11-08 23:34:41 +0200 | [diff] [blame] | 21 | set ::env(DIE_AREA) "0 0 750 525" |
| Ahmed Ghazy | 5586f1b | 2020-11-06 21:34:43 +0200 | [diff] [blame] | 22 | |
| 23 | set ::env(PDN_CFG) $script_dir/pdn.tcl |
| Ahmed Ghazy | 1159d1a | 2020-11-09 22:30:16 +0200 | [diff] [blame] | 24 | set ::env(GLB_RT_MAXLAYER) 5 |
| Ahmed Ghazy | 5586f1b | 2020-11-06 21:34:43 +0200 | [diff] [blame] | 25 | |
| 26 | set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0 |
| 27 | set ::env(PL_TARGET_DENSITY) 0.85 |
| 28 | |
| 29 | set ::env(CELL_PAD) 0 |
| 30 | set ::env(DIODE_INSERTION_STRATEGY) 0 |
