Removed old user_project_wrapper files.

openlane/user_project_wrapper_bak/interactive.tcl

diff --git a/openlane/user_project_wrapper_bak/interactive.tcl b/openlane/user_project_wrapper_bak/interactive.tcl
deleted file mode 100644
index 394f62b..0000000
--- a/openlane/user_project_wrapper_bak/interactive.tcl
+++ /dev/null
@@ -1,65 +0,0 @@
-package require openlane
-set script_dir [file dirname [file normalize [info script]]]
-
-prep -design $script_dir -tag user_project_wrapper -overwrite
-set save_path $script_dir/../..
-
-verilog_elaborate
-
-init_floorplan
-
-place_io_ol
-
-set ::env(FP_DEF_TEMPATE) $script_dir/../../def/user_project_wrapper_empty.def
-
-apply_def_template
-
-add_macro_placement mprj 1150 1700 N
-
-manual_macro_placement f
-
-set ::env(_SPACING) 1.6
-set ::env(_WIDTH) 3
-
-set power_domains [list {vccd1 vssd1} {vccd2 vssd2} {vdda1 vssa1} {vdda2 vssa2}]
-
-set ::env(_VDD_NET_NAME) vccd1
-set ::env(_GND_NET_NAME) vssd1
-set ::env(_V_OFFSET) 14
-set ::env(_H_OFFSET) $::env(_V_OFFSET)
-set ::env(_V_PITCH) 180
-set ::env(_H_PITCH) 180
-set ::env(_V_PDN_OFFSET) 0
-set ::env(_H_PDN_OFFSET) 0
-
-foreach domain $power_domains {
-	set ::env(_VDD_NET_NAME) [lindex $domain 0]
-	set ::env(_GND_NET_NAME) [lindex $domain 1]
-	gen_pdn
-
-	set ::env(_V_OFFSET) \
-	[expr $::env(_V_OFFSET) + 2*($::env(_WIDTH)+$::env(_SPACING))]
-	set ::env(_H_OFFSET) \
-	[expr $::env(_H_OFFSET) + 2*($::env(_WIDTH)+$::env(_SPACING))]
-	set ::env(_V_PDN_OFFSET) [expr $::env(_V_PDN_OFFSET)+6*$::env(_WIDTH)]
-	set ::env(_H_PDN_OFFSET) [expr $::env(_H_PDN_OFFSET)+6*$::env(_WIDTH)]
-}
-
-global_routing_or
-detailed_routing
-
-run_magic
-run_magic_spice_export
-
-save_views       -lef_path $::env(magic_result_file_tag).lef \
-                 -def_path $::env(tritonRoute_result_file_tag).def \
-                 -gds_path $::env(magic_result_file_tag).gds \
-                 -mag_path $::env(magic_result_file_tag).mag \
-                 -save_path $save_path \
-                 -tag $::env(RUN_TAG)
-
-run_magic_drc
-
-run_lvs; # requires run_magic_spice_export
-
-run_antenna_check

openlane/user_project_wrapper_bak/pdn.tcl

diff --git a/openlane/user_project_wrapper_bak/pdn.tcl b/openlane/user_project_wrapper_bak/pdn.tcl
deleted file mode 100644
index f6d953c..0000000
--- a/openlane/user_project_wrapper_bak/pdn.tcl
+++ /dev/null
@@ -1,47 +0,0 @@
-# Power nets
-set ::power_nets $::env(_VDD_NET_NAME)
-set ::ground_nets $::env(_GND_NET_NAME)
-
-pdngen::specify_grid stdcell {
-    name grid
-	core_ring {
-		met5 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_H_OFFSET)}
-		met4 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_V_OFFSET)}
-	}
-	rails {
-	}
-    straps {
-	    met4 {width $::env(_WIDTH) pitch $::env(_V_PITCH) offset $::env(_V_PDN_OFFSET)}
-	    met5 {width $::env(_WIDTH) pitch $::env(_H_PITCH) offset $::env(_H_PDN_OFFSET)}
-    }
-    connect {{met4 met5}}
-}
-
-pdngen::specify_grid macro {
-	instance "obs_core_obs"
-    power_pins $::env(_VDD_NET_NAME)
-    ground_pins $::env(_GND_NET_NAME)
-    blockages "li1 met1 met2 met3 met4 met5"
-    straps { 
-    } 
-    connect {}
-}
-
-
-pdngen::specify_grid macro {
-    power_pins $::env(_VDD_NET_NAME)
-    ground_pins $::env(_GND_NET_NAME)
-    blockages ""
-    straps { 
-    } 
-    connect {}
-}
-
-set ::halo 0
-
-# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
-set ::rails_start_with "POWER" ;
-
-# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
-set ::stripes_start_with "POWER" ;
-

openlane/user_project_wrapper_bak/pin_order.cfg

diff --git a/openlane/user_project_wrapper_bak/pin_order.cfg b/openlane/user_project_wrapper_bak/pin_order.cfg
deleted file mode 120000
index 0717c4b..0000000
--- a/openlane/user_project_wrapper_bak/pin_order.cfg
+++ /dev/null
@@ -1 +0,0 @@
-../user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file